--! @file ap_n_dpc.vhd
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--! @file ap_n_dpc.vhd
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--! @brief Decodificador de operacién. Sistema de decodificación de los \kdatapaths, cuyo objetivo es a partir del par´ametro de entrada DCS.\nSon 4 las posibles configuraciones de \kdatapaths que existen. Los valores de los bits DC son los que determinan y decodifican la interconexión entre los componentes aritméticos. El componente S determina el signo de la operación cuando es una suma la que operación se eséa; ejecutando en el momento.
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--! @brief Decodificador de operacién. Sistema de decodificación de los \kdatapaths, cuyo objetivo es a partir del par´ametro de entrada DCS.\nSon 4 las posibles configuraciones de \kdatapaths que existen. Los valores de los bits DC son los que determinan y decodifican la interconexión entre los componentes aritméticos. El componente S determina el signo de la operación cuando es una suma la que operación se eséa; ejecutando en el momento.
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--! @author Julián Andrés Guarín Reyes
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--! @author Julián Andrés Guarín Reyes
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--------------------------------------------------------------
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--------------------------------------------------------------
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-- RAYTRAC
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-- RAYTRAC
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-- Author Julian Andres Guarin
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-- Author Julian Andres Guarin
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-- ap_n_dpc.vhd
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-- ap_n_dpc.vhd
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-- This file is part of raytrac.
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-- This file is part of raytrac.
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--
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--
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-- raytrac is free software: you can redistribute it and/or modify
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-- raytrac is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- raytrac is distributed in the hope that it will be useful,
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-- raytrac is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.arithpack.all;
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use work.arithpack.all;
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|
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library altera_mf;
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library altera_mf;
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use altera_mf.altera_mf_components.all;
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use altera_mf.altera_mf_components.all;
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entity ap_n_dpc is
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entity ap_n_dpc is
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port (
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port (
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p0,p1,p2,p3,p4,p5,p6,p7,p8: out std_logic_vector(31 downto 0);
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p0,p1,p2,p3,p4,p5,p6,p7,p8: out std_logic_vector(31 downto 0);
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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ax : in std_logic_vector(31 downto 0);
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ax : in std_logic_vector(31 downto 0);
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ay : in std_logic_vector(31 downto 0);
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ay : in std_logic_vector(31 downto 0);
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az : in std_logic_vector(31 downto 0);
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az : in std_logic_vector(31 downto 0);
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bx : in std_logic_vector(31 downto 0);
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bx : in std_logic_vector(31 downto 0);
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by : in std_logic_vector(31 downto 0);
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by : in std_logic_vector(31 downto 0);
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bz : in std_logic_vector(31 downto 0);
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bz : in std_logic_vector(31 downto 0);
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vx : out std_logic_vector(31 downto 0);
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vx : out std_logic_vector(31 downto 0);
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vy : out std_logic_vector(31 downto 0);
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vy : out std_logic_vector(31 downto 0);
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vz : out std_logic_vector(31 downto 0);
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vz : out std_logic_vector(31 downto 0);
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sc : out std_logic_vector(31 downto 0);
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sc : out std_logic_vector(31 downto 0);
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ack : in std_logic;
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ack : in std_logic;
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empty : out std_logic;
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empty : out std_logic;
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sign_switcheroo : in std_logic;
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sign_switcheroo : in std_logic;
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--paraminput : in vectorblock06; --! Vectores A,B
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--paraminput : in vectorblock06; --! Vectores A,B
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dcs : in std_logic_vector(2 downto 0); --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
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dcs : in std_logic_vector(2 downto 0); --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
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sync_chain_1 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.
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sync_chain_1 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.
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pipeline_pending : out std_logic --! Señal para indicar si hay datos en el pipeline aritmético.
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pipeline_pending : out std_logic --! Señal para indicar si hay datos en el pipeline aritmético.
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--qresult_d : out vectorblock04 --! 4 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.
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--qresult_d : out vectorblock04 --! 4 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.
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);
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);
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end entity;
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end entity;
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architecture ap_n_dpc_arch of ap_n_dpc is
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architecture ap_n_dpc_arch of ap_n_dpc is
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--!Constantes de apoyo
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--!Constantes de apoyo
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constant ssync_chain_max : integer :=32;
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constant ssync_chain_max : integer :=32;
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constant ssync_chain_min : integer :=2;
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constant ssync_chain_min : integer :=2;
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--! Tunnning delay
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--! Tunnning delay
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constant adder2_delay: integer := 1;
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constant adder2_delay: integer := 1;
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constant adder1_delay : integer := 1;
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constant adder1_delay : integer := 1;
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--!TBXSTART:FACTORS_N_ADDENDS
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--!TBXSTART:FACTORS_N_ADDENDS
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signal sfactor0 : std_logic_vector(31 downto 0);
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signal sfactor0 : std_logic_vector(31 downto 0);
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signal sfactor1 : std_logic_vector(31 downto 0);
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signal sfactor1 : std_logic_vector(31 downto 0);
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signal sfactor2 : std_logic_vector(31 downto 0);
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signal sfactor2 : std_logic_vector(31 downto 0);
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signal sfactor3 : std_logic_vector(31 downto 0);
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signal sfactor3 : std_logic_vector(31 downto 0);
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signal sfactor4 : std_logic_vector(31 downto 0);
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signal sfactor4 : std_logic_vector(31 downto 0);
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signal sfactor5 : std_logic_vector(31 downto 0);
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signal sfactor5 : std_logic_vector(31 downto 0);
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signal sfactor6 : std_logic_vector(31 downto 0);
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signal sfactor6 : std_logic_vector(31 downto 0);
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signal sfactor7 : std_logic_vector(31 downto 0);
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signal sfactor7 : std_logic_vector(31 downto 0);
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signal sfactor8 : std_logic_vector(31 downto 0);
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signal sfactor8 : std_logic_vector(31 downto 0);
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signal sfactor9 : std_logic_vector(31 downto 0);
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signal sfactor9 : std_logic_vector(31 downto 0);
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signal sfactor10 : std_logic_vector(31 downto 0);
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signal sfactor10 : std_logic_vector(31 downto 0);
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signal sfactor11 : std_logic_vector(31 downto 0);
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signal sfactor11 : std_logic_vector(31 downto 0);
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--signal sfactor : vectorblock12;
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--signal sfactor : vectorblock12;
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signal ssumando0 : std_logic_vector(31 downto 0);
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signal ssumando0 : std_logic_vector(31 downto 0);
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signal ssumando1 : std_logic_vector(31 downto 0);
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signal ssumando1 : std_logic_vector(31 downto 0);
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signal ssumando2 : std_logic_vector(31 downto 0);
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signal ssumando2 : std_logic_vector(31 downto 0);
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signal ssumando3 : std_logic_vector(31 downto 0);
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signal ssumando3 : std_logic_vector(31 downto 0);
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signal ssumando4 : std_logic_vector(31 downto 0);
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signal ssumando4 : std_logic_vector(31 downto 0);
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signal ssumando5 : std_logic_vector(31 downto 0);
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signal ssumando5 : std_logic_vector(31 downto 0);
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--signal ssumando : vectorblock06;
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--signal ssumando : vectorblock06;
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signal sq0_q : std_logic_vector(31 downto 0);
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signal sq0_q : std_logic_vector(31 downto 0);
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--!TBXEND
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--!TBXEND
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--!TBXSTART:ARITHMETIC_RESULTS
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--!TBXSTART:ARITHMETIC_RESULTS
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signal sp0 : std_logic_vector(31 downto 0);
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signal sp0 : std_logic_vector(31 downto 0);
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signal sp1 : std_logic_vector(31 downto 0);
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signal sp1 : std_logic_vector(31 downto 0);
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signal sp2 : std_logic_vector(31 downto 0);
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signal sp2 : std_logic_vector(31 downto 0);
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signal sp3 : std_logic_vector(31 downto 0);
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signal sp3 : std_logic_vector(31 downto 0);
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signal sp4 : std_logic_vector(31 downto 0);
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signal sp4 : std_logic_vector(31 downto 0);
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signal sp5 : std_logic_vector(31 downto 0);
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signal sp5 : std_logic_vector(31 downto 0);
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--signal sprd32blk : vectorblock06;
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--signal sprd32blk : vectorblock06;
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signal sa0 : std_logic_vector(31 downto 0);
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signal sa0 : std_logic_vector(31 downto 0);
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signal sa1 : std_logic_vector(31 downto 0);
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signal sa1 : std_logic_vector(31 downto 0);
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signal sa2 : std_logic_vector(31 downto 0);
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signal sa2 : std_logic_vector(31 downto 0);
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--signal sadd32blk : vectorblock03;
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--signal sadd32blk : vectorblock03;
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signal ssq32 : std_logic_vector(31 downto 0);
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signal ssq32 : std_logic_vector(31 downto 0);
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signal sinv32 : std_logic_vector(31 downto 0);
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signal sinv32 : std_logic_vector(31 downto 0);
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signal sqx_q : std_logic_vector(31 downto 0);
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signal sqx_q : std_logic_vector(31 downto 0);
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signal sqy_q : std_logic_vector(31 downto 0);
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signal sqy_q : std_logic_vector(31 downto 0);
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signal sqz_q : std_logic_vector(31 downto 0);
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signal sqz_q : std_logic_vector(31 downto 0);
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--signal sqxyz_q : vectorblock03;
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--signal sqxyz_q : vectorblock03;
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signal sq1_e : std_logic;
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signal sq1_e : std_logic;
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--!TBXEND
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--!TBXEND
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--!TBXSTART:SYNC_CHAIN
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--!TBXSTART:SYNC_CHAIN
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signal ssync_chain : std_logic_vector(ssync_chain_max downto ssync_chain_min);
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signal ssync_chain : std_logic_vector(ssync_chain_max downto ssync_chain_min);
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--!TBXEND
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--!TBXEND
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--signal qxyzd : std_logic_vector(95 downto 0);
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--signal qxyzd : std_logic_vector(95 downto 0);
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--signal qxyzq : std_logic_vector(95 downto 0);
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--signal qxyzq : std_logic_vector(95 downto 0);
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signal sq2_d : std_logic_vector(31 downto 0);
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signal sq2_d : std_logic_vector(31 downto 0);
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signal sq2_q : std_logic_vector(31 downto 0);
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signal sq2_q : std_logic_vector(31 downto 0);
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signal sq2_w : std_logic;
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signal sq2_w : std_logic;
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signal sq2_e : std_logic;
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signal sq2_e : std_logic;
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signal sqr_e : std_logic;
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signal sqr_e : std_logic;
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signal sqr_w : std_logic; --! Salidas de escritura y lectura en las colas de resultados.
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signal sqr_w : std_logic; --! Salidas de escritura y lectura en las colas de resultados.
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signal sqr_dx : std_logic_vector(31 downto 0);
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signal sqr_dx : std_logic_vector(31 downto 0);
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signal sqr_dy : std_logic_vector(31 downto 0);
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signal sqr_dy : std_logic_vector(31 downto 0);
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signal sqr_dz : std_logic_vector(31 downto 0);
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signal sqr_dz : std_logic_vector(31 downto 0);
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signal sqr_dsc : std_logic_vector(31 downto 0);
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signal sqr_dsc : std_logic_vector(31 downto 0);
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signal sa0o : std_logic_vector(31 downto 0);
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signal sa0o : std_logic_vector(31 downto 0);
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signal sa1o : std_logic_vector(31 downto 0);
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signal sa1o : std_logic_vector(31 downto 0);
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signal sa2o : std_logic_vector(31 downto 0);
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signal sa2o : std_logic_vector(31 downto 0);
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--signal sadd32blko : vectorblock03; --! Salidas de los 3 sumadores.
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--signal sadd32blko : vectorblock03; --! Salidas de los 3 sumadores.
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signal sp0o : std_logic_vector(31 downto 0);
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signal sp0o : std_logic_vector(31 downto 0);
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signal sp1o : std_logic_vector(31 downto 0);
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signal sp1o : std_logic_vector(31 downto 0);
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signal sp2o : std_logic_vector(31 downto 0);
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signal sp2o : std_logic_vector(31 downto 0);
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signal sp3o : std_logic_vector(31 downto 0);
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signal sp3o : std_logic_vector(31 downto 0);
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signal sp4o : std_logic_vector(31 downto 0);
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signal sp4o : std_logic_vector(31 downto 0);
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signal sp5o : std_logic_vector(31 downto 0);
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signal sp5o : std_logic_vector(31 downto 0);
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--signal sprd32blko : vectorblock06; --! Salidas de los 6 multiplicadores.
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--signal sprd32blko : vectorblock06; --! Salidas de los 6 multiplicadores.
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signal sinv32o : std_logic_vector(31 downto 0); --! Salidas de la raiz cuadradas y el inversor.
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signal sinv32o : std_logic_vector(31 downto 0); --! Salidas de la raiz cuadradas y el inversor.
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signal ssq32o : std_logic_vector(31 downto 0); --! Salidas de la raiz cuadradas y el inversor.
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signal ssq32o : std_logic_vector(31 downto 0); --! Salidas de la raiz cuadradas y el inversor.
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--! Bloque Aritmetico de Sumadores y Multiplicadores (madd)
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--! Bloque Aritmetico de Sumadores y Multiplicadores (madd)
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component arithblock
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component arithblock
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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sign : in std_logic;
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sign : in std_logic;
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sign_switch : in std_logic;
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sign_switch : in std_logic;
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factor0 : in std_logic_vector(31 downto 0);
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factor0 : in std_logic_vector(31 downto 0);
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factor1 : in std_logic_vector(31 downto 0);
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factor1 : in std_logic_vector(31 downto 0);
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factor2 : in std_logic_vector(31 downto 0);
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factor2 : in std_logic_vector(31 downto 0);
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factor3 : in std_logic_vector(31 downto 0);
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factor3 : in std_logic_vector(31 downto 0);
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factor4 : in std_logic_vector(31 downto 0);
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factor4 : in std_logic_vector(31 downto 0);
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factor5 : in std_logic_vector(31 downto 0);
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factor5 : in std_logic_vector(31 downto 0);
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factor6 : in std_logic_vector(31 downto 0);
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factor6 : in std_logic_vector(31 downto 0);
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factor7 : in std_logic_vector(31 downto 0);
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factor7 : in std_logic_vector(31 downto 0);
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factor8 : in std_logic_vector(31 downto 0);
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factor8 : in std_logic_vector(31 downto 0);
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factor9 : in std_logic_vector(31 downto 0);
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factor9 : in std_logic_vector(31 downto 0);
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factor10 : in std_logic_vector(31 downto 0);
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factor10 : in std_logic_vector(31 downto 0);
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factor11 : in std_logic_vector(31 downto 0);
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factor11 : in std_logic_vector(31 downto 0);
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--prd32blki : in vectorblock06;
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--prd32blki : in vectorblock06;
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sumando0 : in std_logic_vector(31 downto 0);
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sumando0 : in std_logic_vector(31 downto 0);
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sumando1 : in std_logic_vector(31 downto 0);
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sumando1 : in std_logic_vector(31 downto 0);
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sumando2 : in std_logic_vector(31 downto 0);
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sumando2 : in std_logic_vector(31 downto 0);
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sumando3 : in std_logic_vector(31 downto 0);
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sumando3 : in std_logic_vector(31 downto 0);
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sumando4 : in std_logic_vector(31 downto 0);
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sumando4 : in std_logic_vector(31 downto 0);
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sumando5 : in std_logic_vector(31 downto 0);
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sumando5 : in std_logic_vector(31 downto 0);
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--add32blki : in vectorblock06;
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--add32blki : in vectorblock06;
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a0 : out std_logic_vector(31 downto 0);
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a0 : out std_logic_vector(31 downto 0);
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a1 : out std_logic_vector(31 downto 0);
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a1 : out std_logic_vector(31 downto 0);
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a2 : out std_logic_vector(31 downto 0);
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a2 : out std_logic_vector(31 downto 0);
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--add32blko : out vectorblock03;
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--add32blko : out vectorblock03;
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p0 : out std_logic_vector(31 downto 0);
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p0 : out std_logic_vector(31 downto 0);
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p1 : out std_logic_vector(31 downto 0);
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p1 : out std_logic_vector(31 downto 0);
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p2 : out std_logic_vector(31 downto 0);
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p2 : out std_logic_vector(31 downto 0);
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p3 : out std_logic_vector(31 downto 0);
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p3 : out std_logic_vector(31 downto 0);
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p4 : out std_logic_vector(31 downto 0);
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p4 : out std_logic_vector(31 downto 0);
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p5 : out std_logic_vector(31 downto 0);
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p5 : out std_logic_vector(31 downto 0);
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--prd32blko : out vectorblock06;
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--prd32blko : out vectorblock06;
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sq32o : out std_logic_vector(31 downto 0);
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sq32o : out std_logic_vector(31 downto 0);
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inv32o : out std_logic_vector(31 downto 0)
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inv32o : out std_logic_vector(31 downto 0)
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|
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);
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);
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end component;
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end component;
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|
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begin
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begin
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|
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--! Bloque Aritmético
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--! Bloque Aritmético
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ap : arithblock
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ap : arithblock
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port map (
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port map (
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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|
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sign => dcs(0),
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sign => dcs(0),
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sign_switch => sign_switcheroo,
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factor0 =>sfactor0,
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factor0 =>sfactor0,
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factor1 =>sfactor1,
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factor1 =>sfactor1,
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factor2 =>sfactor2,
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factor2 =>sfactor2,
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factor3 =>sfactor3,
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factor3 =>sfactor3,
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factor4 =>sfactor4,
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factor4 =>sfactor4,
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factor5 =>sfactor5,
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factor5 =>sfactor5,
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factor6 =>sfactor6,
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factor6 =>sfactor6,
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factor7 =>sfactor7,
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factor7 =>sfactor7,
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factor8 =>sfactor8,
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factor8 =>sfactor8,
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factor9 =>sfactor9,
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factor9 =>sfactor9,
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factor10=>sfactor10,
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factor10=>sfactor10,
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factor11=>sfactor11,
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factor11=>sfactor11,
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--prd32blki => sfactor,
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--prd32blki => sfactor,
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|
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sumando0=>ssumando0,
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sumando0=>ssumando0,
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sumando1=>ssumando1,
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sumando1=>ssumando1,
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sumando2=>ssumando2,
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sumando2=>ssumando2,
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sumando3=>ssumando3,
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sumando3=>ssumando3,
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sumando4=>ssumando4,
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sumando4=>ssumando4,
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sumando5=>ssumando5,
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sumando5=>ssumando5,
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--add32blki => ssumando,
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--add32blki => ssumando,
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|
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a0=>sa0o,
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a0=>sa0o,
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a1=>sa1o,
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a1=>sa1o,
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a2=>sa2o,
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a2=>sa2o,
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--add32blko => sadd32blko,
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--add32blko => sadd32blko,
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|
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p0=>sp0o,
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p0=>sp0o,
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p1=>sp1o,
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p1=>sp1o,
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p2=>sp2o,
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p2=>sp2o,
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p3=>sp3o,
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p3=>sp3o,
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p4=>sp4o,
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p4=>sp4o,
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p5=>sp5o,
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p5=>sp5o,
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--prd32blko => sprd32blko,
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--prd32blko => sprd32blko,
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|
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sq32o=> ssq32o,
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sq32o=> ssq32o,
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inv32o=> sinv32o
|
inv32o=> sinv32o
|
);
|
);
|
|
|
--! Cadena de sincronización: 29 posiciones.
|
--! Cadena de sincronización: 29 posiciones.
|
pipeline_pending <= sync_chain_1 or not(sq2_e) or not(sq1_e) or not(sqr_e);
|
pipeline_pending <= sync_chain_1 or not(sq2_e) or not(sq1_e) or not(sqr_e);
|
empty <= sqr_e;
|
empty <= sqr_e;
|
sync_chain_proc:
|
sync_chain_proc:
|
process(clk,rst,sync_chain_1)
|
process(clk,rst,sync_chain_1)
|
begin
|
begin
|
if rst=rstMasterValue then
|
if rst=rstMasterValue then
|
ssync_chain(ssync_chain_max downto ssync_chain_min) <= (others => '0');
|
ssync_chain(ssync_chain_max downto ssync_chain_min) <= (others => '0');
|
|
|
p0 <= (others => '0');
|
p0 <= (others => '0');
|
p1 <= (others => '0');
|
p1 <= (others => '0');
|
p2 <= (others => '0');
|
p2 <= (others => '0');
|
|
|
elsif clk'event and clk='1' then
|
elsif clk'event and clk='1' then
|
for i in ssync_chain_max downto ssync_chain_min+1 loop
|
for i in ssync_chain_max downto ssync_chain_min+1 loop
|
ssync_chain(i) <= ssync_chain(i-1);
|
ssync_chain(i) <= ssync_chain(i-1);
|
end loop;
|
end loop;
|
ssync_chain(ssync_chain_min) <= sync_chain_1;
|
ssync_chain(ssync_chain_min) <= sync_chain_1;
|
|
|
--! Salida de los multiplicadores p0 p1 p2
|
--! Salida de los multiplicadores p0 p1 p2
|
if ssync_chain(23)='1' then
|
if ssync_chain(23)='1' then
|
p0 <= ssq32; -- El resultado quedara consignado en VZ1=BASE+1
|
p0 <= ssq32; -- El resultado quedara consignado en VZ1=BASE+1
|
elsif ssync_chain(28)='1' then
|
elsif ssync_chain(28)='1' then
|
p1 <= sq2_q; -- El resultado quedara consignado en VX1=BASE+3
|
p1 <= sq2_q; -- El resultado quedara consignado en VX1=BASE+3
|
elsif ssync_chain(24)='1' then
|
elsif ssync_chain(24)='1' then
|
p2 <= sinv32; -- El resutlado quedara consignado en VY1=BASE+2
|
p2 <= sinv32; -- El resutlado quedara consignado en VY1=BASE+2
|
p3 <= sqx_q;
|
p3 <= sqx_q;
|
p4 <= sqy_q;
|
p4 <= sqy_q;
|
p5 <= sqz_q;
|
p5 <= sqz_q;
|
elsif ssync_chain(28)='1' then
|
elsif ssync_chain(28)='1' then
|
p6 <= sp3o;
|
p6 <= sp3o;
|
p7 <= sp4o;
|
p7 <= sp4o;
|
p8 <= sp5o;
|
p8 <= sp5o;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end process sync_chain_proc;
|
end process sync_chain_proc;
|
|
|
|
|
|
|
|
|
|
|
--! El siguiente código sirve para conectar arreglos a señales std_logic_1164, son abstracciones de código también, sin embargo se realizan a través de registros.
|
--! El siguiente código sirve para conectar arreglos a señales std_logic_1164, son abstracciones de código también, sin embargo se realizan a través de registros.
|
register_products_outputs:
|
register_products_outputs:
|
process (clk)
|
process (clk)
|
begin
|
begin
|
if clk'event and clk='1' then
|
if clk'event and clk='1' then
|
sp0 <= sp0o;
|
sp0 <= sp0o;
|
sp1 <= sp1o;
|
sp1 <= sp1o;
|
sp2 <= sp2o;
|
sp2 <= sp2o;
|
sp3 <= sp3o;
|
sp3 <= sp3o;
|
sp4 <= sp4o;
|
sp4 <= sp4o;
|
sp5 <= sp5o;
|
sp5 <= sp5o;
|
sa0 <= sa0o;
|
sa0 <= sa0o;
|
sa1 <= sa1o;
|
sa1 <= sa1o;
|
sa2 <= sa2o;
|
sa2 <= sa2o;
|
sinv32 <= sinv32o;
|
sinv32 <= sinv32o;
|
ssq32 <= ssq32o;
|
ssq32 <= ssq32o;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
--! Decodificación del Datapath.
|
--! Decodificación del Datapath.
|
datapathproc:process(dcs,ax,bx,ay,by,az,bz,sinv32,sp0,sp1,sp2,sp3,sp4,sp5,sa0,sa1,sa2,sq0_q,sqx_q,sqy_q,sqz_q,ssync_chain,ssq32,sq2_q)
|
datapathproc:process(dcs,ax,bx,ay,by,az,bz,sinv32,sp0,sp1,sp2,sp3,sp4,sp5,sa0,sa1,sa2,sq0_q,sqx_q,sqy_q,sqz_q,ssync_chain,ssq32,sq2_q)
|
begin
|
begin
|
|
|
case dcs is
|
case dcs is
|
when "011" =>
|
when "011" =>
|
|
|
sq2_w <= '0';
|
sq2_w <= '0';
|
sq2_d <= ssq32;
|
sq2_d <= ssq32;
|
|
|
sfactor0 <= ay;
|
sfactor0 <= ay;
|
sfactor1 <= bz;
|
sfactor1 <= bz;
|
sfactor2 <= az;
|
sfactor2 <= az;
|
sfactor3 <= by;
|
sfactor3 <= by;
|
sfactor4 <= az;
|
sfactor4 <= az;
|
sfactor5 <= bx;
|
sfactor5 <= bx;
|
sfactor6 <= ax;
|
sfactor6 <= ax;
|
sfactor7 <= bz;
|
sfactor7 <= bz;
|
sfactor8 <= ax;
|
sfactor8 <= ax;
|
sfactor9 <= by;
|
sfactor9 <= by;
|
sfactor10 <= ay;
|
sfactor10 <= ay;
|
sfactor11 <= bx;
|
sfactor11 <= bx;
|
|
|
ssumando0 <= sp0;
|
ssumando0 <= sp0;
|
ssumando1 <= sp1;
|
ssumando1 <= sp1;
|
ssumando2 <= sp2;
|
ssumando2 <= sp2;
|
ssumando3 <= sp3;
|
ssumando3 <= sp3;
|
ssumando4 <= sp4;
|
ssumando4 <= sp4;
|
ssumando5 <= sp5;
|
ssumando5 <= sp5;
|
|
|
sqr_dx <= sa0;
|
sqr_dx <= sa0;
|
sqr_dy <= sa1;
|
sqr_dy <= sa1;
|
sqr_dz <= sa2;
|
sqr_dz <= sa2;
|
|
|
sqr_w <= ssync_chain(13+adder2_delay);
|
sqr_w <= ssync_chain(13+adder2_delay);
|
|
|
when"000"|"001" =>
|
when"000"|"001" =>
|
|
|
sq2_w <= '0';
|
sq2_w <= '0';
|
sq2_d <= ssq32;
|
sq2_d <= ssq32;
|
|
|
sfactor0 <= ay;
|
sfactor0 <= ay;
|
sfactor1 <= bz;
|
sfactor1 <= bz;
|
sfactor2 <= az;
|
sfactor2 <= az;
|
sfactor3 <= by;
|
sfactor3 <= by;
|
sfactor4 <= az;
|
sfactor4 <= az;
|
sfactor5 <= bx;
|
sfactor5 <= bx;
|
sfactor6 <= ax;
|
sfactor6 <= ax;
|
sfactor7 <= bz;
|
sfactor7 <= bz;
|
sfactor8 <= ax;
|
sfactor8 <= ax;
|
sfactor9 <= by;
|
sfactor9 <= by;
|
sfactor10 <= ay;
|
sfactor10 <= ay;
|
sfactor11 <= bx;
|
sfactor11 <= bx;
|
|
|
|
|
ssumando0 <= ax;
|
ssumando0 <= ax;
|
ssumando1 <= bx;
|
ssumando1 <= bx;
|
ssumando2 <= ay;
|
ssumando2 <= ay;
|
ssumando3 <= by;
|
ssumando3 <= by;
|
ssumando4 <= az;
|
ssumando4 <= az;
|
ssumando5 <= bz;
|
ssumando5 <= bz;
|
|
|
sqr_dx <= sa0;
|
sqr_dx <= sa0;
|
sqr_dy <= sa1;
|
sqr_dy <= sa1;
|
sqr_dz <= sa2;
|
sqr_dz <= sa2;
|
|
|
sqr_w <= ssync_chain(9+adder2_delay);
|
sqr_w <= ssync_chain(9+adder2_delay);
|
|
|
when"110" |"100" =>
|
when"110" |"100" =>
|
|
|
|
|
|
|
sfactor0 <= ax;
|
sfactor0 <= ax;
|
sfactor1 <= bx;
|
sfactor1 <= bx;
|
sfactor2 <= ay;
|
sfactor2 <= ay;
|
sfactor3 <= by;
|
sfactor3 <= by;
|
sfactor4 <= az;
|
sfactor4 <= az;
|
sfactor5 <= bz;
|
sfactor5 <= bz;
|
|
|
sfactor6 <= sinv32;
|
sfactor6 <= sinv32;
|
sfactor7 <= sqx_q;
|
sfactor7 <= sqx_q;
|
sfactor8 <= sinv32;
|
sfactor8 <= sinv32;
|
sfactor9 <= sqy_q;
|
sfactor9 <= sqy_q;
|
sfactor10 <= sinv32;
|
sfactor10 <= sinv32;
|
sfactor11 <= sqz_q;
|
sfactor11 <= sqz_q;
|
|
|
|
|
ssumando0 <= sp0;
|
ssumando0 <= sp0;
|
ssumando1 <= sp1;
|
ssumando1 <= sp1;
|
ssumando2 <= sa0;
|
ssumando2 <= sa0;
|
ssumando3 <= sq0_q;
|
ssumando3 <= sq0_q;
|
ssumando4 <= az;
|
ssumando4 <= az;
|
ssumando5 <= bz;
|
ssumando5 <= bz;
|
|
|
if dcs(1)='1' then
|
if dcs(1)='1' then
|
sq2_d <= ssq32;
|
sq2_d <= ssq32;
|
sq2_w <= ssync_chain(22+adder1_delay);
|
sq2_w <= ssync_chain(22+adder1_delay);
|
else
|
else
|
sq2_d <= sa1;
|
sq2_d <= sa1;
|
sq2_w <= ssync_chain(21+adder1_delay);
|
sq2_w <= ssync_chain(21+adder1_delay);
|
end if;
|
end if;
|
|
|
sqr_dx <= sp3;
|
sqr_dx <= sp3;
|
sqr_dy <= sp4;
|
sqr_dy <= sp4;
|
sqr_dz <= sp5;
|
sqr_dz <= sp5;
|
|
|
sqr_w <= ssync_chain(27+adder1_delay);
|
sqr_w <= ssync_chain(27+adder1_delay);
|
|
|
when others =>
|
when others =>
|
|
|
sq2_w <= '0';
|
sq2_w <= '0';
|
sq2_d <= ssq32;
|
sq2_d <= ssq32;
|
|
|
sfactor0 <= ax;
|
sfactor0 <= ax;
|
sfactor1 <= bx;
|
sfactor1 <= bx;
|
sfactor2 <= ay;
|
sfactor2 <= ay;
|
sfactor3 <= by;
|
sfactor3 <= by;
|
sfactor4 <= az;
|
sfactor4 <= az;
|
sfactor5 <= bz;
|
sfactor5 <= bz;
|
|
|
sfactor6 <= ax;
|
sfactor6 <= ax;
|
sfactor7 <= bx;
|
sfactor7 <= bx;
|
sfactor8 <= ay;
|
sfactor8 <= ay;
|
sfactor9 <= by;
|
sfactor9 <= by;
|
sfactor10 <= az;
|
sfactor10 <= az;
|
sfactor11 <= bz;
|
sfactor11 <= bz;
|
|
|
ssumando0 <= sp0;
|
ssumando0 <= sp0;
|
ssumando1 <= sp1;
|
ssumando1 <= sp1;
|
ssumando2 <= sa0;
|
ssumando2 <= sa0;
|
ssumando3 <= sq0_q;
|
ssumando3 <= sq0_q;
|
ssumando4 <= az;
|
ssumando4 <= az;
|
ssumando5 <= bz;
|
ssumando5 <= bz;
|
|
|
sqr_dx <= sp3;
|
sqr_dx <= sp3;
|
sqr_dy <= sp4;
|
sqr_dy <= sp4;
|
sqr_dz <= sp5;
|
sqr_dz <= sp5;
|
|
|
sqr_w <= ssync_chain(5);
|
sqr_w <= ssync_chain(5);
|
|
|
end case;
|
end case;
|
|
|
|
|
|
|
|
|
end process;
|
end process;
|
|
|
--! Colas internas de producto punto, ubicada en el pipe line aritméco. Paralelo a los sumadores a0 y a2.
|
--! Colas internas de producto punto, ubicada en el pipe line aritméco. Paralelo a los sumadores a0 y a2.
|
q0 : scfifo --! Debe ir registrada la salida.
|
q0 : scfifo --! Debe ir registrada la salida.
|
generic map (
|
generic map (
|
allow_rwcycle_when_full => "ON",
|
allow_rwcycle_when_full => "ON",
|
lpm_widthu => 4,
|
lpm_widthu => 4,
|
lpm_numwords => 16,
|
lpm_numwords => 16,
|
lpm_showahead => "ON",
|
lpm_showahead => "ON",
|
lpm_width => 32,
|
lpm_width => 32,
|
overflow_checking => "ON",
|
overflow_checking => "ON",
|
underflow_checking => "ON",
|
underflow_checking => "ON",
|
use_eab => "ON"
|
use_eab => "ON"
|
)
|
)
|
port map (
|
port map (
|
sclr => '0',
|
sclr => '0',
|
clock => clk,
|
clock => clk,
|
rdreq => ssync_chain(13),
|
rdreq => ssync_chain(13),
|
wrreq => ssync_chain(5),
|
wrreq => ssync_chain(5),
|
data => sp2,
|
data => sp2,
|
q => sq0_q
|
q => sq0_q
|
);
|
);
|
--! Colas internas de producto punto, ubicada en el pipe line aritméco. Paralelo a los sumadores a0 y a2.
|
--! Colas internas de producto punto, ubicada en el pipe line aritméco. Paralelo a los sumadores a0 y a2.
|
q2 : scfifo --! Debe ir registrada la salida.
|
q2 : scfifo --! Debe ir registrada la salida.
|
generic map (
|
generic map (
|
allow_rwcycle_when_full => "ON",
|
allow_rwcycle_when_full => "ON",
|
lpm_widthu => 4,
|
lpm_widthu => 4,
|
lpm_numwords => 16,
|
lpm_numwords => 16,
|
lpm_showahead => "ON",
|
lpm_showahead => "ON",
|
lpm_type => "SCIFIFO",
|
lpm_type => "SCIFIFO",
|
lpm_width => 32,
|
lpm_width => 32,
|
overflow_checking => "ON",
|
overflow_checking => "ON",
|
underflow_checking => "ON",
|
underflow_checking => "ON",
|
use_eab => "ON"
|
use_eab => "ON"
|
)
|
)
|
port map (
|
port map (
|
rdreq => ssync_chain(28),
|
rdreq => ssync_chain(28),
|
sclr => '0',
|
sclr => '0',
|
clock => clk,
|
clock => clk,
|
empty => sq2_e,
|
empty => sq2_e,
|
q => sqr_dsc,
|
q => sqr_dsc,
|
wrreq => sq2_w,
|
wrreq => sq2_w,
|
data => sq2_d
|
data => sq2_d
|
);
|
);
|
|
|
--! Cola interna de normalización de vectores, ubicada entre el pipeline aritmético
|
--! Cola interna de normalización de vectores, ubicada entre el pipeline aritmético
|
qx : scfifo
|
qx : scfifo
|
generic map (
|
generic map (
|
allow_rwcycle_when_full => "ON",
|
allow_rwcycle_when_full => "ON",
|
lpm_widthu => 5,
|
lpm_widthu => 5,
|
lpm_numwords => 32,
|
lpm_numwords => 32,
|
lpm_showahead => "ON",
|
lpm_showahead => "ON",
|
lpm_width => 32,
|
lpm_width => 32,
|
overflow_checking => "ON",
|
overflow_checking => "ON",
|
underflow_checking => "ON",
|
underflow_checking => "ON",
|
use_eab => "ON"
|
use_eab => "ON"
|
)
|
)
|
port map (
|
port map (
|
aclr => '0',
|
aclr => '0',
|
clock => clk,
|
clock => clk,
|
empty => sq1_e,
|
empty => sq1_e,
|
rdreq => ssync_chain(23+adder1_delay),
|
rdreq => ssync_chain(23+adder1_delay),
|
wrreq => sync_chain_1,
|
wrreq => sync_chain_1,
|
data => ax,
|
data => ax,
|
q => sqx_q
|
q => sqx_q
|
);
|
);
|
qy : scfifo
|
qy : scfifo
|
generic map (
|
generic map (
|
allow_rwcycle_when_full => "ON",
|
allow_rwcycle_when_full => "ON",
|
lpm_widthu => 5,
|
lpm_widthu => 5,
|
lpm_numwords => 32,
|
lpm_numwords => 32,
|
lpm_showahead => "ON",
|
lpm_showahead => "ON",
|
lpm_width => 32,
|
lpm_width => 32,
|
overflow_checking => "ON",
|
overflow_checking => "ON",
|
underflow_checking => "ON",
|
underflow_checking => "ON",
|
use_eab => "ON"
|
use_eab => "ON"
|
)
|
)
|
port map (
|
port map (
|
aclr => '0',
|
aclr => '0',
|
clock => clk,
|
clock => clk,
|
rdreq => ssync_chain(23+adder1_delay),
|
rdreq => ssync_chain(23+adder1_delay),
|
wrreq => sync_chain_1,
|
wrreq => sync_chain_1,
|
data => ay,
|
data => ay,
|
q => sqy_q
|
q => sqy_q
|
);
|
);
|
qz : scfifo
|
qz : scfifo
|
generic map (
|
generic map (
|
allow_rwcycle_when_full => "ON",
|
allow_rwcycle_when_full => "ON",
|
lpm_widthu => 5,
|
lpm_widthu => 5,
|
lpm_numwords => 32,
|
lpm_numwords => 32,
|
lpm_showahead => "ON",
|
lpm_showahead => "ON",
|
lpm_width => 32,
|
lpm_width => 32,
|
overflow_checking => "ON",
|
overflow_checking => "ON",
|
underflow_checking => "ON",
|
underflow_checking => "ON",
|
use_eab => "ON"
|
use_eab => "ON"
|
)
|
)
|
port map (
|
port map (
|
aclr => '0',
|
aclr => '0',
|
clock => clk,
|
clock => clk,
|
rdreq => ssync_chain(23+adder1_delay),
|
rdreq => ssync_chain(23+adder1_delay),
|
wrreq => sync_chain_1,
|
wrreq => sync_chain_1,
|
data => az,
|
data => az,
|
q => sqz_q
|
q => sqz_q
|
);
|
);
|
--!***********************************************************************************************************
|
--!***********************************************************************************************************
|
--!Q RESULT
|
--!Q RESULT
|
--!***********************************************************************************************************
|
--!***********************************************************************************************************
|
|
|
--Colas de resultados
|
--Colas de resultados
|
rx : scfifo
|
rx : scfifo
|
generic map (
|
generic map (
|
allow_rwcycle_when_full => "ON",
|
allow_rwcycle_when_full => "ON",
|
lpm_widthu => 5,
|
lpm_widthu => 5,
|
lpm_numwords => 32,
|
lpm_numwords => 32,
|
lpm_showahead => "ON",
|
lpm_showahead => "ON",
|
lpm_width => 32,
|
lpm_width => 32,
|
overflow_checking => "ON",
|
overflow_checking => "ON",
|
underflow_checking => "ON",
|
underflow_checking => "ON",
|
use_eab => "ON"
|
use_eab => "ON"
|
)
|
)
|
port map (
|
port map (
|
aclr => '0',
|
aclr => '0',
|
clock => clk,
|
clock => clk,
|
empty => sqr_e,
|
empty => sqr_e,
|
rdreq => ack,
|
rdreq => ack,
|
wrreq => sqr_w,
|
wrreq => sqr_w,
|
data => sqr_dx,
|
data => sqr_dx,
|
q => vx
|
q => vx
|
);
|
);
|
ry : scfifo
|
ry : scfifo
|
generic map (
|
generic map (
|
allow_rwcycle_when_full => "ON",
|
allow_rwcycle_when_full => "ON",
|
lpm_widthu => 5,
|
lpm_widthu => 5,
|
lpm_numwords => 32,
|
lpm_numwords => 32,
|
lpm_showahead => "ON",
|
lpm_showahead => "ON",
|
lpm_width => 32,
|
lpm_width => 32,
|
overflow_checking => "ON",
|
overflow_checking => "ON",
|
underflow_checking => "ON",
|
underflow_checking => "ON",
|
use_eab => "ON"
|
use_eab => "ON"
|
)
|
)
|
port map (
|
port map (
|
aclr => '0',
|
aclr => '0',
|
clock => clk,
|
clock => clk,
|
rdreq => ack,
|
rdreq => ack,
|
wrreq => sqr_w,
|
wrreq => sqr_w,
|
data => sqr_dy,
|
data => sqr_dy,
|
q => vy
|
q => vy
|
);
|
);
|
rz : scfifo
|
rz : scfifo
|
generic map (
|
generic map (
|
allow_rwcycle_when_full => "ON",
|
allow_rwcycle_when_full => "ON",
|
lpm_widthu => 5,
|
lpm_widthu => 5,
|
lpm_numwords => 32,
|
lpm_numwords => 32,
|
lpm_showahead => "ON",
|
lpm_showahead => "ON",
|
lpm_width => 32,
|
lpm_width => 32,
|
overflow_checking => "ON",
|
overflow_checking => "ON",
|
underflow_checking => "ON",
|
underflow_checking => "ON",
|
use_eab => "ON"
|
use_eab => "ON"
|
)
|
)
|
port map (
|
port map (
|
aclr => '0',
|
aclr => '0',
|
clock => clk,
|
clock => clk,
|
rdreq => ack,
|
rdreq => ack,
|
wrreq => sqr_w,
|
wrreq => sqr_w,
|
data => sqr_dz,
|
data => sqr_dz,
|
q => vz
|
q => vz
|
);
|
);
|
rsc : scfifo
|
rsc : scfifo
|
generic map (
|
generic map (
|
allow_rwcycle_when_full => "ON",
|
allow_rwcycle_when_full => "ON",
|
lpm_widthu => 5,
|
lpm_widthu => 5,
|
lpm_numwords => 32,
|
lpm_numwords => 32,
|
lpm_showahead => "ON",
|
lpm_showahead => "ON",
|
lpm_width => 32,
|
lpm_width => 32,
|
overflow_checking => "ON",
|
overflow_checking => "ON",
|
underflow_checking => "ON",
|
underflow_checking => "ON",
|
use_eab => "ON"
|
use_eab => "ON"
|
)
|
)
|
port map (
|
port map (
|
aclr => '0',
|
aclr => '0',
|
clock => clk,
|
clock => clk,
|
rdreq => ack,
|
rdreq => ack,
|
wrreq => sqr_w,
|
wrreq => sqr_w,
|
data => sqr_dsc,
|
data => sqr_dsc,
|
q => sc
|
q => sc
|
);
|
);
|
|
|
|
|
end architecture;
|
end architecture;
|
|
|
