library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.math_real.all;
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use ieee.math_real.all;
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library std;
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library std;
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use std.textio.all;
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use std.textio.all;
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--! Memory Compiler Library
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--! Memory Compiler Library
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library altera_mf;
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library altera_mf;
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use altera_mf.all;
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use altera_mf.all;
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library lpm;
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library lpm;
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use lpm.all;
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use lpm.all;
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package arithpack is
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package arithpack is
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--!Constantes usadas por los RTLs
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--!Constantes usadas por los RTLs
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constant qz : integer := 00;constant qy : integer := 01;constant qx : integer := 02;constant sc : integer := 03;
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constant qz : integer := 00;constant qy : integer := 01;constant qx : integer := 02;constant qsc: integer := 03;
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constant az : integer := 00;constant ay : integer := 01;constant ax : integer := 02;constant bz : integer := 03;constant by : integer := 04;constant bx : integer := 05;
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constant az : integer := 00;constant ay : integer := 01;constant ax : integer := 02;constant bz : integer := 03;constant by : integer := 04;constant bx : integer := 05;
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constant f0 : integer := 00;constant f1 : integer := 01;constant f2 : integer := 02;constant f3 : integer := 03;constant f4 : integer := 04;constant f5 : integer := 05;
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constant f0 : integer := 00;constant f1 : integer := 01;constant f2 : integer := 02;constant f3 : integer := 03;constant f4 : integer := 04;constant f5 : integer := 05;
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constant f6 : integer := 06;constant f7 : integer := 07;constant f8 : integer := 08;constant f9 : integer := 09;constant f10: integer := 10;constant f11: integer := 11;
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constant f6 : integer := 06;constant f7 : integer := 07;constant f8 : integer := 08;constant f9 : integer := 09;constant f10: integer := 10;constant f11: integer := 11;
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constant s0 : integer := 00;constant s1 : integer := 01;constant s2 : integer := 02;constant s3 : integer := 03;constant s4 : integer := 04;constant s5 : integer := 05;
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constant s0 : integer := 00;constant s1 : integer := 01;constant s2 : integer := 02;constant s3 : integer := 03;constant s4 : integer := 04;constant s5 : integer := 05;
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constant a0 : integer := 00;constant a1 : integer := 01;constant a2 : integer := 02;
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constant a0 : integer := 00;constant a1 : integer := 01;constant a2 : integer := 02;
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constant p0 : integer := 00;constant p1 : integer := 01;constant p2 : integer := 02;constant p3 : integer := 03;constant p4 : integer := 04;constant p5 : integer := 05;
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constant p0 : integer := 00;constant p1 : integer := 01;constant p2 : integer := 02;constant p3 : integer := 03;constant p4 : integer := 04;constant p5 : integer := 05;
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constant index_control_register : integer := 00;
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constant index_start_address_r : integer := 01;
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constant index_end_address_r : integer := 02;
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constant index_start_address_w : integer := 03;
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constant index_end_address_w : integer := 04;
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constant index_scratch_register : integer := 05;
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--! Máquina de estados.
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--! Control de tamaños de memoria.
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constant widthadmemblock : integer := 9;
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subtype xfloat32 is std_logic_vector(31 downto 0);
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subtype xfloat32 is std_logic_vector(31 downto 0);
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type v3f is array(02 downto 0) of xfloat32;
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type v3f is array(02 downto 0) of xfloat32;
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--! Constantes para definir bloques de valores de 32 bits single float
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--! Constantes para definir bloques de valores de 32 bits single float
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type vectorblock12 is array (11 downto 0) of xfloat32;
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type vectorblock12 is array (11 downto 0) of xfloat32;
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type vectorblock08 is array (07 downto 0) of xfloat32;
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type vectorblock08 is array (07 downto 0) of xfloat32;
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type vectorblock06 is array (05 downto 0) of xfloat32;
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type vectorblock06 is array (05 downto 0) of xfloat32;
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type vectorblock04 is array (03 downto 0) of xfloat32;
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type vectorblock04 is array (03 downto 0) of xfloat32;
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type vectorblock03 is array (02 downto 0) of xfloat32;
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type vectorblock03 is array (02 downto 0) of xfloat32;
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type vectorblock02 is array (01 downto 0) of xfloat32;
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type vectorblock02 is array (01 downto 0) of xfloat32;
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--! Constante de reseteo
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--! Constante de reseteo
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constant rstMasterValue : std_logic :='0';
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constant rstMasterValue : std_logic :='0';
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--! Constantes periodicas.
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--! Constantes periodicas.
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constant tclk : time := 20 ns;
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constant tclk : time := 20 ns;
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constant tclk_2 : time := tclk/2;
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constant tclk_2 : time := tclk/2;
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constant tclk_4 : time := tclk/4;
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constant tclk_4 : time := tclk/4;
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component raytrac
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port (
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clk : in std_logic;
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rst : in std_logic;
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--! Interface Avalon Master
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address_master : out std_logic_vector(31 downto 0);
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begintransfer : out std_logic;
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read_master : out std_logic;
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readdata_master : in std_logic_vector (31 downto 0);
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write_master : out std_logic;
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writedata_master: out std_logic_vector (31 downto 0);
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waitrequest : in std_logic_vector;
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readdatavalid_m : in std_logic_vector;
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--! Interface Avalon Slave
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address_slave : in std_logic_vector(3 downto 0);
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read_slave : in std_logic;
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readdata_slave : in std_logic_vector(31 downto 0);
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write_slave : in std_logic;
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writedata_slave : in std_logic_vector(31 downto 0);
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readdatavalid_s : out std_logic;
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--! Interface Interrupt Sender
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irq : out std_logic
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);
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end component;
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component raytrac_control
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port (
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--! Señales normales de secuencia.
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clk: in std_logic;
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rst: in std_logic;
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--! Interface Avalon Master
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begintransfer : out std_logic;
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address_master : out std_logic_vector(31 downto 0);
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read_master : out std_logic;
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write_master : out std_logic;
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waitrequest : in std_logic;
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readdatavalid_m : in std_logic;
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--! Interface Avalon Slave
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address_slave : in std_logic_vector(3 downto 0);
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read_slave : in std_logic;
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readdata_slave : out std_logic_vector(31 downto 0);
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write_slave : in std_logic;
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writedata_slave : in std_logic_vector(31 downto 0);
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readdatavalid_s : out std_logic;
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--! Interface Interrupt Sender
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irq : out std_logic;
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--! Señales de Control (Memblock)
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go : out std_logic;
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comb : out std_logic;
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load : out std_logic;
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load_chain : out std_logic_vector(1 downto 0);
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qparams_e : in std_logic;
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qresult_e : in std_logic_vector(3 downto 0);
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--! Señles de Control de Datapath (DPC)
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qparams_q : in xfloat32;
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d : out std_logic;
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c : out std_logic;
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s : out std_logic;
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qresult_sel : out std_logic_vector(1 downto 0)
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);
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end component;
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--! Bloque de memorias
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component memblock
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port (
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--!Entradas de Control
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clk : in std_logic;
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rst : in std_logic;
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go : in std_logic;
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comb : in std_logic;
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load : in std_logic;
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load_chain : in std_logic_vector(1 downto 0);
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--! Cola de parámetros
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readdatavalid : in std_logic;
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readdata_master : in xfloat32;
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qparams_r : in std_logic;
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qparams_e : out std_logic;
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--! Cola de resultados
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qresult_d : in vectorblock04;
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qresult_q : out vectorblock04;
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--! Registro de parámetros
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paraminput : out vectorblock06;
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--! Cadena de sincronización
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sync_chain_0 : out std_logic;
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--! señales de colas vacias
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qresult_e : out std_logic_vector(3 downto 0);
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--! Colas de resultados
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qresult_w : in std_logic_vector(3 downto 0);
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qresult_rdec : in std_logic_vector(3 downto 0)
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);
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end component;
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--! Bloque decodificacion DataPath Control.
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component dpc
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port (
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clk : in std_logic;
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rst : in std_logic;
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paraminput : in vectorblock06; --! Vectores A,B
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prd32blko : in vectorblock06; --! Salidas de los 6 multiplicadores.
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add32blko : in vectorblock03; --! Salidas de los 3 sumadores.
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inv32blko : in xfloat32; --! Salidas de la raiz cuadradas y el inversor.
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sqr32blko : in xfloat32; --! Salidas de la raiz cuadradas y el inversor.
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d,c,s : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
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sync_chain_0 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.
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qresult_q : in vectorblock04; --! Salida de las colas de resultados
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qresult_sel : in std_logic_vector (1 downto 0); --! Direccion con el resultado de la
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qresult_rdec : out std_logic_vector (3 downto 0); --!Señales de escritura decodificadas
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qresult_w : out std_logic_vector (3 downto 0); --! Salidas de escritura y lectura en las colas de resultados.
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qresult_d : out vectorblock04; --! 4 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.
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dataread : in std_logic;
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prd32blki : out vectorblock12; --! Entrada de los 12 factores en el bloque de multiplicación respectivamente.
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add32blki : out vectorblock06; --! Entrada de los 6 sumandos del bloque de 3 sumadores.
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dataout : out xfloat32
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);
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end component;
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--! Bloque Aritmetico de Sumadores y Multiplicadores (madd)
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component arithblock
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port (
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clk : in std_logic;
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rst : in std_logic;
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sign : in std_logic;
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prd32blki : in vectorblock12;
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add32blki : in vectorblock06;
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add32blko : out vectorblock03;
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prd32blko : out vectorblock06;
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sq32o : out xfloat32;
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inv32o : out xfloat32
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);
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end component;
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--! Componentes Aritméticos
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component fadd32
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port (
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clk : in std_logic;
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dpc : in std_logic;
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a32 : in xfloat32;
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b32 : in xfloat32;
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c32 : out xfloat32
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);
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end component;
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component fmul32
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port (
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clk : in std_logic;
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a32 : in xfloat32;
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b32 : in xfloat32;
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p32 : out xfloat32
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);
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end component;
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--! Bloque de Raiz Cuadrada
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component sqrt32
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port (
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clk : in std_logic;
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rd32: in xfloat32;
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sq32: out xfloat32
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);
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end component;
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--! Bloque de Inversores.
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component invr32
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port (
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clk : in std_logic;
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dvd32 : in xfloat32;
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qout32 : out xfloat32
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);
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end component;
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--! Contadores para la máquina de estados.
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component customCounter
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port (
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clk : in std_logic;
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rst : in std_logic;
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stateTrans : in std_logic;
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waitrequest_n : in std_logic;
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endaddress : in std_logic_vector (31 downto 2); --! Los 5 bits de arriba.
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startaddress : in std_logic_vector(31 downto 0);
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endaddressfetch : out std_logic;
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address_master : out std_logic_vector (31 downto 0)
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);
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end component;
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--! LPM_MULTIPLIER
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component lpm_mult
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generic (
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lpm_hint : string;
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lpm_pipeline : natural;
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lpm_representation : string;
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lpm_type : string;
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lpm_widtha : natural;
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lpm_widthb : natural;
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lpm_widthp : natural
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);
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port (
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dataa : in std_logic_vector ( lpm_widtha-1 downto 0 );
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datab : in std_logic_vector ( lpm_widthb-1 downto 0 );
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result : out std_logic_vector( lpm_widthp-1 downto 0 )
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);
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end component;
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--! LPM Memory Compiler.
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-- component scfifo
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-- generic (
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-- add_ram_output_register :string;
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-- allow_rwcycle_when_full :string;
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-- intended_device_family :string;
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-- lpm_hint :string;
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-- lpm_numwords :natural;
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-- lpm_showahead :string;
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-- lpm_type :string;
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-- lpm_width :natural;
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-- overflow_checking :string;
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-- underflow_checking :string;
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-- use_eab :string
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-- );
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-- port(
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-- rdreq : in std_logic;
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-- aclr : in std_logic;
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-- empty : out std_logic;
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-- clock : in std_logic;
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-- q : out std_logic_vector(lpm_width-1 downto 0);
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-- wrreq : in std_logic;
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-- data : in std_logic_vector(lpm_width-1 downto 0);
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-- almost_full : out std_logic;
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-- full : out std_logic
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-- );
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-- end component;
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type apCamera is record
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type apCamera is record
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resx,resy : integer;
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resx,resy : integer;
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width,height : real;
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width,height : real;
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dist : real;
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dist : real;
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end record;
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end record;
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--! Función que convierte un std_logic_vector en un numero entero
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--! Función que convierte un std_logic_vector en un numero entero
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function ap_slv2int(sl:std_logic_vector) return integer;
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function ap_slv2int(sl:std_logic_vector) return integer;
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--! Función que convierte un número flotante IEE754 single float, en un número std_logic_vector.
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--! Función que convierte un número flotante IEE754 single float, en un número std_logic_vector.
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function ap_fp2slv (f:real) return std_logic_vector;
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function ap_fp2slv (f:real) return std_logic_vector;
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--! Función que convierte un número std_logic_vector en un ieee754 single float.
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--! Función que convierte un número std_logic_vector en un ieee754 single float.
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function ap_slv2fp (sl:std_logic_vector) return real;
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function ap_slv2fp (sl:std_logic_vector) return real;
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--! Función que devuelve un vector en punto flotante IEEE754 a través de un
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--! Función que devuelve un vector en punto flotante IEEE754 a través de un
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function ap_slv_calc_xyvec (x,y:integer; cam:apCamera) return v3f;
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function ap_slv_calc_xyvec (x,y:integer; cam:apCamera) return v3f;
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--! Función que devuelve una cadena con el número flotante IEEE 754 ó a una cadena de cifras hexadecimales.
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--! Función que devuelve una cadena con el número flotante IEEE 754 ó a una cadena de cifras hexadecimales.
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procedure ap_slvf2string(l:inout line;sl:std_logic_vector);
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procedure ap_slvf2string(l:inout line;sl:std_logic_vector);
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procedure ap_slv2hex (l:inout line;h:in std_logic_vector) ;
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procedure ap_slv2hex (l:inout line;h:in std_logic_vector) ;
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--! Función que devuelve una cadena con los componentes de un vector R3 en punto flotante IEEE754
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--! Función que devuelve una cadena con los componentes de un vector R3 en punto flotante IEEE754
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procedure ap_v3f2string(l:inout line;v:in v3f);
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procedure ap_v3f2string(l:inout line;v:in v3f);
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procedure ap_xfp032string(l:inout line;vb03:in vectorblock03);
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procedure ap_xfp032string(l:inout line;vb03:in vectorblock03);
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--! Función que formatea una instrucción
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--! Función que formatea una instrucción
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function ap_format_instruction(i:string;ac_o,ac_f,bd_o,bd_f:std_logic_vector;comb:std_logic) return std_logic_vector;
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function ap_format_instruction(i:string;ac_o,ac_f,bd_o,bd_f:std_logic_vector;comb:std_logic) return std_logic_vector;
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--! Función que devuelve una cadena de caracteres de un solo caracter con el valor de un bit std_logic
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--! Función que devuelve una cadena de caracteres de un solo caracter con el valor de un bit std_logic
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procedure ap_sl2string(l:inout line;s:std_logic);
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procedure ap_sl2string(l:inout line;s:std_logic);
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--! Procedimiento para mostrar vectores en forma de arreglos de flotantes
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--! Procedimiento para mostrar vectores en forma de arreglos de flotantes
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procedure ap_xfp122string(l:inout line;vb12:in vectorblock12);
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procedure ap_xfp122string(l:inout line;vb12:in vectorblock12);
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procedure ap_xfp082string(l:inout line;vb08:in vectorblock08);
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procedure ap_xfp082string(l:inout line;vb08:in vectorblock08);
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procedure ap_xfp062string(l:inout line;vb06:in vectorblock06);
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procedure ap_xfp062string(l:inout line;vb06:in vectorblock06);
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procedure ap_xfp042string(l:inout line;vb04:in vectorblock04);
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procedure ap_xfp042string(l:inout line;vb04:in vectorblock04);
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procedure ap_xfp022string(l:inout line;vb02:in vectorblock02);
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procedure ap_xfp022string(l:inout line;vb02:in vectorblock02);
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end package;
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end package;
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package body arithpack is
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package body arithpack is
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procedure ap_xfp022string(l:inout line; vb02:in vectorblock02) is
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procedure ap_xfp022string(l:inout line; vb02:in vectorblock02) is
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begin
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begin
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for i in 01 downto 0 loop
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for i in 01 downto 0 loop
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write(l,string'(" ["&integer'image(i)&"]"));
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write(l,string'(" ["&integer'image(i)&"]"));
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write(l,string'(" "));
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write(l,string'(" "));
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ap_slvf2string(l,vb02(i));
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ap_slvf2string(l,vb02(i));
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end loop;
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end loop;
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end procedure;
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end procedure;
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procedure ap_xfp122string(l:inout line; vb12:in vectorblock12) is
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procedure ap_xfp122string(l:inout line; vb12:in vectorblock12) is
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begin
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begin
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for i in 11 downto 0 loop
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for i in 11 downto 0 loop
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write(l,string'(" ["&integer'image(i)&"]"));
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write(l,string'(" ["&integer'image(i)&"]"));
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write(l,string'(" "));
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write(l,string'(" "));
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ap_slvf2string(l,vb12(i));
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ap_slvf2string(l,vb12(i));
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end loop;
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end loop;
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end procedure;
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end procedure;
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procedure ap_xfp082string(l:inout line; vb08:in vectorblock08) is
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procedure ap_xfp082string(l:inout line; vb08:in vectorblock08) is
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begin
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begin
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for i in 07 downto 0 loop
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for i in 07 downto 0 loop
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write(l,string'(" ["&integer'image(i)&"]"));
|
write(l,string'(" ["&integer'image(i)&"]"));
|
write(l,string'(" "));
|
write(l,string'(" "));
|
ap_slvf2string(l,vb08(i));
|
ap_slvf2string(l,vb08(i));
|
end loop;
|
end loop;
|
end procedure;
|
end procedure;
|
|
|
procedure ap_xfp062string(l:inout line; vb06:in vectorblock06) is
|
procedure ap_xfp062string(l:inout line; vb06:in vectorblock06) is
|
|
|
begin
|
begin
|
for i in 05 downto 0 loop
|
for i in 05 downto 0 loop
|
write(l,string'(" ["&integer'image(i)&"]"));
|
write(l,string'(" ["&integer'image(i)&"]"));
|
write(l,string'(" "));
|
write(l,string'(" "));
|
ap_slvf2string(l,vb06(i));
|
ap_slvf2string(l,vb06(i));
|
end loop;
|
end loop;
|
end procedure;
|
end procedure;
|
|
|
procedure ap_xfp042string(l:inout line; vb04:in vectorblock04) is
|
procedure ap_xfp042string(l:inout line; vb04:in vectorblock04) is
|
|
|
begin
|
begin
|
for i in 03 downto 0 loop
|
for i in 03 downto 0 loop
|
write(l,string'(" ["&integer'image(i)&"]"));
|
write(l,string'(" ["&integer'image(i)&"]"));
|
write(l,string'(" "));
|
write(l,string'(" "));
|
ap_slvf2string(l,vb04(i));
|
ap_slvf2string(l,vb04(i));
|
end loop;
|
end loop;
|
end procedure;
|
end procedure;
|
|
|
|
|
procedure ap_sl2string(l:inout line; s:in std_logic)is
|
procedure ap_sl2string(l:inout line; s:in std_logic)is
|
variable tmp:string(1 to 1);
|
variable tmp:string(1 to 1);
|
begin
|
begin
|
|
|
case s is
|
case s is
|
when '1' =>
|
when '1' =>
|
tmp:="1";
|
tmp:="1";
|
when '0' =>
|
when '0' =>
|
tmp:="0";
|
tmp:="0";
|
when 'U' =>
|
when 'U' =>
|
tmp:="U";
|
tmp:="U";
|
when 'X' =>
|
when 'X' =>
|
tmp:="X";
|
tmp:="X";
|
when 'Z' =>
|
when 'Z' =>
|
tmp:="Z";
|
tmp:="Z";
|
when 'W' =>
|
when 'W' =>
|
tmp:="W";
|
tmp:="W";
|
when 'L' =>
|
when 'L' =>
|
tmp:="L";
|
tmp:="L";
|
when 'H' =>
|
when 'H' =>
|
tmp:="H";
|
tmp:="H";
|
when others =>
|
when others =>
|
tmp:="-"; -- Don't care
|
tmp:="-"; -- Don't care
|
end case;
|
end case;
|
write(l,string'(" "));
|
write(l,string'(" "));
|
write(l,string'(tmp));
|
write(l,string'(tmp));
|
write(l,string'(" "));
|
write(l,string'(" "));
|
|
|
|
|
|
|
end procedure;
|
end procedure;
|
|
|
function ap_format_instruction(i:string;ac_o,ac_f,bd_o,bd_f:std_logic_vector;comb:std_logic) return std_logic_vector is
|
function ap_format_instruction(i:string;ac_o,ac_f,bd_o,bd_f:std_logic_vector;comb:std_logic) return std_logic_vector is
|
|
|
alias aco : std_logic_vector (4 downto 0) is ac_o;
|
alias aco : std_logic_vector (4 downto 0) is ac_o;
|
alias acf : std_logic_vector (4 downto 0) is ac_f;
|
alias acf : std_logic_vector (4 downto 0) is ac_f;
|
alias bdo : std_logic_vector (4 downto 0) is bd_o;
|
alias bdo : std_logic_vector (4 downto 0) is bd_o;
|
alias bdf : std_logic_vector (4 downto 0) is bd_f;
|
alias bdf : std_logic_vector (4 downto 0) is bd_f;
|
variable ins : std_logic_vector (31 downto 0);
|
variable ins : std_logic_vector (31 downto 0);
|
alias it : string (1 to 3) is i;
|
alias it : string (1 to 3) is i;
|
begin
|
begin
|
|
|
case it is
|
case it is
|
when "mag" =>
|
when "mag" =>
|
ins(31 downto 29) := "100";
|
ins(31 downto 29) := "100";
|
ins(04 downto 00) := '1'&x"8";
|
ins(04 downto 00) := '1'&x"8";
|
when "nrm" =>
|
when "nrm" =>
|
ins(31 downto 29) := "110";
|
ins(31 downto 29) := "110";
|
ins(04 downto 00) := '1'&x"d";
|
ins(04 downto 00) := '1'&x"d";
|
when "add" =>
|
when "add" =>
|
ins(31 downto 29) := "001";
|
ins(31 downto 29) := "001";
|
ins(04 downto 00) := '0'&x"a";
|
ins(04 downto 00) := '0'&x"a";
|
when "sub" =>
|
when "sub" =>
|
ins(31 downto 29) := "011";
|
ins(31 downto 29) := "011";
|
ins(04 downto 00) := '0'&x"a";
|
ins(04 downto 00) := '0'&x"a";
|
when "dot" =>
|
when "dot" =>
|
ins(31 downto 29) := "000";
|
ins(31 downto 29) := "000";
|
ins(04 downto 00) := '1'&x"7";
|
ins(04 downto 00) := '1'&x"7";
|
when "crs" =>
|
when "crs" =>
|
ins(31 downto 29) := "010";
|
ins(31 downto 29) := "010";
|
ins(04 downto 00) := '0'&x"e";
|
ins(04 downto 00) := '0'&x"e";
|
when others =>
|
when others =>
|
ins(31 downto 29) := "111";
|
ins(31 downto 29) := "111";
|
ins(04 downto 00) := '0'&x"5";
|
ins(04 downto 00) := '0'&x"5";
|
end case;
|
end case;
|
ins(28 downto 24) := aco;
|
ins(28 downto 24) := aco;
|
ins(23 downto 19) := acf;
|
ins(23 downto 19) := acf;
|
ins(18 downto 14) := bdo;
|
ins(18 downto 14) := bdo;
|
ins(13 downto 09) := bdf;
|
ins(13 downto 09) := bdf;
|
ins(08) := comb;
|
ins(08) := comb;
|
ins(07 downto 05) := "000";
|
ins(07 downto 05) := "000";
|
return ins;
|
return ins;
|
|
|
|
|
end function;
|
end function;
|
|
|
|
|
|
|
procedure ap_v3f2string(l:inout line;v:in v3f) is
|
procedure ap_v3f2string(l:inout line;v:in v3f) is
|
begin
|
begin
|
write(l,string'("[X]"));
|
write(l,string'("[X]"));
|
write(l,string'(" "));
|
write(l,string'(" "));
|
ap_slvf2string(l,v(2));
|
ap_slvf2string(l,v(2));
|
write(l,string'("[Y]"));
|
write(l,string'("[Y]"));
|
write(l,string'(" "));
|
write(l,string'(" "));
|
ap_slvf2string(l,v(1));
|
ap_slvf2string(l,v(1));
|
write(l,string'("[Z]"));
|
write(l,string'("[Z]"));
|
write(l,string'(" "));
|
write(l,string'(" "));
|
ap_slvf2string(l,v(0));
|
ap_slvf2string(l,v(0));
|
end procedure;
|
end procedure;
|
procedure ap_xfp032string(l:inout line;vb03:in vectorblock03) is
|
procedure ap_xfp032string(l:inout line;vb03:in vectorblock03) is
|
begin
|
begin
|
write(l,string'("[X]"));
|
write(l,string'("[X]"));
|
write(l,string'(" "));
|
write(l,string'(" "));
|
ap_slvf2string(l,vb03(2));
|
ap_slvf2string(l,vb03(2));
|
write(l,string'("[Y]"));
|
write(l,string'("[Y]"));
|
write(l,string'(" "));
|
write(l,string'(" "));
|
ap_slvf2string(l,vb03(1));
|
ap_slvf2string(l,vb03(1));
|
write(l,string'("[Z]"));
|
write(l,string'("[Z]"));
|
write(l,string'(" "));
|
write(l,string'(" "));
|
ap_slvf2string(l,vb03(0));
|
ap_slvf2string(l,vb03(0));
|
end procedure;
|
end procedure;
|
|
|
constant hexchars : string (1 to 16) := "0123456789ABCDEF";
|
constant hexchars : string (1 to 16) := "0123456789ABCDEF";
|
procedure ap_slv2hex (l:inout line;h:in std_logic_vector) is
|
procedure ap_slv2hex (l:inout line;h:in std_logic_vector) is
|
variable index_high,index_low,highone,nc : integer;
|
variable index_high,index_low,highone,nc : integer;
|
begin
|
begin
|
highone := h'high-h'low;
|
highone := h'high-h'low;
|
nc:=0;
|
nc:=0;
|
for i in h'high downto h'low loop
|
for i in h'high downto h'low loop
|
if h(i)/='0' and h(i)/='1' then
|
if h(i)/='0' and h(i)/='1' then
|
nc:=1;
|
nc:=1;
|
end if;
|
end if;
|
end loop;
|
end loop;
|
|
|
if nc=1 then
|
if nc=1 then
|
for i in h'high downto h'low loop
|
for i in h'high downto h'low loop
|
ap_sl2string(l,h(i));
|
ap_sl2string(l,h(i));
|
end loop;
|
end loop;
|
else
|
else
|
for i in (highone)/4 downto 0 loop
|
for i in (highone)/4 downto 0 loop
|
index_low:=i*4;
|
index_low:=i*4;
|
if (index_low+3)>highone then
|
if (index_low+3)>highone then
|
index_high := highone;
|
index_high := highone;
|
else
|
else
|
index_high := i*4+3;
|
index_high := i*4+3;
|
end if;
|
end if;
|
write(l,hexchars(1+ieee.std_logic_unsigned.conv_integer(h(index_high+h'low downto index_low+h'low))));
|
write(l,hexchars(1+ieee.std_logic_unsigned.conv_integer(h(index_high+h'low downto index_low+h'low))));
|
end loop;
|
end loop;
|
end if;
|
end if;
|
end procedure;
|
end procedure;
|
|
|
function ap_slv2int (sl:std_logic_vector) return integer is
|
function ap_slv2int (sl:std_logic_vector) return integer is
|
alias s : std_logic_vector (sl'high downto sl'low) is sl;
|
alias s : std_logic_vector (sl'high downto sl'low) is sl;
|
variable i : integer;
|
variable i : integer;
|
begin
|
begin
|
i:=0;
|
i:=0;
|
for index in s'high downto s'low loop
|
for index in s'high downto s'low loop
|
if s(index)='1' then
|
if s(index)='1' then
|
i:=i*2+1;
|
i:=i*2+1;
|
else
|
else
|
i:=i*2;
|
i:=i*2;
|
end if;
|
end if;
|
end loop;
|
end loop;
|
return i;
|
return i;
|
|
|
end function;
|
end function;
|
function ap_fp2slv (f:real) return std_logic_vector is
|
function ap_fp2slv (f:real) return std_logic_vector is
|
variable faux : real;
|
variable faux : real;
|
variable sef : std_logic_vector (31 downto 0);
|
variable sef : std_logic_vector (31 downto 0);
|
begin
|
begin
|
--! Signo
|
--! Signo
|
if (f<0.0) then
|
if (f<0.0) then
|
sef(31) := '1';
|
sef(31) := '1';
|
faux:=f*(-1.0);
|
faux:=f*(-1.0);
|
else
|
else
|
sef(31) := '0';
|
sef(31) := '0';
|
faux:=f;
|
faux:=f;
|
end if;
|
end if;
|
|
|
--! Exponente
|
--! Exponente
|
sef(30 downto 23) := conv_std_logic_vector(127+integer(floor(log(faux,2.0))),8);
|
sef(30 downto 23) := conv_std_logic_vector(127+integer(floor(log(faux,2.0))),8);
|
|
|
--! Fraction
|
--! Fraction
|
faux :=faux/(2.0**real(floor(log(faux,2.0))));
|
faux :=faux/(2.0**real(floor(log(faux,2.0))));
|
faux := faux - 1.0;
|
faux := faux - 1.0;
|
|
|
sef(22 downto 0) := conv_std_logic_vector(integer(faux*(2.0**23.0)),23);
|
sef(22 downto 0) := conv_std_logic_vector(integer(faux*(2.0**23.0)),23);
|
|
|
return sef;
|
return sef;
|
|
|
end function;
|
end function;
|
|
|
function ap_slv2fp(sl:std_logic_vector) return real is
|
function ap_slv2fp(sl:std_logic_vector) return real is
|
variable frc:integer;
|
variable frc:integer;
|
alias s: std_logic_vector(31 downto 0) is sl;
|
alias s: std_logic_vector(31 downto 0) is sl;
|
variable f,expo: real;
|
variable f,expo: real;
|
|
|
begin
|
begin
|
|
|
|
|
expo:=real(ap_slv2int(s(30 downto 23)) - 127);
|
expo:=real(ap_slv2int(s(30 downto 23)) - 127);
|
expo:=(2.0)**(expo);
|
expo:=(2.0)**(expo);
|
frc:=ap_slv2int('1'&s(22 downto 0));
|
frc:=ap_slv2int('1'&s(22 downto 0));
|
f:=real(frc)*(2.0**(-23.0));
|
f:=real(frc)*(2.0**(-23.0));
|
f:=f*real(expo);
|
f:=f*real(expo);
|
|
|
if s(31)='1' then
|
if s(31)='1' then
|
return -f;
|
return -f;
|
else
|
else
|
return f;
|
return f;
|
end if;
|
end if;
|
|
|
|
|
|
|
|
|
end function;
|
end function;
|
|
|
function ap_slv_calc_xyvec (x,y:integer; cam:apCamera) return v3f is
|
function ap_slv_calc_xyvec (x,y:integer; cam:apCamera) return v3f is
|
|
|
|
|
variable dx,dy : real;
|
variable dx,dy : real;
|
variable v : v3f;
|
variable v : v3f;
|
begin
|
begin
|
|
|
dx := cam.width/real(cam.resx);
|
dx := cam.width/real(cam.resx);
|
dy := cam.height/real(cam.resy);
|
dy := cam.height/real(cam.resy);
|
|
|
--! Eje Z: Tomando el dedo índice de la mano derecha, este eje queda apuntando en la direcci&on en la que mira la cámara u observador siempre.
|
--! Eje Z: Tomando el dedo índice de la mano derecha, este eje queda apuntando en la direcci&on en la que mira la cámara u observador siempre.
|
v(0):=ap_fp2slv(cam.dist);
|
v(0):=ap_fp2slv(cam.dist);
|
|
|
--! Eje X: Tomando el dedo corazón de la mano derecha, este eje queda apuntando a la izquierda del observador, desde el observador.
|
--! Eje X: Tomando el dedo corazón de la mano derecha, este eje queda apuntando a la izquierda del observador, desde el observador.
|
v(2):=ap_fp2slv(dx*real(cam.resx)*0.5-real(x)*dx-dx*0.5);
|
v(2):=ap_fp2slv(dx*real(cam.resx)*0.5-real(x)*dx-dx*0.5);
|
|
|
--! Eje Y: Tomando el dedo pulgar de la mano derecha, este eje queda apuntando hacia arriba del observador, desde el observador.
|
--! Eje Y: Tomando el dedo pulgar de la mano derecha, este eje queda apuntando hacia arriba del observador, desde el observador.
|
v(1):=ap_fp2slv(dy*real(cam.resy)*0.5-real(y)*dy-dy*0.5);
|
v(1):=ap_fp2slv(dy*real(cam.resy)*0.5-real(y)*dy-dy*0.5);
|
|
|
return v;
|
return v;
|
|
|
end function;
|
end function;
|
|
|
procedure ap_slvf2string(l:inout line;sl:std_logic_vector) is
|
procedure ap_slvf2string(l:inout line;sl:std_logic_vector) is
|
alias f: std_logic_vector(31 downto 0) is sl;
|
alias f: std_logic_vector(31 downto 0) is sl;
|
variable r: real;
|
variable r: real;
|
|
|
begin
|
begin
|
|
|
r:=ap_slv2fp(f);
|
r:=ap_slv2fp(f);
|
write(l,string'(real'image(r)));
|
write(l,string'(real'image(r)));
|
write(l,string'(" [ s:"));
|
write(l,string'(" [ s:"));
|
ap_slv2hex(l,f(31 downto 31));
|
ap_slv2hex(l,f(31 downto 31));
|
write(l,string'(" f: "));
|
write(l,string'(" f: "));
|
ap_slv2hex(l,f(30 downto 23));
|
ap_slv2hex(l,f(30 downto 23));
|
write(l,string'(" m: "));
|
write(l,string'(" m: "));
|
ap_slv2hex(l,f(22 downto 00));
|
ap_slv2hex(l,f(22 downto 00));
|
write(l,string'(" ]"));
|
write(l,string'(" ]"));
|
|
|
end procedure;
|
end procedure;
|
|
|
|
|
|
|
|
|
|
|