--! @file raytrac.vhd
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--! @file raytrac.vhd
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--! @brief Sistema de Procesamiento Vectorial. La interface es compatible con el bus Avalon de Altera.
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--! @brief Sistema de Procesamiento Vectorial. La interface es compatible con el bus Avalon de Altera.
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--! @author Julián Andrés Guarín Reyes
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--! @author Julián Andrés Guarín Reyes
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--------------------------------------------------------------
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--------------------------------------------------------------
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-- RAYTRAC
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-- RAYTRAC
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-- Author Julian Andres Guarin
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-- Author Julian Andres Guarin
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-- raytrac.vhd
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-- raytrac.vhd
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-- This file is part of raytrac.
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-- This file is part of raytrac.
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--
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--
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-- raytrac is free software: you can redistribute it and/or modify
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-- raytrac is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- raytrac is distributed in the hope that it will be useful,
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-- raytrac is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR a PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR a PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.arithpack.all;
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use work.arithpack.all;
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library altera_mf;
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library altera_mf;
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use altera_mf.altera_mf_components.all;
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use altera_mf.altera_mf_components.all;
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library lpm;
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library lpm;
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use lpm.lpm_components.all;
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use lpm.lpm_components.all;
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entity raytrac is
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entity raytrac is
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generic (
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generic (
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wd : integer := 32;
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wd : integer := 32;
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fd : integer := 8; --! Result Fifo Depth = 2**fd =256
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fd : integer := 8; --! Result Fifo Depth = 2**fd =256
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mb : integer := 4 --! Max Burst Length = 2**mb
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mb : integer := 4 --! Max Burst Length = 2**mb
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);
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);
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port (
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port (
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clk: in std_logic;
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clk: in std_logic;
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rst: in std_logic;
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rst: in std_logic;
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--! Avalon MM Slave
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--! Avalon MM Slave
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slave_address : in std_logic_vector(3 downto 0);
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slave_address : in std_logic_vector(3 downto 0);
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slave_read : in std_logic;
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slave_read : in std_logic;
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slave_write : in std_logic;
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slave_write : in std_logic;
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slave_readdata : out std_logic_vector(31 downto 0);
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slave_readdata : out std_logic_vector(31 downto 0);
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slave_writedata : in std_logic_vector(31 downto 0);
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slave_writedata : in std_logic_vector(31 downto 0);
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--! Avalon MM Master (Read & Write common signals)
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--! Avalon MM Master (Read & Write common signals)
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master_address : out std_logic_vector(31 downto 0);
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master_address : out std_logic_vector(31 downto 0);
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master_burstcount : out std_logic_vector(4 downto 0);
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master_burstcount : out std_logic_vector(4 downto 0);
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master_waitrequest : in std_logic;
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master_waitrequest : in std_logic;
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--! Avalon MM Master (Read Stage)
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--! Avalon MM Master (Read Stage)
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master_read : out std_logic;
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master_read : out std_logic;
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master_readdata : in std_logic_vector(31 downto 0);
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master_readdata : in std_logic_vector(31 downto 0);
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master_readdatavalid : in std_logic;
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master_readdatavalid : in std_logic;
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--! Avalon MM Master (Write Stage)
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--! Avalon MM Master (Write Stage)
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master_write : out std_logic;
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master_write : out std_logic;
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master_writedata : out std_logic_vector(31 downto 0);
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master_writedata : out std_logic_vector(31 downto 0);
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--! Avalon IRQ
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--! Avalon IRQ
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irq : out std_logic
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irq : out std_logic
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);
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);
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end entity;
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end entity;
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architecture raytrac_arch of raytrac is
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architecture raytrac_arch of raytrac is
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--! Altera Compiler Directive, to avoid m9k autoinferring thanks to the guys at http://www.alteraforum.com/forum/archive/index.php/t-30784.html ....
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--! Altera Compiler Directive, to avoid m9k autoinferring thanks to the guys at http://www.alteraforum.com/forum/archive/index.php/t-30784.html ....
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attribute altera_attribute : string;
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attribute altera_attribute : string;
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attribute altera_attribute of raytrac_arch : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
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attribute altera_attribute of raytrac_arch : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
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type registerblock is array (15 downto 0) of xfloat32;
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type registerblock is array (15 downto 0) of xfloat32;
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type transferState is (IDLE,SINK,SOURCE);
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type transferState is (IDLE,SINK,SOURCE);
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type upload_chain is (UPVX,UPVY,UPVZ,SC,DMA);
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type upload_chain is (UPVX,UPVY,UPVZ,SC,DMA);
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type download_chain is (DWAX,DWAY,DWAZ,DWBX,DWBY,DWBZ,DWAXBX,DWAYBY,DWAZBZ);
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type download_chain is (DWAX,DWAY,DWAZ,DWBX,DWBY,DWBZ,DWAXBX,DWAYBY,DWAZBZ);
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constant reg_ctrl : integer:=00;
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constant reg_ctrl : integer:=00;
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constant reg_vz : integer:=01;
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constant reg_vz : integer:=01;
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constant reg_vy : integer:=02;
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constant reg_vy : integer:=02;
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constant reg_vx : integer:=03;
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constant reg_vx : integer:=03;
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constant reg_scalar : integer:=04;
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constant reg_scalar : integer:=04;
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constant reg_nfetch : integer:=05;
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constant reg_nfetch : integer:=05;
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constant reg_outputcounter : integer:=06;
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constant reg_timercounter : integer:=06;
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constant reg_inputcounter : integer:=07;
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constant reg_inputcounter : integer:=07;
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constant reg_fetchstart : integer:=08;
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constant reg_fetchstart : integer:=08;
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constant reg_sinkstart : integer:=09;
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constant reg_sinkstart : integer:=09;
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constant reg_ax : integer:=10;
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constant reg_ax : integer:=10;
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constant reg_ay : integer:=11;
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constant reg_ay : integer:=11;
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constant reg_az : integer:=12;
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constant reg_az : integer:=12;
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constant reg_bx : integer:=13;
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constant reg_bx : integer:=13;
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constant reg_by : integer:=14;
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constant reg_by : integer:=14;
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constant reg_bz : integer:=15;
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constant reg_bz : integer:=15;
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constant reg_ctrl_cmb : integer:=00; --! CMB bit : Combinatorial Instruction.
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constant reg_ctrl_cmb : integer:=00; --! CMB bit : Combinatorial Instruction.
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constant reg_ctrl_s : integer:=01; --! S bit of the DCS field.
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constant reg_ctrl_s : integer:=01; --! S bit of the DCS field.
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constant reg_ctrl_c : integer:=02; --! C bit of the DCS field.
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constant reg_ctrl_c : integer:=02; --! C bit of the DCS field.
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constant reg_ctrl_d : integer:=03; --! D bit of the DCS field.
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constant reg_ctrl_d : integer:=03; --! D bit of the DCS field.
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constant reg_ctrl_sc : integer:=04; --! SC bit of the VTSC field.
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constant reg_ctrl_sc : integer:=04; --! SC bit of the VTSC field.
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constant reg_ctrl_vt : integer:=05; --! VT bit of the VTSC field.
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constant reg_ctrl_vt : integer:=05; --! VT bit of the VTSC field.
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constant reg_ctrl_dma : integer:=06; --! DMA bit.
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constant reg_ctrl_dma : integer:=06; --! DMA bit.
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constant reg_ctrl_flags_fc : integer:=07; --! Flood Condition Flag.
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constant reg_ctrl_flags_fc : integer:=07; --! Flood Condition Flag.
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constant reg_ctrl_flags_dc : integer:=08; --! Drain Condition Flag.
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constant reg_ctrl_flags_dc : integer:=08; --! Drain Condition Flag.
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constant reg_ctrl_flags_wp : integer:=09; --! Write on Memory Pending Flag.
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constant reg_ctrl_flags_wp : integer:=09; --! Write on Memory Pending Flag.
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constant reg_ctrl_flags_pp : integer:=10; --! Pipeline Pending Flag.
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constant reg_ctrl_flags_pp : integer:=10; --! Pipeline Pending Flag.
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constant reg_ctrl_flags_pl : integer:=11; --! Load Parameter Pending Flag.
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constant reg_ctrl_flags_pl : integer:=11; --! Load Parameter Pending Flag.
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constant reg_ctrl_flags_dp : integer:=12; --! Data Pending flag.
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constant reg_ctrl_flags_dp : integer:=12; --! Data Pending flag.
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constant reg_ctrl_flags_ap : integer:=13; --! Address Pending Flag.
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constant reg_ctrl_flags_ap : integer:=13; --! Address Pending Flag.
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constant reg_ctrl_rlsc : integer:=14; --! RLSC bit : Reload Load Sync Chain.
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constant reg_ctrl_rlsc : integer:=14; --! RLSC bit : Reload Load Sync Chain.
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constant reg_ctrl_rom : integer:=15; --! ROM bit : Read Only Mode bit.
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constant reg_ctrl_rom : integer:=15; --! ROM bit : Read Only Mode bit.
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constant reg_ctrl_alb : integer:=16; --! Conditional Writing. A<B.
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constant reg_ctrl_alb : integer:=16; --! Conditional Writing. A<B.
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constant reg_ctrl_ageb : integer:=17; --! A>=B.
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constant reg_ctrl_ageb : integer:=17; --! A>=B.
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constant reg_ctrl_aeb : integer:=18; --! A==B.
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constant reg_ctrl_aeb : integer:=18; --! A==B.
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constant reg_ctrl_aneb : integer:=19; --! A!=B.
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constant reg_ctrl_aneb : integer:=19; --! A!=B.
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constant reg_ctrl_accum_op : integer:=20; --! Acummulative Addition/Sub. User must write in the high word of nfetch how many time should be executed the addition/sub.
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constant reg_ctrl_accum_op : integer:=20; --! Acummulative Addition/Sub. User must write in the high word of nfetch how many time should be executed the addition/sub.
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constant reg_ctrl_irq : integer:=31; --! IRQ bit : Interrupt Request Signal.
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constant reg_ctrl_irq : integer:=31; --! IRQ bit : Interrupt Request Signal.
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--! Nfetch Reg Mask
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--! Nfetch Reg Mask
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constant reg_nfetch_high : integer:=11; --! NFETCH_HIGH : Higher bit to program the number of addresses to load in the interconnection.
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constant reg_nfetch_high : integer:=11; --! NFETCH_HIGH : Higher bit to program the number of addresses to load in the interconnection.
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--! Avalon MM Slave
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--! Avalon MM Slave
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signal sreg_block : registerblock;
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signal sreg_block : registerblock;
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signal sslave_read : std_logic;
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signal sslave_read : std_logic;
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signal sslave_write : std_logic;
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signal sslave_write : std_logic;
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signal sslave_writedata : std_logic_vector (wd-1 downto 0);
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signal sslave_writedata : std_logic_vector (wd-1 downto 0);
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signal sslave_address : std_logic_vector (3 downto 0);
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signal sslave_address : std_logic_vector (3 downto 0);
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signal sslave_waitrequest : std_logic;
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signal sslave_waitrequest : std_logic;
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--! Avalon MM Master
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--! Avalon MM Master
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signal smaster_write : std_logic;
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signal smaster_write : std_logic;
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signal smaster_read : std_logic;
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signal smaster_read : std_logic;
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--! State Machine and event signaling
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--! State Machine and event signaling
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signal sm : transferState;
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signal sm : transferState;
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signal sr_e : std_logic;
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signal sr_e : std_logic;
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signal sr_ack : std_logic;
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signal sr_ack : std_logic;
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signal soutb_ack : std_logic;
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signal soutb_ack : std_logic;
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signal soutb_d : std_logic_vector(wd-1 downto 0);
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signal soutb_d : std_logic_vector(wd-1 downto 0);
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signal soutb_w : std_logic;
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signal soutb_w : std_logic;
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signal soutb_e : std_logic;
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signal soutb_e : std_logic;
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signal soutb_ae : std_logic;
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signal soutb_ae : std_logic;
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signal soutb_af : std_logic;
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signal soutb_af : std_logic;
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signal soutb_usedw : std_logic_vector(fd-1 downto 0);
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signal soutb_usedw : std_logic_vector(fd-1 downto 0);
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signal ssync_chain_1 : std_logic;
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signal ssync_chain_1 : std_logic;
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signal ssync_chain_pending : std_logic;
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signal ssync_chain_pending : std_logic;
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signal sfetch_data_pending : std_logic;
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signal sfetch_data_pending : std_logic;
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signal sload_add_pending : std_logic;
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signal sload_add_pending : std_logic;
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signal spipeline_pending : std_logic;
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signal spipeline_pending : std_logic;
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signal swrite_pending : std_logic;
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signal swrite_pending : std_logic;
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signal sparamload_pending : std_logic;
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signal sparamload_pending : std_logic;
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signal sZeroTransit : std_logic;
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signal sZeroTransit : std_logic;
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--!Unload Control
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--!Unload Control
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signal supload_chain : upload_chain;
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signal supload_chain : upload_chain;
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signal supload_start : upload_chain;
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signal supload_start : upload_chain;
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--!Señales de apoyo:
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--!Señales de apoyo:
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signal zero : std_logic_vector(31 downto 0);
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signal zero : std_logic_vector(31 downto 0);
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--!High Register Bank Control Signals or AKA Load Sync Chain Control
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--!High Register Bank Control Signals or AKA Load Sync Chain Control
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signal sdownload_chain : download_chain;
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signal sdownload_chain : download_chain;
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signal sdownload_start : download_chain;
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signal sdownload_start : download_chain;
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signal srestart_chain : std_logic;
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--!State Machine Hysteresis Control Signals
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--!State Machine Hysteresis Control Signals
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signal sdrain_condition : std_logic;
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signal sdrain_condition : std_logic;
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signal sdrain_burstcount : std_logic_vector(mb downto 0);
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signal sdrain_burstcount : std_logic_vector(mb downto 0);
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signal sdata_fetch_counter : std_logic_vector(reg_nfetch_high downto 0);
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signal sdata_fetch_counter : std_logic_vector(reg_nfetch_high downto 0);
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signal sburstcount_sink : std_logic_vector(mb downto 0);
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signal sburstcount_sink : std_logic_vector(mb downto 0);
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signal sflood_condition : std_logic;
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signal sflood_condition : std_logic;
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signal sflood_burstcount : std_logic_vector(mb downto 0);
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signal sflood_burstcount : std_logic_vector(mb downto 0);
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signal sp0,sp1,sp2,sp3,sp4,sp5,sp6,sp7,sp8: std_logic_vector(31 downto 0);
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signal sp0,sp1,sp2,sp3,sp4,sp5,sp6,sp7,sp8: std_logic_vector(31 downto 0);
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--! Arithmetic Pipeline and Data Path Control
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--! Arithmetic Pipeline and Data Path Control
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component ap_n_dpc
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component ap_n_dpc
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port (
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port (
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p0,p1,p2,p3,p4,p5,p6,p7,p8 : out std_logic_vector(31 downto 0);
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p0,p1,p2,p3,p4,p5,p6,p7,p8 : out std_logic_vector(31 downto 0);
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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ax : in std_logic_vector(31 downto 0);
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ax : in std_logic_vector(31 downto 0);
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ay : in std_logic_vector(31 downto 0);
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ay : in std_logic_vector(31 downto 0);
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az : in std_logic_vector(31 downto 0);
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az : in std_logic_vector(31 downto 0);
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bx : in std_logic_vector(31 downto 0);
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bx : in std_logic_vector(31 downto 0);
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by : in std_logic_vector(31 downto 0);
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by : in std_logic_vector(31 downto 0);
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bz : in std_logic_vector(31 downto 0);
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bz : in std_logic_vector(31 downto 0);
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vx : out std_logic_vector(31 downto 0);
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vx : out std_logic_vector(31 downto 0);
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vy : out std_logic_vector(31 downto 0);
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vy : out std_logic_vector(31 downto 0);
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vz : out std_logic_vector(31 downto 0);
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vz : out std_logic_vector(31 downto 0);
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sc : out std_logic_vector(31 downto 0);
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sc : out std_logic_vector(31 downto 0);
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ack : in std_logic;
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ack : in std_logic;
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empty : out std_logic;
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empty : out std_logic;
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dcs : in std_logic_vector(2 downto 0); --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
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dcs : in std_logic_vector(2 downto 0); --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
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sync_chain_1 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.
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sync_chain_1 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.
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pipeline_pending : out std_logic --! Señal para indicar si hay datos en el pipeline aritmético.
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pipeline_pending : out std_logic --! Señal para indicar si hay datos en el pipeline aritmético.
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);
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);
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end component;
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end component;
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--! Nets para la salida de la cola de resultados y entrada del multiplexor del upload state machine.
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--! Nets para la salida de la cola de resultados y entrada del multiplexor del upload state machine.
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signal svx,svy,svz,ssc : std_logic_vector(31 downto 0);
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signal svx,svy,svz,ssc : std_logic_vector(31 downto 0);
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begin
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begin
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--!Zero agreggate
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--!Zero agreggate
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zero <= (others => '0');
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zero <= (others => '0');
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--! *************************************************************************************************************************************************************************************************************************************************************
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--! *************************************************************************************************************************************************************************************************************************************************************
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--! ARITHMETIC PIPELINE AND DATA PATH INSTANTIATION => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
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--! ARITHMETIC PIPELINE AND DATA PATH INSTANTIATION => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
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--! *************************************************************************************************************************************************************************************************************************************************************
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--! *************************************************************************************************************************************************************************************************************************************************************
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--! Arithpipeline and Datapath Control Instance
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--! Arithpipeline and Datapath Control Instance
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arithmetic_pipeline_and_datapath_controller : ap_n_dpc
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arithmetic_pipeline_and_datapath_controller : ap_n_dpc
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port map (
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port map (
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p0 => sp0,
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p0 => sp0,
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p1 => sp1,
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p1 => sp1,
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p2 => sp2,
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p2 => sp2,
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p3 => sp3,
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p3 => sp3,
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p4 => sp4,
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p4 => sp4,
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p5 => sp5,
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p5 => sp5,
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p6 => sp6,
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p6 => sp6,
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p7 => sp7,
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p7 => sp7,
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p8 => sp8,
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p8 => sp8,
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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ax => sreg_block(reg_ax),
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ax => sreg_block(reg_ax),
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ay => sreg_block(reg_ay),
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ay => sreg_block(reg_ay),
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az => sreg_block(reg_az),
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az => sreg_block(reg_az),
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bx => sreg_block(reg_bx),
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bx => sreg_block(reg_bx),
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by => sreg_block(reg_by),
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by => sreg_block(reg_by),
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bz => sreg_block(reg_bz),
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bz => sreg_block(reg_bz),
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vx => svx,
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vx => svx,
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vy => svy,
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vy => svy,
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vz => svz,
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vz => svz,
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sc => ssc,
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sc => ssc,
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ack => sr_ack,
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ack => sr_ack,
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empty => sr_e,
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empty => sr_e,
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dcs => sreg_block(reg_ctrl)(reg_ctrl_d downto reg_ctrl_s),
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dcs => sreg_block(reg_ctrl)(reg_ctrl_d downto reg_ctrl_s),
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sync_chain_1 => ssync_chain_1,
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sync_chain_1 => ssync_chain_1,
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pipeline_pending => spipeline_pending
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pipeline_pending => spipeline_pending
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);
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);
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--! ******************************************************************************************************************************************************
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--! ******************************************************************************************************************************************************
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--! TRANSFER CONTROL RTL CODE
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--! TRANSFER CONTROL RTL CODE
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--! ******************************************************************************************************************************************************
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--! ******************************************************************************************************************************************************
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TRANSFER_CONTROL:
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TRANSFER_CONTROL:
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process(clk,rst,master_waitrequest,sm,soutb_ae,soutb_usedw,spipeline_pending,soutb_e,zero,soutb_af,sfetch_data_pending,sreg_block,sslave_write,sslave_address,sslave_writedata,ssync_chain_pending,smaster_read,smaster_write,sdata_fetch_counter,sload_add_pending,swrite_pending,sdownload_chain)
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process(clk,rst,master_waitrequest,sm,soutb_ae,soutb_usedw,spipeline_pending,soutb_e,zero,soutb_af,sfetch_data_pending,sreg_block,sslave_write,sslave_address,sslave_writedata,ssync_chain_pending,smaster_read,smaster_write,sdata_fetch_counter,sload_add_pending,swrite_pending,sdownload_chain)
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begin
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begin
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--! Conexióln a señales externas.
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--! Conexióln a señales externas.
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irq <= sreg_block(reg_ctrl)(reg_ctrl_irq);
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irq <= sreg_block(reg_ctrl)(reg_ctrl_irq);
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master_read <= smaster_read;
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master_read <= smaster_read;
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master_write <= smaster_write;
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master_write <= smaster_write;
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--! Direct Memory Access Selector.
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--! Direct Memory Access Selector.
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--! ZERO_TRANSIT: Cuando todos los elementos de sincronización están en cero menos la cola de sincronización de carga de parametros.
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--! ZERO_TRANSIT: Cuando todos los elementos de sincronización están en cero menos la cola de sincronización de carga de parametros.
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sZeroTransit <= not(sload_add_pending or sfetch_data_pending or spipeline_pending or swrite_pending);
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sZeroTransit <= not(sload_add_pending or sfetch_data_pending or spipeline_pending or swrite_pending);
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--! ELEMENTO DE SINCRONIZACION OUT QUEUE: Datos pendientes por cargar a la memoria a través de la interconexión
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--! ELEMENTO DE SINCRONIZACION OUT QUEUE: Datos pendientes por cargar a la memoria a través de la interconexión
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swrite_pending <= not(soutb_e);
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swrite_pending <= not(soutb_e);
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--! ELEMENTO DE SINCRONIZACION DESCARGA DE DATOS: Hay datos pendientes por descargar desde la memoria a través de la interconexión.
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--! ELEMENTO DE SINCRONIZACION DESCARGA DE DATOS: Hay datos pendientes por descargar desde la memoria a través de la interconexión.
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if sdata_fetch_counter=zero(reg_nfetch_high downto 0) then
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if sdata_fetch_counter=zero(reg_nfetch_high downto 0) then
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sfetch_data_pending <= '0';
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sfetch_data_pending <= '0';
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else
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else
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sfetch_data_pending <= '1';
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sfetch_data_pending <= '1';
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end if;
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end if;
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--! ELEMENTO DE SINCRONIZACION CARGA DE DIRECCIONES: Hay direcciones pendientes por cargar a la interconexión?
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--! ELEMENTO DE SINCRONIZACION CARGA DE DIRECCIONES: Hay direcciones pendientes por cargar a la interconexión?
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if sreg_block(reg_nfetch)(reg_nfetch_high downto 0)=zero(reg_nfetch_high downto 0) then
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if sreg_block(reg_nfetch)(reg_nfetch_high downto 0)=zero(reg_nfetch_high downto 0) then
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sload_add_pending <= '0';
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sload_add_pending <= '0';
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else
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else
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sload_add_pending <= '1';
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sload_add_pending <= '1';
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end if;
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end if;
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--! ELEMENTO DE SINCRONIZACION CARGA DE OPERANDOS: Se están cargando los operandos que serán operados en el pipeline aritmético.
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--! ELEMENTO DE SINCRONIZACION CARGA DE OPERANDOS: Se están cargando los operandos que serán operados en el pipeline aritmético.
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if sdownload_chain /= DWAX and sdownload_chain /= DWAXBX then
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if sdownload_chain /= DWAX and sdownload_chain /= DWAXBX then
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sparamload_pending <= '1';
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sparamload_pending <= '1';
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else
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else
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sparamload_pending <= '0';
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sparamload_pending <= '0';
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end if;
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end if;
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--! Se debe iniciar una transacción de descarga de datos desde la memoria externa?
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--! Se debe iniciar una transacción de descarga de datos desde la memoria externa?
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if soutb_af='0' and sload_add_pending='1' then
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if soutb_af='0' and sload_add_pending='1' then
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--! Flow Control : La saturación de la cola de resultados continuará si no está tan llena y además hay pendientes datos por ser descargados.
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--! Flow Control : La saturación de la cola de resultados continuará si no está tan llena y además hay pendientes datos por ser descargados.
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sflood_condition <= '1';
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sflood_condition <= '1';
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else
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else
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--! Flow Control : La saturación de la cola de resultados debe parar porque está casí llena.
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--! Flow Control : La saturación de la cola de resultados debe parar porque está casí llena.
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sflood_condition <= '0';
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sflood_condition <= '0';
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end if;
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end if;
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if sreg_block(reg_nfetch)(reg_nfetch_high downto mb)/=zero(reg_nfetch_high downto mb) then
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if sreg_block(reg_nfetch)(reg_nfetch_high downto mb)/=zero(reg_nfetch_high downto mb) then
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--! Flow Control: Si el número de descargas pendientes es mayor o igual al max burst length, entonces cargar max burst en el contador.
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--! Flow Control: Si el número de descargas pendientes es mayor o igual al max burst length, entonces cargar max burst en el contador.
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sflood_burstcount <= '1'&zero(mb-1 downto 0);
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sflood_burstcount <= '1'&zero(mb-1 downto 0);
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else
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else
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--! Flow Control: Si le número de descargas pendientes es inferior a Max Burst Count entonces cargar los bits menos significativos del registro de descargas pendientes.
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--! Flow Control: Si le número de descargas pendientes es inferior a Max Burst Count entonces cargar los bits menos significativos del registro de descargas pendientes.
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sflood_burstcount <= '0'&sreg_block(reg_nfetch)(mb-1 downto 0);
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sflood_burstcount <= '0'&sreg_block(reg_nfetch)(mb-1 downto 0);
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end if;
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end if;
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--! Se debe iniciar una transacción de carga de datos hacia la memoria externa?
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--! Se debe iniciar una transacción de carga de datos hacia la memoria externa?
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if soutb_ae='1' then
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if soutb_ae='1' then
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--! Flow Control : Cuando se esté drenando la cola de resultados, si la cola está casí vac&iaute;a, la longitud del burst serán los bits menos significativos del contador de la cola.
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--! Flow Control : Cuando se esté drenando la cola de resultados, si la cola está casí vac&iaute;a, la longitud del burst serán los bits menos significativos del contador de la cola.
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sdrain_burstcount <= soutb_usedw(mb downto 0);
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sdrain_burstcount <= soutb_usedw(mb downto 0);
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--! Flow Control: El drenado de datos continuará si el número de datos en la cola bajo y no hay datos transitando por el pipeline, ni datos pendientes por cargar desde la memoria.
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--! Flow Control: El drenado de datos continuará si el número de datos en la cola bajo y no hay datos transitando por el pipeline, ni datos pendientes por cargar desde la memoria.
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sdrain_condition <= not(sload_add_pending) and not(sfetch_data_pending) and not(spipeline_pending) and swrite_pending;
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sdrain_condition <= not(sload_add_pending) and not(sfetch_data_pending) and not(spipeline_pending) and swrite_pending;
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else
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else
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--! Flow Control: Cuando se esté drenando la cola de resultados, si la cola de tiene una cantidad de datos mayor al burst count entonces se hará una transacción de longitud equivalente al burst count.
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--! Flow Control: Cuando se esté drenando la cola de resultados, si la cola de tiene una cantidad de datos mayor al burst count entonces se hará una transacción de longitud equivalente al burst count.
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sdrain_burstcount <= '1'&zero(mb-1 downto 0);
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sdrain_burstcount <= '1'&zero(mb-1 downto 0);
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--! Flow Control: El drenado de datos continuará si el número de datos en la cola es mayor o igual a 2**mb O si hay muy pocos datos y no hay datos transitando por el pipeline.
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--! Flow Control: El drenado de datos continuará si el número de datos en la cola es mayor o igual a 2**mb O si hay muy pocos datos y no hay datos transitando por el pipeline.
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sdrain_condition <= '1';
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sdrain_condition <= '1';
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end if;
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end if;
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--! Restart param load chain
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srestart_chain <= sreg_block(reg_ctrl)(reg_ctrl_irq) and sreg_block(reg_ctrl)(reg_ctrl_rlsc);
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--! Data dumpster: Descaratar dato de upload una vez la interconexión haya enganchado el dato.
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--! Data dumpster: Descaratar dato de upload una vez la interconexión haya enganchado el dato.
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if sm=SINK and master_waitrequest='0' and smaster_write='1' then
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if sm=SINK and master_waitrequest='0' and smaster_write='1' then
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soutb_ack <= '1';
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soutb_ack <= '1';
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else
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else
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soutb_ack <= '0';
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soutb_ack <= '0';
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end if;
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end if;
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--! Flow Control State Machine.
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--! Flow Control State Machine.
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if rst=rstMasterValue then
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if rst=rstMasterValue then
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--! State Machine
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--! State Machine
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sm <= IDLE;
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sm <= IDLE;
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--! Master Write & Read Common Signals Reset Value
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--! Master Write & Read Common Signals Reset Value
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master_burstcount <= (others => '0');
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master_burstcount <= (others => '0');
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master_address <= (others => '0');
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master_address <= (others => '0');
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sdata_fetch_counter <= (others => '0');
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sdata_fetch_counter <= (others => '0');
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sburstcount_sink <= (others => '0');
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sburstcount_sink <= (others => '0');
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--! Master Read Only Signals Reset Value
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--! Master Read Only Signals Reset Value
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smaster_read <= '0';
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smaster_read <= '0';
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--! Master Write Only Signals
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--! Master Write Only Signals
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smaster_write <= '0';
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smaster_write <= '0';
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--! Reg Ctrl & Fetch address and writeaddress
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--! Reg Ctrl & Fetch address and writeaddress
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--! Sinking address
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--! Sinking address
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sreg_block(reg_sinkstart) <= (others => '0');
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sreg_block(reg_sinkstart) <= (others => '0');
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--! Sourcing address
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--! Sourcing address
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sreg_block(reg_fetchstart) <= (others => '0');
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sreg_block(reg_fetchstart) <= (others => '0');
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--! Control and Status Register
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--! Control and Status Register
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sreg_block(reg_ctrl) <= (others => '0');
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sreg_block(reg_ctrl) <= (others => '0');
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--! Contador Overall
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--! Contador Overall
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sreg_block(reg_inputcounter) <= (others => '0');
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sreg_block(reg_inputcounter) <= (others => '0');
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sreg_block(reg_outputcounter) <= (others => '0');
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-- sreg_block(reg_timercounter) <= (others => '0');
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--! Address Fetch Counter
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--! Address Fetch Counter
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sreg_block(reg_nfetch) <= (others => '0');
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sreg_block(reg_nfetch) <= (others => '0');
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elsif clk'event and clk='1' then
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elsif clk'event and clk='1' then
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--! Nevermind the State, discount the incoming valid data counter.
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--! Nevermind the State, discount the incoming valid data counter.
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sdata_fetch_counter <= sdata_fetch_counter-master_readdatavalid;
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sdata_fetch_counter <= sdata_fetch_counter-master_readdatavalid;
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--! Debug Counter.
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--! Debug Counter.
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sreg_block(reg_inputcounter) <= sreg_block(reg_inputcounter) + master_readdatavalid;
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sreg_block(reg_inputcounter) <= sreg_block(reg_inputcounter) + master_readdatavalid;
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sreg_block(reg_outputcounter) <= sreg_block(reg_outputcounter) + soutb_ack;
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--!Timer Counter.
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-- case sm is
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-- when IDLE =>
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-- sreg_block(reg_timercounter) <= sreg_block(reg_timercounter) + 0;
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-- when others =>
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-- sreg_block(reg_timercounter) <= sreg_block(reg_timercounter) + 1;
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-- end case;
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--! Flags
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--! Flags
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case sm is
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case sm is
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when SOURCE =>
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when SOURCE =>
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--! ******************************************************************************************************************************************************
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--! ******************************************************************************************************************************************************
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--! Flooding the pipeline ........
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--! Flooding the pipeline ........
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--! ******************************************************************************************************************************************************
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--! ******************************************************************************************************************************************************
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if smaster_read='0' then
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if smaster_read='0' then
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if sflood_condition = '1' then
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if sflood_condition = '1' then
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--! Flow Control: Hay suficiente espacio en el buffer de salida y hay descargas pendientes por hacer
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--! Flow Control: Hay suficiente espacio en el buffer de salida y hay descargas pendientes por hacer
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smaster_read <= '1';
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smaster_read <= '1';
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master_address <= sreg_block(reg_fetchstart);
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master_address <= sreg_block(reg_fetchstart);
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master_burstcount <= sflood_burstcount;
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master_burstcount <= sflood_burstcount;
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sdata_fetch_counter <= sdata_fetch_counter+sflood_burstcount-master_readdatavalid;
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sdata_fetch_counter <= sdata_fetch_counter+sflood_burstcount-master_readdatavalid;
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--! Context Saving:
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--! Context Saving:
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sreg_block(reg_fetchstart) <= sreg_block(reg_fetchstart) + (sflood_burstcount&"00");
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sreg_block(reg_fetchstart) <= sreg_block(reg_fetchstart) + (sflood_burstcount&"00");
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sreg_block(reg_nfetch)(reg_nfetch_high downto 0) <= sreg_block(reg_nfetch)(reg_nfetch_high downto 0) - sflood_burstcount;
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sreg_block(reg_nfetch)(reg_nfetch_high downto 0) <= sreg_block(reg_nfetch)(reg_nfetch_high downto 0) - sflood_burstcount;
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else
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else
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--! Flow Control : Cambiar al estado SINK, porque o está muy llena la cola de salida o no hay descargas pendientes por realizar.
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--! Flow Control : Cambiar al estado SINK, porque o está muy llena la cola de salida o no hay descargas pendientes por realizar.
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sm <= SINK;
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sm <= SINK;
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end if;
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end if;
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else --master_read=1;
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else --master_read=1;
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if master_waitrequest='0' then
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if master_waitrequest='0' then
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--! Las direcciones de lectura están cargadas. Terminar la transferencia.
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--! Las direcciones de lectura están cargadas. Terminar la transferencia.
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smaster_read <= '0';
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smaster_read <= '0';
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end if;
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end if;
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end if;
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end if;
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when SINK =>
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when SINK =>
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--! ******************************************************************************************************************************************************
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--! ******************************************************************************************************************************************************
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--! Draining the pipeline ........
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--! Draining the pipeline ........
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--! ******************************************************************************************************************************************************
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--! ******************************************************************************************************************************************************
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if smaster_write='0' then
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if smaster_write='0' then
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if sdrain_condition='1' then
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if sdrain_condition='1' then
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--! Flow Control : Hay muchos datos aun en la cola de resultados Ó la cola de resultados está casí vacía y no hay datos transitando en el pipeline aritm&eetico.
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--! Flow Control : Hay muchos datos aun en la cola de resultados Ó la cola de resultados está casí vacía y no hay datos transitando en el pipeline aritm&eetico.
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smaster_write <= '1';
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smaster_write <= '1';
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master_address <= sreg_block(reg_sinkstart);
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master_address <= sreg_block(reg_sinkstart);
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master_burstcount <= sdrain_burstcount;
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master_burstcount <= sdrain_burstcount;
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--!Context Saving
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--!Context Saving
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sreg_block(reg_sinkstart) <= sreg_block(reg_sinkstart) + (sdrain_burstcount&"00");
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sreg_block(reg_sinkstart) <= sreg_block(reg_sinkstart) + (sdrain_burstcount&"00");
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sburstcount_sink <= sdrain_burstcount-1;
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sburstcount_sink <= sdrain_burstcount-1;
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else
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else
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--! Flow Control: Son muy pocos los datos que hay en el buffer de salida y existen aun datos transitando en el resto del pipe ir al estado SOURCE.
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--! Flow Control: Son muy pocos los datos que hay en el buffer de salida y existen aun datos transitando en el resto del pipe ir al estado SOURCE.
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if sZeroTransit='1' then
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if sZeroTransit='1' then
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--! Flow Control: Finalizada la instrucción, generar una interrupción e ir al estado IDLE.
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--! Flow Control: Finalizada la instrucción, generar una interrupción e ir al estado IDLE.
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sm <= IDLE;
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sm <= IDLE;
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sreg_block(reg_ctrl)(reg_ctrl_irq) <= '1';
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sreg_block(reg_ctrl)(reg_ctrl_irq) <= '1';
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sreg_block(reg_ctrl)(reg_ctrl_rom) <= '0';
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sreg_block(reg_ctrl)(reg_ctrl_rom) <= '0';
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sreg_block(reg_ctrl)(reg_ctrl_flags_dc downto reg_ctrl_flags_fc) <= sdrain_condition & sflood_condition;
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sreg_block(reg_ctrl)(reg_ctrl_flags_dc downto reg_ctrl_flags_fc) <= sdrain_condition & sflood_condition;
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sreg_block(reg_ctrl)(reg_ctrl_flags_ap downto reg_ctrl_flags_wp) <= sload_add_pending & sfetch_data_pending & sparamload_pending & spipeline_pending & swrite_pending;
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sreg_block(reg_ctrl)(reg_ctrl_flags_ap downto reg_ctrl_flags_wp) <= sload_add_pending & sfetch_data_pending & sparamload_pending & spipeline_pending & swrite_pending;
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else
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else
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--! Flow Control: Cambiar a Source porque aun hay elementos transitando.
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--! Flow Control: Cambiar a Source porque aun hay elementos transitando.
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sm <= SOURCE;
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sm <= SOURCE;
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end if;
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end if;
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end if;
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end if;
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else --!smaster_write=1
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else --!smaster_write=1
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if master_waitrequest = '0' then
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if master_waitrequest = '0' then
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--! Descartar datos : revisar antes de este proceso secuencial la parte combinatoria (Data Dumpster).
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--! Descartar datos : revisar antes de este proceso secuencial la parte combinatoria (Data Dumpster).
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if sburstcount_sink/=zero(mb downto 0) then
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if sburstcount_sink/=zero(mb downto 0) then
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--! Datos pendientes por transmitir aun en el burst. Restar uno
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--! Datos pendientes por transmitir aun en el burst. Restar uno
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sburstcount_sink <= sburstcount_sink-1;
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sburstcount_sink <= sburstcount_sink-1;
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else
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else
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--! No escribir mas. Finalizar la transmisión
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--! No escribir mas. Finalizar la transmisión
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smaster_write <= '0';
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smaster_write <= '0';
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--! Si no hay transito de dato se con terminada la instrucción siempre que el estado de control de flujo esté sidera
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--! Si no hay transito de dato se con terminada la instrucción siempre que el estado de control de flujo esté sidera
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if sZeroTransit='1' then
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if sZeroTransit='1' then
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--! Flow Control: Finalizada la instrucción, generar una interrupción e ir al estado IDLE.
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--! Flow Control: Finalizada la instrucción, generar una interrupción e ir al estado IDLE.
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sm <= IDLE;
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sm <= IDLE;
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sreg_block(reg_ctrl)(reg_ctrl_irq) <= '1';
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sreg_block(reg_ctrl)(reg_ctrl_irq) <= '1';
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sreg_block(reg_ctrl)(reg_ctrl_rom) <= '0';
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sreg_block(reg_ctrl)(reg_ctrl_rom) <= '0';
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sreg_block(reg_ctrl)(reg_ctrl_flags_dc downto reg_ctrl_flags_fc) <= sdrain_condition & sflood_condition;
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sreg_block(reg_ctrl)(reg_ctrl_flags_dc downto reg_ctrl_flags_fc) <= sdrain_condition & sflood_condition;
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sreg_block(reg_ctrl)(reg_ctrl_flags_ap downto reg_ctrl_flags_wp) <= sload_add_pending & sfetch_data_pending & sparamload_pending & spipeline_pending & swrite_pending;
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sreg_block(reg_ctrl)(reg_ctrl_flags_ap downto reg_ctrl_flags_wp) <= sload_add_pending & sfetch_data_pending & sparamload_pending & spipeline_pending & swrite_pending;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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when IDLE =>
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when IDLE =>
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--! ******************************************************************************************************************************************************
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--! ******************************************************************************************************************************************************
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--! Programming the pipeline
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--! Programming the pipeline
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--! ******************************************************************************************************************************************************
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--! ******************************************************************************************************************************************************
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--! El registro de control en sus campos fetch e irq, es escribile solo cuando estamos en estado IDLE.
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--! El registro de control en sus campos fetch e irq, es escribile solo cuando estamos en estado IDLE.
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if sslave_write='1' then
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if sslave_write='1' then
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case sslave_address is
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case sslave_address is
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when x"0" =>
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when x"0" =>
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--! Solo se permitira escribir en el registro de control si no hay una interrupción activa o si la hay solamente si se esta intentando desactivar la interrupci´n
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--! Solo se permitira escribir en el registro de control si no hay una interrupción activa o si la hay solamente si se esta intentando desactivar la interrupci´n
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if sreg_block(reg_ctrl)(reg_ctrl_irq)='0' or sslave_writedata(reg_ctrl_irq)='0' then
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if sreg_block(reg_ctrl)(reg_ctrl_irq)='0' or sslave_writedata(reg_ctrl_irq)='0' then
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sreg_block(reg_ctrl)<= sslave_writedata;
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sreg_block(reg_ctrl)<= sslave_writedata;
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end if;
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end if;
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when x"5" => sreg_block(reg_nfetch) <= sslave_writedata;
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when x"5" => sreg_block(reg_nfetch) <= sslave_writedata;
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when x"6" => sreg_block(reg_outputcounter) <= sslave_writedata;
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-- when x"6" => sreg_block(reg_timercounter) <= sslave_writedata;
|
when x"7" => sreg_block(reg_inputcounter) <= sslave_writedata;
|
when x"7" => sreg_block(reg_inputcounter) <= sslave_writedata;
|
when x"8" => sreg_block(reg_fetchstart) <= sslave_writedata;
|
when x"8" => sreg_block(reg_fetchstart) <= sslave_writedata;
|
when x"9" => sreg_block(reg_sinkstart) <= sslave_writedata;
|
when x"9" => sreg_block(reg_sinkstart) <= sslave_writedata;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
else
|
else
|
|
|
if sZeroTransit='0' then
|
if sZeroTransit='0' then
|
|
|
|
|
--! Flow Control: Existe un número de descargas programadas por el sistema, comenzar a realizarlas.
|
--! Flow Control: Existe un número de descargas programadas por el sistema, comenzar a realizarlas.
|
--! Ir al estado Source.
|
--! Ir al estado Source.
|
sm <= SOURCE;
|
sm <= SOURCE;
|
sreg_block(reg_ctrl)(reg_ctrl_rom) <= '1';
|
sreg_block(reg_ctrl)(reg_ctrl_rom) <= '1';
|
|
|
else
|
else
|
sreg_block(reg_ctrl)(reg_ctrl_rom) <= '0';
|
sreg_block(reg_ctrl)(reg_ctrl_rom) <= '0';
|
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
--! ******************************************************************************************************************************************************
|
--! ******************************************************************************************************************************************************
|
--! FLOW CONTROL RTL CODE
|
--! FLOW CONTROL RTL CODE
|
--! ******************************************************************************************************************************************************
|
--! ******************************************************************************************************************************************************
|
--! buffer de salida
|
--! buffer de salida
|
--! ******************************************************************************************************************************************************
|
--! ******************************************************************************************************************************************************
|
output_buffer:scfifo
|
output_buffer:scfifo
|
generic map (almost_empty_value => 2**mb,almost_full_value => (2**fd)-52, lpm_widthu => fd, lpm_numwords => 2**fd, lpm_showahead => "ON", lpm_width => 32, overflow_checking => "ON", underflow_checking => "ON", use_eab => "ON")
|
generic map (almost_empty_value => 2**mb,almost_full_value => (2**fd)-52, lpm_widthu => fd, lpm_numwords => 2**fd, lpm_showahead => "ON", lpm_width => 32, overflow_checking => "ON", underflow_checking => "ON", use_eab => "ON")
|
port map (empty => soutb_e, aclr => '0', clock => clk, rdreq => soutb_ack, wrreq => soutb_w, q => master_writedata, usedw => soutb_usedw, almost_full => soutb_af, almost_empty => soutb_ae, data => soutb_d);
|
port map (empty => soutb_e, aclr => '0', clock => clk, rdreq => soutb_ack, wrreq => soutb_w, q => master_writedata, usedw => soutb_usedw, almost_full => soutb_af, almost_empty => soutb_ae, data => soutb_d);
|
--! ******************************************************************************************************************************************************
|
--! ******************************************************************************************************************************************************
|
--! PROCESO DE CONTROL DE FLUJO ENTRE EL BUFFER DE RESULTADOS Y EL BUFFER DE SALIDA
|
--! PROCESO DE CONTROL DE FLUJO ENTRE EL BUFFER DE RESULTADOS Y EL BUFFER DE SALIDA
|
--! ******************************************************************************************************************************************************
|
--! ******************************************************************************************************************************************************
|
|
|
FLOW_CONTROL_OUTPUT_STAGE:
|
FLOW_CONTROL_OUTPUT_STAGE:
|
process (clk,rst,master_readdata, master_readdatavalid,sr_e,sreg_block(reg_ctrl)(reg_ctrl_vt downto reg_ctrl_sc),sm,supload_chain,zero,ssync_chain_pending,supload_start)
|
process (clk,rst,master_readdata, master_readdatavalid,sr_e,sreg_block(reg_ctrl)(reg_ctrl_vt downto reg_ctrl_sc),sm,supload_chain,zero,ssync_chain_pending,supload_start)
|
begin
|
begin
|
|
|
|
|
--! Compute initial State.
|
--! Compute initial State.
|
|
|
--! Escribir en el output buffer.
|
--! Escribir en el output buffer.
|
if supload_chain=DMA then
|
if supload_chain=DMA then
|
--! Modo DMA escribir los datos de entrada directamente en el buffer.
|
--! Modo DMA escribir los datos de entrada directamente en el buffer.
|
soutb_w <= master_readdatavalid;
|
soutb_w <= master_readdatavalid;
|
else
|
else
|
--!Modo Arithmetic Pipeline
|
--!Modo Arithmetic Pipeline
|
soutb_w <= not(sr_e);
|
soutb_w <= not(sr_e);
|
end if;
|
end if;
|
|
|
--! Control de lectura de la cola de resultados.
|
--! Control de lectura de la cola de resultados.
|
if sr_e='0' then
|
if sr_e='0' then
|
--!Hay datos en la cola de resultados.
|
--!Hay datos en la cola de resultados.
|
if (supload_chain=UPVZ and sreg_block(reg_ctrl)(reg_ctrl_sc)='0') or supload_chain=SC then
|
if (supload_chain=UPVZ and sreg_block(reg_ctrl)(reg_ctrl_sc)='0') or supload_chain=SC then
|
--!Se transfiere el ultimo componente vectorial y no se estan cargando resultados escalares.
|
--!Se transfiere el ultimo componente vectorial y no se estan cargando resultados escalares.
|
sr_ack <= '1';
|
sr_ack <= '1';
|
else
|
else
|
sr_ack <= '0';
|
sr_ack <= '0';
|
end if;
|
end if;
|
else
|
else
|
sr_ack <= '0';
|
sr_ack <= '0';
|
end if;
|
end if;
|
|
|
|
|
--! Decodificar que salida de la cola de resultados se conecta a la entrada del otput buffer
|
--! Decodificar que salida de la cola de resultados se conecta a la entrada del otput buffer
|
--! DMA Path Control: Si se encuentra habilitado el modo dma entonces conectar la entrada del buffer de salida a la interconexión
|
--! DMA Path Control: Si se encuentra habilitado el modo dma entonces conectar la entrada del buffer de salida a la interconexión
|
case supload_chain is
|
case supload_chain is
|
when UPVX =>
|
when UPVX =>
|
soutb_d <= svx;
|
soutb_d <= svx;
|
when UPVY =>
|
when UPVY =>
|
soutb_d <= svy;
|
soutb_d <= svy;
|
when UPVZ =>
|
when UPVZ =>
|
soutb_d <= svz;
|
soutb_d <= svz;
|
when SC =>
|
when SC =>
|
soutb_d <= ssc;
|
soutb_d <= ssc;
|
when DMA =>
|
when DMA =>
|
soutb_d <= master_readdata;
|
soutb_d <= master_readdata;
|
end case;
|
end case;
|
|
|
|
|
case sreg_block(reg_ctrl)(reg_ctrl_vt downto reg_ctrl_sc) is
|
case sreg_block(reg_ctrl)(reg_ctrl_vt downto reg_ctrl_sc) is
|
when "01" =>
|
when "01" =>
|
supload_start <= SC;
|
supload_start <= SC;
|
when others =>
|
when others =>
|
supload_start <= UPVX;
|
supload_start <= UPVX;
|
end case;
|
end case;
|
|
|
|
|
--! Máquina de estados para el width adaptation RES(128) -> OUTPUTBUFFER(32).
|
--! Máquina de estados para el width adaptation RES(128) -> OUTPUTBUFFER(32).
|
if rst=rstMasterValue then
|
if rst=rstMasterValue then
|
supload_chain <= UPVX;
|
supload_chain <= UPVX;
|
elsif clk'event and clk='1' and sreg_block(reg_ctrl)(reg_ctrl_dma)='0' then
|
elsif clk'event and clk='1' and sreg_block(reg_ctrl)(reg_ctrl_dma)='0' then
|
--! Modo de operación normal.
|
--! Modo de operación normal.
|
case supload_chain is
|
case supload_chain is
|
when UPVX =>
|
when UPVX =>
|
if sr_e='1' then
|
if sr_e='1' then
|
supload_chain <= supload_start;
|
supload_chain <= supload_start;
|
else
|
else
|
supload_chain <= UPVY;
|
supload_chain <= UPVY;
|
end if;
|
end if;
|
when UPVY =>
|
when UPVY =>
|
supload_chain <= UPVZ;
|
supload_chain <= UPVZ;
|
when UPVZ =>
|
when UPVZ =>
|
if sreg_block(reg_ctrl)(reg_ctrl_sc)='0' then
|
if sreg_block(reg_ctrl)(reg_ctrl_sc)='0' then
|
supload_chain <= UPVX;
|
supload_chain <= UPVX;
|
else
|
else
|
supload_chain <= SC;
|
supload_chain <= SC;
|
end if;
|
end if;
|
when SC|DMA =>
|
when SC|DMA =>
|
supload_chain <= supload_start;
|
supload_chain <= supload_start;
|
|
|
end case;
|
end case;
|
|
|
elsif clk'event and clk='1' then
|
elsif clk'event and clk='1' then
|
--! Modo DMA
|
--! Modo DMA
|
supload_chain <= DMA;
|
supload_chain <= DMA;
|
end if;
|
end if;
|
|
|
|
|
end process;
|
end process;
|
--! ******************************************************************************************************************************************************
|
--! ******************************************************************************************************************************************************
|
--! PROCESO DE CONTROL DE FLUJO ENTRE LA ENTRADA DESDE LA INTERCONEXI&OACUTE;N Y LOS PARAMETROS DE ENTRADA EN EL PIPELINE ARITMETICO
|
--! PROCESO DE CONTROL DE FLUJO ENTRE LA ENTRADA DESDE LA INTERCONEXI&OACUTE;N Y LOS PARAMETROS DE ENTRADA EN EL PIPELINE ARITMETICO
|
--! ******************************************************************************************************************************************************
|
--! ******************************************************************************************************************************************************
|
FLOW_CONTROL_INPUT_STAGE:
|
FLOW_CONTROL_INPUT_STAGE:
|
process(clk,rst,master_readdatavalid,master_readdata,sreg_block(reg_ctrl)(reg_ctrl_dma downto reg_ctrl_s),sslave_write,sslave_address,supload_chain)
|
process(clk,rst,master_readdatavalid,master_readdata,sreg_block(reg_ctrl)(reg_ctrl_dma downto reg_ctrl_s),sslave_write,sslave_address,supload_chain)
|
begin
|
begin
|
--! Está ocurriendo un evento de transición del estado TX al estado FETCH: Programar el enganche de parámetros que vienen de la interconexión.
|
--! Está ocurriendo un evento de transición del estado TX al estado FETCH: Programar el enganche de parámetros que vienen de la interconexión.
|
--! Mirar como es la carga inicial. Si es Normalizacion o Magnitud (dcs=110) entonces cargar DWAXBX de lo contrario solo DWAX.
|
--! Mirar como es la carga inicial. Si es Normalizacion o Magnitud (dcs=110) entonces cargar DWAXBX de lo contrario solo DWAX.
|
case sreg_block(reg_ctrl)(reg_ctrl_d downto reg_ctrl_s) is
|
case sreg_block(reg_ctrl)(reg_ctrl_d downto reg_ctrl_s) is
|
when "110" => sdownload_start <= DWAXBX;
|
when "110" => sdownload_start <= DWAXBX;
|
when others => sdownload_start <= DWAX;
|
when others => sdownload_start <= DWAX;
|
end case;
|
end case;
|
if rst=rstMasterValue then
|
if rst=rstMasterValue then
|
ssync_chain_1 <= '0';
|
ssync_chain_1 <= '0';
|
sdownload_chain <= DWAX;
|
sdownload_chain <= DWAX;
|
for i in reg_bz downto reg_ax loop
|
for i in reg_bz downto reg_ax loop
|
sreg_block(i) <= (others => '0');
|
sreg_block(i) <= (others => '0');
|
end loop;
|
end loop;
|
elsif clk'event and clk='1' then
|
elsif clk'event and clk='1' then
|
ssync_chain_1 <= '0';
|
ssync_chain_1 <= '0';
|
if master_readdatavalid='1' and sreg_block(reg_ctrl)(reg_ctrl_dma)='0' then
|
if master_readdatavalid='1' and sreg_block(reg_ctrl)(reg_ctrl_dma)='0' and (sreg_block(reg_ctrl)(reg_ctrl_irq)='0' or sreg_block(reg_ctrl)(reg_ctrl_rlsc)='0') then
|
--! El dato en la interconexión es valido, se debe enganchar.
|
--! El dato en la interconexión es valido, se debe enganchar.
|
case sdownload_chain is
|
case sdownload_chain is
|
when DWAX | DWAXBX =>
|
when DWAX | DWAXBX =>
|
--! Cargar el operando correspondiente al componente "X" del vector "A"
|
--! Cargar el operando correspondiente al componente "X" del vector "A"
|
ssync_chain_1 <= '0';
|
ssync_chain_1 <= '0';
|
sreg_block(reg_ax) <= master_readdata;
|
sreg_block(reg_ax) <= master_readdata;
|
if sdownload_start = DWAXBX then
|
if sdownload_start = DWAXBX then
|
--! Operación Unaria por ejemplo magnitud de un vector
|
--! Operación Unaria por ejemplo magnitud de un vector
|
--! Escribir en el registro bx adicionalmente.
|
--! Escribir en el registro bx adicionalmente.
|
sreg_block(reg_bx) <= master_readdata;
|
sreg_block(reg_bx) <= master_readdata;
|
--! El siguiente estado es cargar el componente "Y" de del operando a ejecutar.
|
--! El siguiente estado es cargar el componente "Y" de del operando a ejecutar.
|
sdownload_chain <= DWAYBY;
|
sdownload_chain <= DWAYBY;
|
else
|
else
|
--! Operación de dos operandos. Por ejemplo Producto Cruz.
|
--! Operación de dos operandos. Por ejemplo Producto Cruz.
|
--! El siguiente estado es cargar el vector "Y" del operando "A".
|
--! El siguiente estado es cargar el vector "Y" del operando "A".
|
sdownload_chain <= DWAY;
|
sdownload_chain <= DWAY;
|
end if;
|
end if;
|
when DWAY | DWAYBY =>
|
when DWAY | DWAYBY =>
|
sreg_block(reg_ay) <= master_readdata;
|
sreg_block(reg_ay) <= master_readdata;
|
ssync_chain_1 <= '0';
|
ssync_chain_1 <= '0';
|
if sdownload_chain = DWAYBY then
|
if sdownload_chain = DWAYBY then
|
sreg_block(reg_by) <= master_readdata;
|
sreg_block(reg_by) <= master_readdata;
|
sdownload_chain <= DWAZBZ;
|
sdownload_chain <= DWAZBZ;
|
else
|
else
|
sdownload_chain <= DWAZ;
|
sdownload_chain <= DWAZ;
|
end if;
|
end if;
|
when DWAZ | DWAZBZ =>
|
when DWAZ | DWAZBZ =>
|
sreg_block(reg_az) <= master_readdata;
|
sreg_block(reg_az) <= master_readdata;
|
if sdownload_chain=DWAZBZ then
|
if sdownload_chain=DWAZBZ then
|
ssync_chain_1 <= '1';
|
ssync_chain_1 <= '1';
|
sreg_block(reg_bz) <= master_readdata;
|
sreg_block(reg_bz) <= master_readdata;
|
sdownload_chain <= DWAXBX;
|
sdownload_chain <= DWAXBX;
|
else
|
else
|
ssync_chain_1 <= '0';
|
ssync_chain_1 <= '0';
|
sdownload_chain <= DWBX;
|
sdownload_chain <= DWBX;
|
end if;
|
end if;
|
when DWBX =>
|
when DWBX =>
|
ssync_chain_1 <= '0';
|
ssync_chain_1 <= '0';
|
sreg_block(reg_bx) <= master_readdata;
|
sreg_block(reg_bx) <= master_readdata;
|
sdownload_chain <= DWBY;
|
sdownload_chain <= DWBY;
|
when DWBY =>
|
when DWBY =>
|
ssync_chain_1 <= '0';
|
ssync_chain_1 <= '0';
|
sreg_block(reg_by) <= master_readdata;
|
sreg_block(reg_by) <= master_readdata;
|
sdownload_chain <= DWBZ;
|
sdownload_chain <= DWBZ;
|
when DWBZ =>
|
when DWBZ =>
|
sreg_block(reg_bz) <= master_readdata;
|
sreg_block(reg_bz) <= master_readdata;
|
ssync_chain_1 <= '1';
|
ssync_chain_1 <= '1';
|
if sreg_block(reg_ctrl)(reg_ctrl_cmb)='1' then
|
if sreg_block(reg_ctrl)(reg_ctrl_cmb)='1' then
|
sdownload_chain <= DWBX;
|
sdownload_chain <= DWBX;
|
else
|
else
|
sdownload_chain <= DWAX;
|
sdownload_chain <= DWAX;
|
end if;
|
end if;
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
|
--! Ok operation check if operation has ended. If that's the case.
|
if srestart_chain='1' then
|
elsif sreg_block(reg_ctrl)(reg_ctrl_irq)='1' and sreg_block(reg_ctrl)(reg_ctrl_rlsc)='1' then
|
sdownload_chain <= sdownload_start;
|
sdownload_chain <= sdownload_start;
|
end if;
|
end if;
|
|
|
end if;
|
|
end if;
|
end if;
|
end process;
|
end process;
|
--! *************************************************************************************************************************************************************************************************************************************************************
|
--! *************************************************************************************************************************************************************************************************************************************************************
|
--! AVALON MEMORY MAPPED MASTER FINISHED
|
--! AVALON MEMORY MAPPED MASTER FINISHED
|
--! *************************************************************************************************************************************************************************************************************************************************************
|
--! *************************************************************************************************************************************************************************************************************************************************************
|
--! *************************************************************************************************************************************************************************************************************************************************************
|
--! *************************************************************************************************************************************************************************************************************************************************************
|
--! AVALON MEMORY MAPPED SLAVE BEGINS => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
|
--! AVALON MEMORY MAPPED SLAVE BEGINS => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
|
--! *************************************************************************************************************************************************************************************************************************************************************
|
--! *************************************************************************************************************************************************************************************************************************************************************
|
--! Master Slave Process: Proceso para la escritura y lectura de registros desde el NIOS II.
|
--! Master Slave Process: Proceso para la escritura y lectura de registros desde el NIOS II.
|
low_register_bank:
|
low_register_bank:
|
process (clk,rst,sreg_block,soutb_w,supload_chain)
|
process (clk,rst,sreg_block,soutb_w,supload_chain)
|
begin
|
begin
|
if rst=rstMasterValue then
|
if rst=rstMasterValue then
|
for i in reg_scalar downto reg_vz loop
|
for i in reg_scalar downto reg_vz loop
|
sreg_block(i) <= (others => '0');
|
sreg_block(i) <= (others => '0');
|
end loop;
|
end loop;
|
|
sreg_block(reg_timercounter) <= (others => '0');
|
slave_readdata <= (others => '0');
|
slave_readdata <= (others => '0');
|
sslave_address <= (others => '0');
|
sslave_address <= (others => '0');
|
sslave_writedata <= (others => '0');
|
sslave_writedata <= (others => '0');
|
sslave_write <= '0';
|
sslave_write <= '0';
|
sslave_read <= '0';
|
sslave_read <= '0';
|
elsif clk'event and clk='1' then
|
elsif clk'event and clk='1' then
|
|
|
|
|
sslave_address <= slave_address;
|
sslave_address <= slave_address;
|
sslave_write <= slave_write;
|
sslave_write <= slave_write;
|
sslave_read <= slave_read;
|
sslave_read <= slave_read;
|
sslave_writedata <= slave_writedata;
|
sslave_writedata <= slave_writedata;
|
|
|
for i in reg_scalar downto reg_scalar loop
|
if sslave_write='1' and sslave_address=reg_timercounter then
|
if sslave_address=i then
|
sreg_block(reg_timercounter) <= sslave_writedata;
|
if sslave_write='1' then
|
else
|
sreg_block(i) <= sslave_writedata;
|
sreg_block(reg_timercounter) <= sreg_block(reg_timercounter)+1;
|
end if;
|
end if;
|
|
|
|
if sslave_write='1' and sslave_address=reg_scalar then
|
|
sreg_block(reg_scalar) <= sslave_writedata;
|
|
else
|
|
sreg_block(reg_scalar) <= sreg_block(reg_scalar);
|
end if;
|
end if;
|
end loop;
|
|
|
-- for i in reg_scalar downto reg_scalar loop
|
|
-- if sslave_address=i then
|
|
-- if sslave_write='1' then
|
|
-- sreg_block(i) <= sslave_writedata;
|
|
-- end if;
|
|
-- end if;
|
|
-- end loop;
|
for i in 15 downto 0 loop
|
for i in 15 downto 0 loop
|
if sslave_address=i then
|
if sslave_address=i then
|
if sslave_read='1' then
|
if sslave_read='1' then
|
|
|
if (i<10 and i>3) or i=0 then
|
if (i<10 and i>3) or i=0 then
|
slave_readdata <= sreg_block(i);
|
slave_readdata <= sreg_block(i);
|
elsif i=1 then
|
elsif i=1 then
|
slave_readdata <= sp0;
|
slave_readdata <= sp0;
|
elsif i=2 then
|
elsif i=2 then
|
slave_readdata <= sp1;
|
slave_readdata <= sp1;
|
elsif i=3 then
|
elsif i=3 then
|
slave_readdata <= sp2;
|
slave_readdata <= sp2;
|
elsif i=10 then
|
elsif i=10 then
|
slave_readdata <= sp3;
|
slave_readdata <= sp3;
|
elsif i=11 then
|
elsif i=11 then
|
slave_readdata <= sp4;
|
slave_readdata <= sp4;
|
elsif i=12 then
|
elsif i=12 then
|
slave_readdata <= sp5;
|
slave_readdata <= sp5;
|
elsif i=13 then
|
elsif i=13 then
|
slave_readdata <= sp6;
|
slave_readdata <= sp6;
|
elsif i=14 then
|
elsif i=14 then
|
slave_readdata <= sp7;
|
slave_readdata <= sp7;
|
elsif i=15 then
|
elsif i=15 then
|
slave_readdata <= sp8;
|
slave_readdata <= sp8;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end loop;
|
end loop;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
--! *************************************************************************************************************************************************************************************************************************************************************
|
--! *************************************************************************************************************************************************************************************************************************************************************
|
--! AVALON MEMORY MAPPED SLAVE FINISHED
|
--! AVALON MEMORY MAPPED SLAVE FINISHED
|
--! *************************************************************************************************************************************************************************************************************************************************************
|
--! *************************************************************************************************************************************************************************************************************************************************************
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------
|
--! Control Register (reg_ctrl) BASE_ADDRESS + 0x0 |
|
--! Control Register (reg_ctrl) BASE_ADDRESS + 0x0 |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------
|
--! Bit No. | Nombre | Descripción |
|
--! Bit No. | Nombre | Descripción |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------
|
--! 0 | cmb (rw) | 1: La operación es combinatoria, por lo tanto cargan los primeros 3 valores en el Operando A y el |
|
--! 0 | cmb (rw) | 1: La operación es combinatoria, por lo tanto cargan los primeros 3 valores en el Operando A y el |
|
--! | | de vectores en el operando B. |
|
--! | | de vectores en el operando B. |
|
--! | | 0: La operación no es combinatoria, se cargan vectores en los operandos A y B. |
|
--! | | 0: La operación no es combinatoria, se cargan vectores en los operandos A y B. |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! | | Configuración del Datapath, Interconexión del Pipeline Aritmético y Cadena de Carga |
|
--! | | Configuración del Datapath, Interconexión del Pipeline Aritmético y Cadena de Carga |
|
--! | | Dependiendo del valor de estos 3 bits se configura la operación a ejecutar. |
|
--! | | Dependiendo del valor de estos 3 bits se configura la operación a ejecutar. |
|
--! | | |
|
--! | | |
|
--! [3:1] | dcs (rw) | 011: Producto Cruz |
|
--! [3:1] | dcs (rw) | 011: Producto Cruz |
|
--! | | 000: Suma Vectorial |
|
--! | | 000: Suma Vectorial |
|
--! | | 001: Resta Vectorial |
|
--! | | 001: Resta Vectorial |
|
--! | | 110: Normalización Vectorial y cálculo de Magnitud Vectorial |
|
--! | | 110: Normalización Vectorial y cálculo de Magnitud Vectorial |
|
--! | | 100: Producto Punto |
|
--! | | 100: Producto Punto |
|
--! | | 111: Producto Simple |
|
--! | | 111: Producto Simple |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! [5:4] | vtsc (rw) | 00: Solo leer los resultados vectoriales. |
|
--! [5:4] | vtsc (rw) | 00: Solo leer los resultados vectoriales. |
|
--! | | 01: Solo leer los resultados escalares. |
|
--! | | 01: Solo leer los resultados escalares. |
|
--! | | 10: Solo leer los resultados vectoriales. |
|
--! | | 10: Solo leer los resultados vectoriales. |
|
--! | | 11: Leer los resultados escalares y vectoriales. |
|
--! | | 11: Leer los resultados escalares y vectoriales. |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! 6 | dma (rw) | 1: Modo DMA: Los datos que ingresan se leen desde la dirección FETCHSTART (BASE+0x08) y se escriben en |
|
--! 6 | dma (rw) | 1: Modo DMA: Los datos que ingresan se leen desde la dirección FETCHSTART (BASE+0x08) y se escriben en |
|
--! | | la dirección SINKSTART (BASE+0x09). |
|
--! | | la dirección SINKSTART (BASE+0x09). |
|
--! | | 0: Modo Arithmetic Pipeline: Los datos ingresan en grupos de a 6 valores para 2 vectores de 3 valores cada uno,|
|
--! | | 0: Modo Arithmetic Pipeline: Los datos ingresan en grupos de a 6 valores para 2 vectores de 3 valores cada uno,|
|
--! | | cuando se usa en modo uno a uno (cmb=1), ó en grupos de 3 valores para 1 vector de 3 valores, |
|
--! | | cuando se usa en modo uno a uno (cmb=1), ó en grupos de 3 valores para 1 vector de 3 valores, |
|
--! | | pero con el operando A fijado con el valor de la primera carga de valores en modo combinatorio (cmb=1). |
|
--! | | pero con el operando A fijado con el valor de la primera carga de valores en modo combinatorio (cmb=1). |
|
--! | | De la misma manera que en modo DMA se cargan los operandos en la dirección FETCHSTART y se escriben |
|
--! | | De la misma manera que en modo DMA se cargan los operandos en la dirección FETCHSTART y se escriben |
|
--! | | los resultados en la dirección SINKSTART. |
|
--! | | los resultados en la dirección SINKSTART. |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! 7 | flag_fc(r)| 1: Al momento de generar una interrupción este bit se coloca en 1 si se cumplen las condiciones de |
|
--! 7 | flag_fc(r)| 1: Al momento de generar una interrupción este bit se coloca en 1 si se cumplen las condiciones de |
|
--! | | descarga de datos de la memoria (revisar el net signal sflood_condition). Si se encuentra en uno se |
|
--! | | descarga de datos de la memoria (revisar el net signal sflood_condition). Si se encuentra en uno se |
|
--! | | trataría de una inconsistencia puesto que la interrupción se dispara una vez se ha terminado |
|
--! | | trataría de una inconsistencia puesto que la interrupción se dispara una vez se ha terminado |
|
--! | | de ejecutar una instrucción y el que la bandera este en uno significa que hay transacciones de |
|
--! | | de ejecutar una instrucción y el que la bandera este en uno significa que hay transacciones de |
|
--! | | descarga de datos desde la memoria pendientes. |
|
--! | | descarga de datos desde la memoria pendientes. |
|
--! | | |
|
--! | | |
|
--! | | En general que cualquiera de estas banderas se coloque en uno es una señalizacion de error, puesto |
|
--! | | En general que cualquiera de estas banderas se coloque en uno es una señalizacion de error, puesto |
|
--! | | que una vez se ha terminado de ejecutar una instrucción no deben haber transacciones pendientes. |
|
--! | | que una vez se ha terminado de ejecutar una instrucción no deben haber transacciones pendientes. |
|
--! | | La razón de ser de estas banderas es hacer depuración del hardware mas que del software. |
|
--! | | La razón de ser de estas banderas es hacer depuración del hardware mas que del software. |
|
--! | | |
|
--! | | |
|
--! | | 0: Flood Condition off. |
|
--! | | 0: Flood Condition off. |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! 8 | flag_dc(r)| 1: Error, la instrucción ya se ejecutó y hay datos transitando en el buffer de salida aun. |
|
--! 8 | flag_dc(r)| 1: Error, la instrucción ya se ejecutó y hay datos transitando en el buffer de salida aun. |
|
--! | | 0: Drain Condition off. |
|
--! | | 0: Drain Condition off. |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! 9 | wp(r) | 1: Error, la instrucción ya se ejecutó y hay datos transitando en el buffer de salida aun. |
|
--! 9 | wp(r) | 1: Error, la instrucción ya se ejecutó y hay datos transitando en el buffer de salida aun. |
|
--! | | 0: Write on Memory not pending. |
|
--! | | 0: Write on Memory not pending. |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! 10 | pp(r) | 1: Error, la instrucción ya se ejecutón y hay datos transitando el pipeline aritmético. |
|
--! 10 | pp(r) | 1: Error, la instrucción ya se ejecutón y hay datos transitando el pipeline aritmético. |
|
--! | | 0: Pipeline not pending. |
|
--! | | 0: Pipeline not pending. |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! 11 | pl(r) | 1: La carga de parametros no se completó. Esto por lo general pasa cuando uno va a realizar una |
|
--! 11 | pl(r) | 1: La carga de parametros no se completó. Esto por lo general pasa cuando uno va a realizar una |
|
--! | | operaci´n combinatoria y solo cargo el primer operando, el A, esto puede ocurrir porque por ejemplo |
|
--! | | operaci´n combinatoria y solo cargo el primer operando, el A, esto puede ocurrir porque por ejemplo |
|
--! | | se puede desear sumar un conjunto de vectores a un vector de referencia. Este vector de referencia puede |
|
--! | | se puede desear sumar un conjunto de vectores a un vector de referencia. Este vector de referencia puede |
|
--! | | estar en un area de memoria distinta, que el resto de los vectores. Por lo tanto el pseudo codigo para |
|
--! | | estar en un area de memoria distinta, que el resto de los vectores. Por lo tanto el pseudo codigo para |
|
--! | | ejecutar una operación de este tipo seria: |
|
--! | | ejecutar una operación de este tipo seria: |
|
--! | | |
|
--! | | |
|
--! | | ld vect,add,cmb; //Resultados solo vectoriales, ejecutar operación suma en modo combinatorio |
|
--! | | ld vect,add,cmb; //Resultados solo vectoriales, ejecutar operación suma en modo combinatorio |
|
--! | | ld &A; //Cargar la direccion del Vector A. |
|
--! | | ld &A; //Cargar la direccion del Vector A. |
|
--! | | ld 3; //Cargar 3 valores, o sea el Vector A. |
|
--! | | ld 3; //Cargar 3 valores, o sea el Vector A. |
|
--! | | wait int; //Esperar a que se ejecute la interrupcion. Una vez se termine de ejecutar si la bandera|
|
--! | | wait int; //Esperar a que se ejecute la interrupcion. Una vez se termine de ejecutar si la bandera|
|
--! | | //pl está en uno se vuelve a comenzar y se deshecha el dato que hay como |
|
--! | | //pl está en uno se vuelve a comenzar y se deshecha el dato que hay como |
|
--! | | //parámetro. Para este ejemplo se asume que está en uno |
|
--! | | //parámetro. Para este ejemplo se asume que está en uno |
|
--! | | ld &B; //Cargar la dirección donde se encuentran los vectores B |
|
--! | | ld &B; //Cargar la dirección donde se encuentran los vectores B |
|
--! | | ld &C; //Cargar la dirección donde se exribiran los resultados. |
|
--! | | ld &C; //Cargar la dirección donde se exribiran los resultados. |
|
--! | | ld 24; //Cargar los siguientes 24 valores a partir de &B correspondiente a 8 vectores |
|
--! | | ld 24; //Cargar los siguientes 24 valores a partir de &B correspondiente a 8 vectores |
|
--! | | //ejecutando 8 sumas vectoriales que se escribirín a apartir de &C |
|
--! | | //ejecutando 8 sumas vectoriales que se escribirín a apartir de &C |
|
--! | | wait int; //Esperar a que termine la ejecución de las sumas. |
|
--! | | wait int; //Esperar a que termine la ejecución de las sumas. |
|
--! | | |
|
--! | | |
|
--! | | 0: Los operandos se cargaron integros se cargo del todo y no hubo que desechar parametros. |
|
--! | | 0: Los operandos se cargaron integros se cargo del todo y no hubo que desechar parametros. |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! 12 | dp (r) | 1: Error, la instrucción se termino y aun hay datos pendientes por ser descargados |
|
--! 12 | dp (r) | 1: Error, la instrucción se termino y aun hay datos pendientes por ser descargados |
|
--! | | 0: No hay datos pendientes por ser descargados. |
|
--! | | 0: No hay datos pendientes por ser descargados. |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! 13 | ap (r) | 1: Carga de direcciones en la interconexión aún está pendiente y la instrucció ya |
|
--! 13 | ap (r) | 1: Carga de direcciones en la interconexión aún está pendiente y la instrucció ya |
|
--! | | se ejecutó |
|
--! | | se ejecutó |
|
--! | | 0: No hay direcciones pendientes por cargar. |
|
--! | | 0: No hay direcciones pendientes por cargar. |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! 14 | rlsc (rw) | 1: El sistema está configurado para resetear la recarga sincronizada de parámetros una vez |
|
--! 14 | rlsc (rw) | 1: El sistema está configurado para resetear la recarga sincronizada de parámetros una vez |
|
--! | | concluya la instrucción |
|
--! | | concluya la instrucción |
|
--! | | |
|
--! | | |
|
--! | | 0: El sistema está configurado para no resetear la cadena de sincronización de carga. |
|
--! | | 0: El sistema está configurado para no resetear la cadena de sincronización de carga. |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! 15 | rom (r) | 1: Los registros solo se pueden leer no se pueden escribir. Etsado SINK y SOURCE |
|
--! 15 | rom (r) | 1: Los registros solo se pueden leer no se pueden escribir. Etsado SINK y SOURCE |
|
--! | | 0: Los registros se pueden leer y escribir. |
|
--! | | 0: Los registros se pueden leer y escribir. |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! [30:16] | nfetch(rw)| Cantidad de direcciones a cargar en la interconexón para realizar la posterior descarga de datos de la |
|
--! [30:16] | nfetch(rw)| Cantidad de direcciones a cargar en la interconexón para realizar la posterior descarga de datos de la |
|
--! | | memoria al RayTrac.
|
--! | | memoria al RayTrac.
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! 31 | irq | 1: Evento de interrupción. El usuario debe hacer clear de este bit para dar la interrupci&o;n por |
|
--! 31 | irq | 1: Evento de interrupción. El usuario debe hacer clear de este bit para dar la interrupci&o;n por |
|
--! | | por atendida. Este bit se pone en uno cuando el sistema pasa de estado TX a FETCH o FETCH a TX. |
|
--! | | por atendida. Este bit se pone en uno cuando el sistema pasa de estado TX a FETCH o FETCH a TX. |
|
--! | | |
|
--! | | |
|
--! | | 0: El RayTrac se encuentra en operación Normal. |
|
--! | | 0: El RayTrac se encuentra en operación Normal. |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------
|
--! Result Vector Z component (reg_vz) BASE_ADDRESS + 0x4 |
|
--! Result Vector Z component (reg_vz) BASE_ADDRESS + 0x4 |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Result Vector Y component (reg_vy) BASE_ADDRESS + 0x8 |
|
--! Result Vector Y component (reg_vy) BASE_ADDRESS + 0x8 |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Result Vector X component (reg_vx) BASE_ADDRESS + 0xC |
|
--! Result Vector X component (reg_vx) BASE_ADDRESS + 0xC |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Result Vector Scalar component (reg_scalar) BASE_ADDRESS + 0x10 |
|
--! Result Vector Scalar component (reg_scalar) BASE_ADDRESS + 0x10 |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Scratch Vector 00 (reg_nfetch) BASE_ADDRESS + 0x14 |
|
--! Scratch Vector 00 (reg_nfetch) BASE_ADDRESS + 0x14 |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! output Data Counter (reg_outputcounter) BASE_ADDRESS + 0x18 |
|
--! output Data Counter (reg_timercounter) BASE_ADDRESS + 0x18 |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Input Data Counter (reg_inputcounter) BASE_ADDRESS + 0x1C |
|
--! Input Data Counter (reg_inputcounter) BASE_ADDRESS + 0x1C |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Data Fetch Start Address (reg_fetchstart) BASE_ADDRESS + 0x20 |
|
--! Data Fetch Start Address (reg_fetchstart) BASE_ADDRESS + 0x20 |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Data Write Start Address (reg_sinkstart) BASE_ADDRESS + 0x24 |
|
--! Data Write Start Address (reg_sinkstart) BASE_ADDRESS + 0x24 |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Parameter AX component (reg_ax) BASE_ADDRESS + 0x28 |
|
--! Parameter AX component (reg_ax) BASE_ADDRESS + 0x28 |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Parameter Ay component (reg_ay) BASE_ADDRESS + 0x2C |
|
--! Parameter Ay component (reg_ay) BASE_ADDRESS + 0x2C |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Parameter Az component (reg_az) BASE_ADDRESS + 0x30 |
|
--! Parameter Az component (reg_az) BASE_ADDRESS + 0x30 |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Parameter Bx component (reg_bx) BASE_ADDRESS + 0x34 |
|
--! Parameter Bx component (reg_bx) BASE_ADDRESS + 0x34 |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Parameter By component (reg_by) BASE_ADDRESS + 0x38 |
|
--! Parameter By component (reg_by) BASE_ADDRESS + 0x38 |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--! Parameter Bz component (reg_bz) BASE_ADDRESS + 0x3C |
|
--! Parameter Bz component (reg_bz) BASE_ADDRESS + 0x3C |
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
|
|
|
|
|
|
|
|
|
|
|
|
|
end architecture;
|
end architecture;
|
|
|
|
|
