--! @file fastmux.vhd
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--! @file fastmux.vhd
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--! @brief Multiplexor.
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--! @brief Multiplexor.
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--! @author Julián Andrés Guarín Reyes.
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--! @author Julián Andrés Guarín Reyes.
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-- RAYTRAC
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-- RAYTRAC
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-- Author Julian Andres Guarin
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-- Author Julian Andres Guarin
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-- fastmux.vhd
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-- fastmux.vhd
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-- This file is part of raytrac.
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-- This file is part of raytrac.
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--
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--
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-- raytrac is free software: you can redistribute it and/or modify
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-- raytrac is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- raytrac is distributed in the hope that it will be useful,
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-- raytrac is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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--! Libreria de definicion de senales y tipos estandares, comportamiento de operadores aritmeticos y logicos.
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library ieee;
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library ieee;
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--! Paquete de definicion estandard de logica.
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity fastmux is
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entity fastmux is
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generic (
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generic (
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width : integer := 18
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width : integer := 18
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);
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);
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port (
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port (
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a,b:in std_logic_vector(width-1 downto 0);
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a,b:in std_logic_vector(width-1 downto 0);
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s:in std_logic;
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s:in std_logic;
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c: out std_logic_vector(width-1 downto 0)
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c: out std_logic_vector(width-1 downto 0)
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);
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);
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end entity;
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end entity;
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--! @brief Definicion arquitectura del mux
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--! @details El Mux esta descrito de manera estructural, instanciado bit por bit en la salida, multiplexores de un solo bit.
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architecture fastmux_arch of fastmux is
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architecture fastmux_arch of fastmux is
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begin
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begin
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muxgen:
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muxgen:
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for i in 0 to width-1 generate
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for i in 0 to width-1 generate
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c(i) <= (a(i) and not(s)) or (b(i) and s);
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c(i) <= (a(i) and not(s)) or (b(i) and s);
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end generate muxgen;
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end generate muxgen;
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