------------------------------------------------
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------------------------------------------------
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--! @file ema32x2.vhd
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--! @file ema32x2.vhd
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--! @brief RayTrac Floating Point Adder
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--! @brief RayTrac Floating Point Adder
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--! @author Julián Andrés Guarín Reyes
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--! @author Julián Andrés Guarín Reyes
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--------------------------------------------------
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--------------------------------------------------
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-- RAYTRAC (FP BRANCH)
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-- RAYTRAC (FP BRANCH)
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-- Author Julian Andres Guarin
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-- Author Julian Andres Guarin
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-- ema32x2.vhd
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-- ema32x2.vhd
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-- This file is part of raytrac.
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-- This file is part of raytrac.
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--
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--
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-- raytrac is free software: you can redistribute it and/or modify
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-- raytrac is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- raytrac is distributed in the hope that it will be useful,
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-- raytrac is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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--! Esta entidad recibe dos números en formato punto flotante IEEE 754, de precision simple y devuelve las mantissas signadas y corridas, y el exponente correspondiente al resultado antes de normalizarlo al formato float.
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--! Esta entidad recibe dos números en formato punto flotante IEEE 754, de precision simple y devuelve las mantissas signadas y corridas, y el exponente correspondiente al resultado antes de normalizarlo al formato float.
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--!\nLas 2 mantissas y el exponente entran despues a la entidad add2 que suma las mantissas y entrega el resultado en formato IEEE 754.
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--!\nLas 2 mantissas y el exponente entran despues a la entidad add2 que suma las mantissas y entrega el resultado en formato IEEE 754.
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entity ema32x2 is
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entity ema32x2 is
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port (
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port (
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clk,dpc : in std_logic;
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clk,dpc : in std_logic;
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a32,b32 : in std_logic_vector (31 downto 0);
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a32,b32 : in std_logic_vector (31 downto 0);
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res32 : out std_logic_vector(31 downto 0)
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res32 : out std_logic_vector(31 downto 0)
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);
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);
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end ema32x2;
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end ema32x2;
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architecture ema32x2_arch of ema32x2 is
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architecture ema32x2_arch of ema32x2 is
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component shftr
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component shftr
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port (
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port (
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dir : in std_logic;
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dir : in std_logic;
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places : in std_logic_vector (3 downto 0);
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places : in std_logic_vector (3 downto 0);
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data24 : in std_logic_vector (23 downto 0);
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data24 : in std_logic_vector (23 downto 0);
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data40 : out std_logic_vector (39 downto 0)
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data40 : out std_logic_vector (39 downto 0)
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);
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);
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end component;
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end component;
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signal s2slr : std_logic_vector(1 downto 0);
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signal s2slr : std_logic_vector(1 downto 0);
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signal s3lshift,s4lshift : std_logic_vector(4 downto 0);
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signal s3lshift,s4lshift : std_logic_vector(4 downto 0);
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signal s0sdelta,s0udelta,s0udeltaa,s0udeltab,s2exp,s3exp,s4exp : std_logic_vector(7 downto 0);
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signal s0sdelta,s0udelta,s0udeltaa,s0udeltab,s2exp,s3exp,s4exp : std_logic_vector(7 downto 0);
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signal s4slab : std_logic_vector(15 downto 0);
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signal s4slab : std_logic_vector(15 downto 0);
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signal s2slab : std_logic_vector(16 downto 0);
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signal s2slab : std_logic_vector(16 downto 0);
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signal b1s,s4nrmP : std_logic_vector(22 downto 0); -- Inversor de la mantissa
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signal b1s,s4nrmP : std_logic_vector(22 downto 0); -- Inversor de la mantissa
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signal s0a,s0b,s1a,s1b : std_logic_vector(31 downto 0); -- Float 32 bit
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signal s0a,s0b,s1a,s1b : std_logic_vector(31 downto 0); -- Float 32 bit
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signal s1sma,s2sma,s2smb,s3sma,s3smb,s3ures,s4ures : std_logic_vector(24 downto 0); -- Signed mantissas
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signal s1sma,s2sma,s2smb,s3sma,s3smb,s3ures,s4ures : std_logic_vector(24 downto 0); -- Signed mantissas
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signal s3res : std_logic_vector(25 downto 0); -- Signed mantissa result
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signal s3res : std_logic_vector(25 downto 0); -- Signed mantissa result
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signal s1pS,s1pH,s1pL,s4nrmL,s4nrmH,s4nrmS : std_logic_vector(17 downto 0); -- Shifert Product
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signal s1pS,s1pH,s1pL,s4nrmL,s4nrmH,s4nrmS : std_logic_vector(17 downto 0); -- Shifert Product
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signal s0zeroa,s0zerob,s1zeroa,s1zerob,s1z,s4sgr : std_logic;
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signal s0zeroa,s0zerob,s1zeroa,s1zerob,s1z,s4sgr : std_logic;
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signal s2sma,s2smb : std_logic_vector (56 downto 0);
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signal s2sma,s2smb : std_logic_vector (56 downto 0);
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begin
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begin
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process (clk)
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process (clk)
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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--!Registro de entrada
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--!Registro de entrada
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s0a <= a32;
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s0a <= a32;
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s0b(31) <= dpc xor b32(31); --! Importante: Integrar el signo en el operando B
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s0b(31) <= dpc xor b32(31); --! Importante: Integrar el signo en el operando B
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s0b(30 downto 0) <= b32(30 downto 0);
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s0b(30 downto 0) <= b32(30 downto 0);
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s0b(22 downto 0) <= b32(22 downto 0);
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s0b(22 downto 0) <= b32(22 downto 0);
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--!Etapa 0,Calcular la manera en que se llevara a cabo la desnormalizacion
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--!Etapa 0,Calcular la manera en que se llevara a cabo la desnormalizacion
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s1signa <= s0a(31);
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s1signa <= s0a(31);
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s1signb <= s0b(31);
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s1signb <= s0b(31);
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s1dira <= s0sdelta(7);
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s1dira <= s0sdelta(7);
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s1uma <= s0a(22 downto 0);
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s1uma <= s0a(22 downto 0);
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s1umb <= s0b(22 downto 0);
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s1umb <= s0b(22 downto 0);
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if sa(30 downto 23) = "00000000" or sb(30 downto 23) = "00000000" then
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if sa(30 downto 23) = "00000000" or sb(30 downto 23) = "00000000" then
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s1expb <= s0b(30 downto 23) or s0a(30 downto 23);
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s1expb <= s0b(30 downto 23) or s0a(30 downto 23);
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s1udeltaa <= "0000";
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s1udeltaa <= "0000";
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s1udeltab <= "0000";
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s1udeltab <= "0000";
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s1zero <= '1';
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s1zero <= '1';
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else
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else
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s1expb <= s0b(30 downto 23);
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s1expb <= s0b(30 downto 23);
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s1udeltaa <= s0udeltaa(3 downto 0);
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s1udeltaa <= s0udeltaa(3 downto 0);
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s1udeltab <= s1udeltab(3 downto 0);
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s1udeltab <= s1udeltab(3 downto 0);
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s1zero <= '0';
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s1zero <= '0';
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end if;
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end if;
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--! Etapa 1: Denormalización de las mantissas.
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--! Etapa 1: Denormalización de las mantissas.
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--! A
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--! A
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s2exp <= s1a(30 downto 23);
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s2exp <= s1a(30 downto 23);
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s2sma <= s1sma;
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s2sma <= s1sma;
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--! B
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--! B
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for i in 23 downto 15 loop
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for i in 23 downto 15 loop
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s2smb(i) <= s1pL(23-i) xor s1b(31);
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s2smb(i) <= s1pL(23-i) xor s1b(31);
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end loop;
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end loop;
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for i in 14 downto 6 loop
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for i in 14 downto 6 loop
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s2smb(i) <= (s1pH(14-i) or s1pL(14-i+9)) xor s1b(31);
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s2smb(i) <= (s1pH(14-i) or s1pL(14-i+9)) xor s1b(31);
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end loop;
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end loop;
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for i in 5 downto 0 loop
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for i in 5 downto 0 loop
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s2smb(i) <= (s1pS(5-i) or s1pH(5-i+9)) xor s1b(31);
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s2smb(i) <= (s1pS(5-i) or s1pH(5-i+9)) xor s1b(31);
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end loop;
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end loop;
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if s1b(30 downto 28)>"000" then
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if s1b(30 downto 28)>"000" then
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s2slr <= "11";
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s2slr <= "11";
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else
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else
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s2slr <= s1b(27 downto 26);
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s2slr <= s1b(27 downto 26);
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end if;
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end if;
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s2smb(24) <= s1b(31);
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s2smb(24) <= s1b(31);
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--! Etapa2: Finalizar la denormalización de b.
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--! Etapa2: Finalizar la denormalización de b.
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--! A
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--! A
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s3sma <= s2sma;
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s3sma <= s2sma;
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s3exp <= s2exp;
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s3exp <= s2exp;
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--! B
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--! B
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case (s2slr) is
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case (s2slr) is
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when "00" =>
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when "00" =>
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s3smb <= s2smb(24 downto 0)+s2smb(24);
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s3smb <= s2smb(24 downto 0)+s2smb(24);
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when "01" =>
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when "01" =>
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s3smb <= ( s2slab(8 downto 0) & s2smb(23 downto 8) ) + s2smb(24);
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s3smb <= ( s2slab(8 downto 0) & s2smb(23 downto 8) ) + s2smb(24);
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when "10" =>
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when "10" =>
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s3smb <= ( s2slab(16 downto 0) & s2smb(23 downto 16)) + s2smb(24);
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s3smb <= ( s2slab(16 downto 0) & s2smb(23 downto 16)) + s2smb(24);
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when others =>
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when others =>
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s3smb <= (others => '0');
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s3smb <= (others => '0');
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end case;
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end case;
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--! Etapa 3: Etapa 3 Realizar la suma, quitar el signo de la mantissa y codificar el corrimiento hacia la izquierda.
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--! Etapa 3: Etapa 3 Realizar la suma, quitar el signo de la mantissa y codificar el corrimiento hacia la izquierda.
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s4ures <= s3ures+s3res(25); --Resultado no signado
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s4ures <= s3ures+s3res(25); --Resultado no signado
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s4sgr <= s3res(25); --Signo
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s4sgr <= s3res(25); --Signo
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s4exp <= s3exp; --Exponente
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s4exp <= s3exp; --Exponente
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s4lshift <= s3lshift; --Corrimiento hacia la izquierda.
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s4lshift <= s3lshift; --Corrimiento hacia la izquierda.
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--! Etapa 4: Corrimiento y normalización de la mantissa resultado.
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--! Etapa 4: Corrimiento y normalización de la mantissa resultado.
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res32(31) <= s4sgr;
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res32(31) <= s4sgr;
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if s4ures(24)='1' then
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if s4ures(24)='1' then
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res32(22 downto 0) <= s4ures(23 downto 1);
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res32(22 downto 0) <= s4ures(23 downto 1);
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res32(30 downto 23) <= s4exp+1;
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res32(30 downto 23) <= s4exp+1;
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else
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else
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case s4lshift(4 downto 3) is
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case s4lshift(4 downto 3) is
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when "00" =>
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when "00" =>
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res32(22 downto 0) <= s4nrmP(22 downto 0);
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res32(22 downto 0) <= s4nrmP(22 downto 0);
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res32(30 downto 23) <= s4exp - s4lshift;
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res32(30 downto 23) <= s4exp - s4lshift;
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when "01" =>
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when "01" =>
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res32(22 downto 0) <= s4nrmP(14 downto 0) & s4slab(7 downto 0);
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res32(22 downto 0) <= s4nrmP(14 downto 0) & s4slab(7 downto 0);
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res32(30 downto 23) <= s4exp - s4lshift;
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res32(30 downto 23) <= s4exp - s4lshift;
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when "10" =>
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when "10" =>
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res32(22 downto 0) <= s4nrmP(6 downto 0) & s4slab(15 downto 0);
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res32(22 downto 0) <= s4nrmP(6 downto 0) & s4slab(15 downto 0);
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res32(30 downto 23) <= s4exp - s4lshift;
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res32(30 downto 23) <= s4exp - s4lshift;
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when others =>
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when others =>
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res32(30 downto 0) <= (others => '0');
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res32(30 downto 0) <= (others => '0');
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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--! Combinatorial gremlin, Etapa 0, Calcular la manera en que se llevara a cabo la desnormalizacion.
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--! Combinatorial gremlin, Etapa 0, Calcular la manera en que se llevara a cabo la desnormalizacion.
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process (s0b(30 downto 23),s0a(30 downto 23))
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process (s0b(30 downto 23),s0a(30 downto 23))
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begin
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begin
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--! Diferencia signada entre el valor del exponente a y el exponente b
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--! Diferencia signada entre el valor del exponente a y el exponente b
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s0sdelta <= s0a(30 downto 23) - s0b(30 downto 23);
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s0sdelta <= s0a(30 downto 23) - s0b(30 downto 23);
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--! Manejo de cero
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--! Manejo de cero
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if sa(30 downto 23) = "00000000" then
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if sa(30 downto 23) = "00000000" then
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s0zeroa <= '0';
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s0zeroa <= '0';
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else
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else
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s0zeroa <= '1';
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s0zeroa <= '1';
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end if;
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end if;
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if sb(30 downto 23) = "00000000" then
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if sb(30 downto 23) = "00000000" then
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s0zerob <= '0';
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s0zerob <= '0';
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else
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else
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s0zerob <= '1';
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s0zerob <= '1';
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end if;
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end if;
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end process;
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end process;
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process (s0sdelta)
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process (s0sdelta)
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begin
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begin
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--! Esta parte define en que rango de la grafica de normalizacón se movera la normalizaci—n del resultado de la mantissa
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--! Esta parte define en que rango de la grafica de normalizacón se movera la normalizaci—n del resultado de la mantissa
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case s0sdelta(7 downto 1) is
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case s0sdelta(7 downto 1) is
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when "0000000" =>
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when "0000000" =>
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s0nrmshftype <= '0';
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s0nrmshftype <= '0';
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when "1111111" =>
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when "1111111" =>
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s0nrmshftype <= not(s0sdelta(0));
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s0nrmshftype <= not(s0sdelta(0));
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when others =>
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when others =>
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s0nrmshftype <= '1';
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s0nrmshftype <= '1';
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end case;
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end case;
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--! Valor absoluto de la diferencia entre el exponente a y el b
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--! Valor absoluto de la diferencia entre el exponente a y el b
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for i in 7 downto 0 loop
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for i in 7 downto 0 loop
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s0udelta(i) <= s0sdelta(7) xor s0sdelta(i);
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s0udelta(i) <= s0sdelta(7) xor s0sdelta(i);
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end loop;
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end loop;
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end process
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end process
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process (s0udelta,s0sdelta(7))
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process (s0udelta,s0sdelta(7))
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begin
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begin
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s0udeltaa <= (s0udelta(7)&s0udelta(7 downto 1))+("0000000"&s0sdelta(7));
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s0udeltaa <= (s0udelta(7)&s0udelta(7 downto 1))+("0000000"&s0sdelta(7));
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s0udeltab <= (s0udelta(7)&s0udelta(7 downto 1))+("0000000"&s0udelta(0));
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s0udeltab <= (s0udelta(7)&s0udelta(7 downto 1))+("0000000"&s0udelta(0));
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end process;
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end process;
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--! Combinatorial Gremlin, Etapa 1 Denormalización de las mantissas.
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--! Combinatorial Gremlin, Etapa 1 Denormalización de las mantissas.
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shftra:shftr
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shftra:shftr
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port map (s1dira,s1udeltaa(3 downto 0),'1'&s1uma,s1data40a);
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port map (s1dira,s1udeltaa(3 downto 0),'1'&s1uma,s1data40a);
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shftrb:shftr
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shftrb:shftr
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port map (not(s1dira),s1udeltab(3 downto 0),'1'&s1umb,s1data40b);
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port map (not(s1dira),s1udeltab(3 downto 0),'1'&s1umb,s1data40b);
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|
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process (s1data40b,s1data40a)
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process (s1data40b,s1data40a)
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begin
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begin
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|
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if s1dira='1' then
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if s1dira='1' then
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s1signeddata56a(55 downto 40) <= (others => '0');
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s1signeddata56a(55 downto 40) <= (others => '0');
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s1signeddata56b(15 downto 0) <= (others => '0');
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s1signeddata56b(15 downto 0) <= (others => '0');
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for i in 39 downto 0 loop
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for i in 39 downto 0 loop
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s1signeddata56a(i) <= s1signa xor s1data40a(i);
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s1signeddata56a(i) <= s1signa xor s1data40a(i);
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s1signeddata56b(i+16) <= s1signb xor s1data40b(i);
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s1signeddata56b(i+16) <= s1signb xor s1data40b(i);
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end loop;
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end loop;
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else
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else
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s1signeddata56a(15 downto 0) <= (others => '0');
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s1signeddata56a(15 downto 0) <= (others => '0');
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s1signeddata56b(55 downto 40) <= (others => '0');
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s1signeddata56b(55 downto 40) <= (others => '0');
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for i in 39 downto 0 loop
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for i in 39 downto 0 loop
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s1signeddata56a(i+16) <= s1signa xor s1data40a(i);
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s1signeddata56a(i+16) <= s1signa xor s1data40a(i);
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s1signeddata56b(i) <= s1signb xor s1data40b(i);
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s1signeddata56b(i) <= s1signb xor s1data40b(i);
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end loop;
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end loop;
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end if;
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end if;
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|
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end process;
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end process;
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|
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|
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s1b2b1s:
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s1b2b1s:
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for i in 22 downto 0 generate
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for i in 22 downto 0 generate
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b1s(i) <= s1b(22-i);
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b1s(i) <= s1b(22-i);
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end generate s1b2b1s;
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end generate s1b2b1s;
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signa:
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signa:
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for i in 22 downto 0 generate
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for i in 22 downto 0 generate
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s1sma(i) <= s1a(31) xor s1a(i);
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s1sma(i) <= s1a(31) xor s1a(i);
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end generate;
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end generate;
|
s1sma(23) <= not(s1a(31));
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s1sma(23) <= not(s1a(31));
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s1sma(24) <= s1a(31);
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s1sma(24) <= s1a(31);
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|
|
|
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--! Combinatorial Gremlin, Etapa2: Finalizar la denormalización de b.
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--! Combinatorial Gremlin, Etapa2: Finalizar la denormalización de b.
|
s2signslab:
|
s2signslab:
|
for i in 16 downto 0 generate
|
for i in 16 downto 0 generate
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s2slab(i) <= s2smb(24);
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s2slab(i) <= s2smb(24);
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end generate s2signslab;
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end generate s2signslab;
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--! Combinatorial Gremlin, Etapa 3 Realizar la suma, quitar el signo de la mantissa y codificar el corrimiento hacia la izquierda.
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--! Combinatorial Gremlin, Etapa 3 Realizar la suma, quitar el signo de la mantissa y codificar el corrimiento hacia la izquierda.
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--adder:sadd2
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--adder:sadd2
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--port map (s3sma(24)&s3sma,s3smb(24)&s3smb,dpc,s3res);
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--port map (s3sma(24)&s3sma,s3smb(24)&s3smb,dpc,s3res);
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process (s3sma,s3smb)
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process (s3sma,s3smb)
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begin
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begin
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--! Magia: La suma ocurre aqui
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--! Magia: La suma ocurre aqui
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s3res <= (s3sma(24)&s3sma)+(s3smb(24)&s3smb);
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s3res <= (s3sma(24)&s3sma)+(s3smb(24)&s3smb);
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end process;
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end process;
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process(s3res)
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process(s3res)
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variable lshift : integer range 24 downto 0;
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variable lshift : integer range 24 downto 0;
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begin
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begin
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lshift:=24;
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lshift:=24;
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|
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for i in 0 to 23 loop
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for i in 0 to 23 loop
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s3ures(i) <= s3res(25) xor s3res(i);
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s3ures(i) <= s3res(25) xor s3res(i);
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if (s3res(25) xor s3res(i))='1' then
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if (s3res(25) xor s3res(i))='1' then
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lshift:=23-i;
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lshift:=23-i;
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end if;
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end if;
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end loop;
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end loop;
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s3ures(24) <= s3res(24) xor s3res(25);
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s3ures(24) <= s3res(24) xor s3res(25);
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s3lshift <= conv_std_logic_vector(lshift,5);
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s3lshift <= conv_std_logic_vector(lshift,5);
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end process;
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end process;
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--! Combinatorial Gremlin, Etapa 4 corrimientos y normalización de la mantissa resultado.
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--! Combinatorial Gremlin, Etapa 4 corrimientos y normalización de la mantissa resultado.
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normsupershiftermult:lpm_mult
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normsupershiftermult:lpm_mult
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",9,9,18)
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",9,9,18)
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port map (shl(conv_std_logic_vector(1,9),s4lshift(2 downto 0)),s4ures(22 downto 14),s4nrmS);
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port map (shl(conv_std_logic_vector(1,9),s4lshift(2 downto 0)),s4ures(22 downto 14),s4nrmS);
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normhighshiftermult:lpm_mult
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normhighshiftermult:lpm_mult
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",9,9,18)
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",9,9,18)
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port map (shl(conv_std_logic_vector(1,9),s4lshift(2 downto 0)),s4ures(13 downto 5),s4nrmH);
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port map (shl(conv_std_logic_vector(1,9),s4lshift(2 downto 0)),s4ures(13 downto 5),s4nrmH);
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normlowshiftermult:lpm_mult
|
normlowshiftermult:lpm_mult
|
generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",9,9,18)
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",9,9,18)
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port map (shl(conv_std_logic_vector(1,9),s4lshift(2 downto 0)),s4ures(4 downto 0)&conv_std_logic_vector(0,4),s4nrmL);
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port map (shl(conv_std_logic_vector(1,9),s4lshift(2 downto 0)),s4ures(4 downto 0)&conv_std_logic_vector(0,4),s4nrmL);
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process (s4nrmS,s4nrmH,s4nrmL)
|
process (s4nrmS,s4nrmH,s4nrmL)
|
begin
|
begin
|
s4nrmP(22 downto 14) <= s4nrmS(8 downto 0) or s4nrmH(17 downto 9);
|
s4nrmP(22 downto 14) <= s4nrmS(8 downto 0) or s4nrmH(17 downto 9);
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s4nrmP(13 downto 5) <= s4nrmH(8 downto 0) or s4nrmL(17 downto 9);
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s4nrmP(13 downto 5) <= s4nrmH(8 downto 0) or s4nrmL(17 downto 9);
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s4nrmP(4 downto 0) <= s4nrmL(8 downto 4);
|
s4nrmP(4 downto 0) <= s4nrmL(8 downto 4);
|
end process;
|
end process;
|
s4signslab:
|
s4signslab:
|
for i in 15 downto 0 generate
|
for i in 15 downto 0 generate
|
s4slab(i) <= '0';
|
s4slab(i) <= '0';
|
end generate s4signslab;
|
end generate s4signslab;
|
end ema32x2_arch;
|
end ema32x2_arch;
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