library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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package arithpack is
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package arithpack is
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constant rstMasterValue : std_logic := '0';
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constant rstMasterValue : std_logic := '0';
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component uf
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component uf
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port (
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port (
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opcode : in std_logic;
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opcode : in std_logic;
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mxfx : in std_logic_vector(12*18-1 downto 0);
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m0f0,m0f1,m1f0m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : in std_logic_vector(17 downto 0);
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cpx,cpy,cpz,dp0,dp1 : out std_logic_vector(31 downto 0)
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cpx,cpy,cpz,dp0,dp1 : out std_logic_vector(31 downto 0)
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clk,rst : in std_logic
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clk,rst : in std_logic
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);
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);
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end component;
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end component;
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component opcoder
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component opcoder
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port (
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port (
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Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz : in std_logic_vector (17 downto 0);
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Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz : in std_logic_vector (17 downto 0);
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m0f0,m0f1,m1f0m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : out std_logic_vector (17 downto 0);
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m0f0,m0f1,m1f0m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : out std_logic_vector (17 downto 0);
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opcode,addcode : in std_logic
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opcode,addcode : in std_logic
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);
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);
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end component;
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end component;
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component r_a18_b18_smul_c32_r
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component r_a18_b18_smul_c32_r
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port (
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port (
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aclr,clock:in std_logic;
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aclr,clock:in std_logic;
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dataa,datab:in std_logic_vector (17 downto 0);
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dataa,datab:in std_logic_vector (17 downto 0);
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result: out std_logic_vector(31 downto 0)
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result: out std_logic_vector(31 downto 0)
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);
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);
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end component;
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end component;
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component cla_logic_block
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component cla_logic_block
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generic ( w: integer:=4);
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generic ( w: integer:=4);
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port (
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port (
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p,g:in std_logic_vector(w-1 downto 0);
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p,g:in std_logic_vector(w-1 downto 0);
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cin:in std_logic;
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cin:in std_logic;
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c:out std_logic_vector(w downto 1)
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c:out std_logic_vector(w downto 1)
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);
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);
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end component;
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end component;
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component rca_logic_block
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component rca_logic_block
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generic ( w : integer := 4);
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generic ( w : integer := 4);
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port (
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port (
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p,g: in std_logic_vector(w-1 downto 0);
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p,g: in std_logic_vector(w-1 downto 0);
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cin: in std_logic;
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cin: in std_logic;
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c: out std_logic_vector(w downto 1)
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c: out std_logic_vector(w downto 1)
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);
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);
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end component;
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end component;
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component adder
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component adder
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generic (
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generic (
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w : integer := 4;
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w : integer := 4;
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carry_logic := "CLA";
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carry_logic := "CLA";
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substractor_selector := "YES";
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substractor_selector := "YES";
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);
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);
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port (
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port (
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a,b : in std_logic_vector (w-1 downto 0);
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a,b : in std_logic_vector (w-1 downto 0);
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s,ci : in std_logic;
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s,ci : in std_logic;
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result : out std_logic_vector (w-1 downto 0);
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result : out std_logic_vector (w-1 downto 0);
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cout : out std_logic
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cout : out std_logic
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);
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);
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end component;
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end component;
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end package;
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end package;
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