--! @file raytrac.vhd
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--! @file raytrac.vhd
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--! @brief Descripción del sistema aritmetico usado por raytrac.
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--! @brief Descripción del sistema aritmetico usado por raytrac.
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--! @author Julián Andrés Guarín Reyes.
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--! @author Julián Andrés Guarín Reyes.
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-- RAYTRAC
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-- RAYTRAC
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-- Author Julian Andres Guarin
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-- Author Julian Andres Guarin
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-- uf.vhd
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-- uf.vhd
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-- This file is part of raytrac.
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-- This file is part of raytrac.
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--
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--
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-- raytrac is free software: you can redistribute it and/or modify
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-- raytrac is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- raytrac is distributed in the hope that it will be useful,
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-- raytrac is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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--! Libreria de definicion de senales y tipos estandares, comportamiento de operadores aritmeticos y logicos.\n Signal and types definition library. This library also defines
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--! Libreria de definicion de senales y tipos estandares, comportamiento de operadores aritmeticos y logicos.\n Signal and types definition library. This library also defines
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library ieee;
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library ieee;
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--! Paquete de definicion estandard de logica. Standard logic definition pack.
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--! Paquete de definicion estandard de logica. Standard logic definition pack.
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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|
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--! Paquete para el manejo de aritmŽtica con signo sobre el tipo std_logic_vector
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--! Paquete para el manejo de aritmŽtica con signo sobre el tipo std_logic_vector
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use ieee.std_logic_signed.all;
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use ieee.std_logic_signed.all;
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|
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--! Se usaran en esta descripcion los componentes del package arithpack.vhd.\n It will be used in this description the components on the arithpack.vhd package.
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--! Se usaran en esta descripcion los componentes del package arithpack.vhd.\n It will be used in this description the components on the arithpack.vhd package.
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use work.arithpack.all;
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use work.arithpack.all;
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--! uf es la descripción del circuito que realiza la aritmética del Rt Engine.
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--! uf es la descripción del circuito que realiza la aritmética del Rt Engine.
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|
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--! La entrada opcode indica la operación que se está realizando, en los sumadores, es la misma señal que se encuentra en la entidad opcoder, que selecciona si se está realizando un producto punto o un producto cruz. Dentro de la arquitectura de uf, la señal opcode selecciona en la primera etapa de sumadores, si la operación a realizar será una resta o una suma.
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--! La entrada opcode indica la operación que se está realizando, en los sumadores, es la misma señal que se encuentra en la entidad opcoder, que selecciona si se está realizando un producto punto o un producto cruz. Dentro de la arquitectura de uf, la señal opcode selecciona en la primera etapa de sumadores, si la operación a realizar será una resta o una suma.
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--! Los resultados estarán en distintas salidas dependiendo de la operación, lo cual es apenas natural: El producto cruz tiene por resultado un vector, mientras que el producto punto tiene por resultado un escalar.
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--! Los resultados estarán en distintas salidas dependiendo de la operación, lo cual es apenas natural: El producto cruz tiene por resultado un vector, mientras que el producto punto tiene por resultado un escalar.
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--! Esta entidad utiliza las señales de control clk y rst.}
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--! Esta entidad utiliza las señales de control clk y rst.}
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--! \n\n
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--! \n\n
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--! La característica fundamental de uf, es que puede realizar 2 operaciones de producto punto al mimso tiempo ó una operación de producto cruz al mismo tiempo. La otra característica importante es que el pipe de producto punto es mas largo que el pipe de producto cruz: el producto punto tomará 3 clocks para realizarse, mientras que el procto punto tomara 4 clocks para realizarse.
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--! La característica fundamental de uf, es que puede realizar 2 operaciones de producto punto al mimso tiempo ó una operación de producto cruz al mismo tiempo. La otra característica importante es que el pipe de producto punto es mas largo que el pipe de producto cruz: el producto punto tomará 3 clocks para realizarse, mientras que el procto punto tomara 4 clocks para realizarse.
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entity uf is
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entity uf is
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generic (
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generic (
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use_std_logic_signed : string := "NO"
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use_std_logic_signed : string := "NO";
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carry_logic : string := "CLA"
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);
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);
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port (
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port (
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opcode : in std_logic; --! Entrada que dentro de la arquitectura funciona como selector de la operación que se lleva a cabo en la primera etapa de sumadores/restadores.
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opcode : in std_logic; --! Entrada que dentro de la arquitectura funciona como selector de la operación que se lleva a cabo en la primera etapa de sumadores/restadores.
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m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : in std_logic_vector(17 downto 0); --! Entradas que van conectadas a los multiplicadores en la primera etapa de la descripción.
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m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : in std_logic_vector(17 downto 0); --! Entradas que van conectadas a los multiplicadores en la primera etapa de la descripción.
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cpx,cpy,cpz,dp0,dp1 : out std_logic_vector(31 downto 0); --! Salidas donde se registran los resultados de las operaciones aritméticas: cpx,cpy,cpz serán los componentes del vector que da por resultado el producto cruz entre los vectores AxB ó CxD.
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cpx,cpy,cpz,dp0,dp1 : out std_logic_vector(31 downto 0); --! Salidas donde se registran los resultados de las operaciones aritméticas: cpx,cpy,cpz serán los componentes del vector que da por resultado el producto cruz entre los vectores AxB ó CxD.
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clk,rst : in std_logic --! Las entradas de control usuales.
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clk,rst : in std_logic --! Las entradas de control usuales.
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);
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);
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end uf;
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end uf;
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architecture uf_arch of uf is
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architecture uf_arch of uf is
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|
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-- Stage 0 signals
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-- Stage 0 signals
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signal stage0mf00,stage0mf01,stage0mf10,stage0mf11,stage0mf20,stage0mf21,stage0mf30,stage0mf31,stage0mf40,stage0mf41,stage0mf50,stage0mf51 : std_logic_vector(17 downto 0); --! Señales que conectan los operandos seleccionados en opcode a las entradas de los multiplicadores.
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signal stage0mf00,stage0mf01,stage0mf10,stage0mf11,stage0mf20,stage0mf21,stage0mf30,stage0mf31,stage0mf40,stage0mf41,stage0mf50,stage0mf51 : std_logic_vector(17 downto 0); --! Señales que conectan los operandos seleccionados en opcode a las entradas de los multiplicadores.
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signal stage0p0,stage0p1, stage0p2, stage0p3, stage0p4, stage0p5 : std_logic_vector(31 downto 0); --! Señales / buses, con los productos de los multiplicadores.
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signal stage0p0,stage0p1, stage0p2, stage0p3, stage0p4, stage0p5 : std_logic_vector(31 downto 0); --! Señales / buses, con los productos de los multiplicadores.
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signal stageMopcode : std_logic; --! Señal de atraso del opcode. Revisar el diagrama de bloques para mayor claridad.
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signal stageMopcode : std_logic; --! Señal de atraso del opcode. Revisar el diagrama de bloques para mayor claridad.
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--Stage 1 signals
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--Stage 1 signals
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signal stage1p0, stage1p1, stage1p2, stage1p3, stage1p4, stage1p5 : std_logic_vector (31 downto 0); --! Señales provenientes de los productos de la etapa previa de multiplicadores.
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signal stage1p0, stage1p1, stage1p2, stage1p3, stage1p4, stage1p5 : std_logic_vector (31 downto 0); --! Señales provenientes de los productos de la etapa previa de multiplicadores.
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signal stage1a0, stage1a1, stage1a2 : std_logic_vector (31 downto 0); --! Señales / buses, con los resultados de los sumadores.
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signal stage1a0, stage1a1, stage1a2 : std_logic_vector (31 downto 0); --! Señales / buses, con los resultados de los sumadores.
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signal stageSRopcode : std_logic; --! Señal proveniente del opcode que selecciona si los sumadores deben ejecutar una resta o una suma dependiendo de la operación que se ejecute en ese momento del pipe.
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signal stageSRopcode : std_logic; --! Señal proveniente del opcode que selecciona si los sumadores deben ejecutar una resta o una suma dependiendo de la operación que se ejecute en ese momento del pipe.
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-- Some support signals
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-- Some support signals
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signal stage1_internalCarry : std_logic_vector(2 downto 0); --! Cada uno de los 3 sumadores de la etapa de sumadores está compuesto de una cascada de 2 sumadores Carry Look Ahead: aXhigh y aXlow. El carry out del componente low y el carry in del componente high, se conectará a través de las señales internal carry.
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signal stage1_internalCarry : std_logic_vector(2 downto 0); --! Cada uno de los 3 sumadores de la etapa de sumadores está compuesto de una cascada de 2 sumadores Carry Look Ahead: aXhigh y aXlow. El carry out del componente low y el carry in del componente high, se conectará a través de las señales internal carry.
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signal stage2_internalCarry : std_logic_vector(1 downto 0); --! Cada uno de los 2 sumadores de la última etapa de sumadores está compuesto de una cascada de 2 sumadores Carry Look AheadÑ: aXhigh y aXlow. El carry out del componente low y el carry in del componente high, se conectará a través de las señales internal carry.
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signal stage2_internalCarry : std_logic_vector(1 downto 0); --! Cada uno de los 2 sumadores de la última etapa de sumadores está compuesto de una cascada de 2 sumadores Carry Look AheadÑ: aXhigh y aXlow. El carry out del componente low y el carry in del componente high, se conectará a través de las señales internal carry.
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--Stage 2 signals
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--Stage 2 signals
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signal stage2a0, stage2a2, stage2a3, stage2a4, stage2p2, stage2p3 : std_logic_vector (31 downto 0); --! Estas señales corresponden a los sumandos derivados de la primera etapa de multiplicadores (stage2p2, stage2p3) y a los sumandos derivados del resultado de las sumas en la primera etapa de sumadores.
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signal stage2a0, stage2a2, stage2a3, stage2a4, stage2p2, stage2p3 : std_logic_vector (31 downto 0); --! Estas señales corresponden a los sumandos derivados de la primera etapa de multiplicadores (stage2p2, stage2p3) y a los sumandos derivados del resultado de las sumas en la primera etapa de sumadores.
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begin
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begin
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-- Multiplicator Instantiation (StAgE 0)
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-- Multiplicator Instantiation (StAgE 0)
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--! Multiplicador 0
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--! Multiplicador 0
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m0 : r_a18_b18_smul_c32_r
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m0 : r_a18_b18_smul_c32_r
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port map (
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port map (
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aclr => rst,
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aclr => rst,
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clock => clk,
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clock => clk,
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dataa => stage0mf00,
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dataa => stage0mf00,
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datab => stage0mf01,
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datab => stage0mf01,
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result => stage0p0
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result => stage0p0
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);
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);
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--! Multiplicador 1
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--! Multiplicador 1
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m1 : r_a18_b18_smul_c32_r
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m1 : r_a18_b18_smul_c32_r
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port map (
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port map (
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aclr => rst,
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aclr => rst,
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clock => clk,
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clock => clk,
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dataa => stage0mf10,
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dataa => stage0mf10,
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datab => stage0mf11,
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datab => stage0mf11,
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result => stage0p1
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result => stage0p1
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);
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);
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--! Multiplicador 2
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--! Multiplicador 2
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m2 : r_a18_b18_smul_c32_r
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m2 : r_a18_b18_smul_c32_r
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port map (
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port map (
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aclr => rst,
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aclr => rst,
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clock => clk,
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clock => clk,
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dataa => stage0mf20,
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dataa => stage0mf20,
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datab => stage0mf21,
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datab => stage0mf21,
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result => stage0p2
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result => stage0p2
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);
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);
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--! Multiplicador 3
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--! Multiplicador 3
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m3 : r_a18_b18_smul_c32_r
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m3 : r_a18_b18_smul_c32_r
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port map (
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port map (
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aclr => rst,
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aclr => rst,
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clock => clk,
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clock => clk,
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dataa => stage0mf30,
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dataa => stage0mf30,
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datab => stage0mf31,
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datab => stage0mf31,
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result => stage0p3
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result => stage0p3
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);
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);
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--! Multiplicador 4
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--! Multiplicador 4
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m4 : r_a18_b18_smul_c32_r
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m4 : r_a18_b18_smul_c32_r
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port map (
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port map (
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aclr => rst,
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aclr => rst,
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clock => clk,
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clock => clk,
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dataa => stage0mf40,
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dataa => stage0mf40,
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datab => stage0mf41,
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datab => stage0mf41,
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result => stage0p4
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result => stage0p4
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);
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);
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--! Multiplicador 5
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--! Multiplicador 5
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m5 : r_a18_b18_smul_c32_r
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m5 : r_a18_b18_smul_c32_r
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port map (
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port map (
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aclr => rst,
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aclr => rst,
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clock => clk,
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clock => clk,
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dataa => stage0mf50,
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dataa => stage0mf50,
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datab => stage0mf51,
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datab => stage0mf51,
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result => stage0p5
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result => stage0p5
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);
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);
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useIeee:
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useIeee:
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if use_std_logic_signed="YES" generate
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if use_std_logic_signed="YES" generate
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-- Adder Instantiation (sTaGe 1)
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-- Adder Instantiation (sTaGe 1)
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stage1adderProc:
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stage1adderProc:
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process (stage1p0,stage1p1,stage1p2,stage1p3,stage1p4,stage1p5,stageSRopcode)
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process (stage1p0,stage1p1,stage1p2,stage1p3,stage1p4,stage1p5,stageSRopcode)
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begin
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begin
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case (stageSRopcode) is
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case (stageSRopcode) is
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when '1' => -- Cross Product
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when '1' => -- Cross Product
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stage1a0 <= stage1p0-stage1p1;
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stage1a0 <= stage1p0-stage1p1;
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stage1a2 <= stage1p4-stage1p5;
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stage1a2 <= stage1p4-stage1p5;
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when others => -- Dot Product
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when others => -- Dot Product
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stage1a0 <= stage1p0+stage1p1;
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stage1a0 <= stage1p0+stage1p1;
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stage1a2 <= stage1p4+stage1p5;
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stage1a2 <= stage1p4+stage1p5;
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end case;
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end case;
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end process stage1adderProc;
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end process stage1adderProc;
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stage1a1 <= stage1p2-stage1p3; -- This is always going to be a substraction
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stage1a1 <= stage1p2-stage1p3; -- This is always going to be a substraction
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-- Adder Instantiation (Stage 2)
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-- Adder Instantiation (Stage 2)
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stage2a3 <= stage2a0+stage2p2;
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stage2a3 <= stage2a0+stage2p2;
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stage2a4 <= stage2p3+stage2a2;
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stage2a4 <= stage2p3+stage2a2;
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end generate useIeee;
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end generate useIeee;
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dontUseIeee:
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dontUseIeee:
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if use_std_logic_signed="NO" generate
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if use_std_logic_signed="NO" generate
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--! Adder 0, 16 bit carry lookahead low adder.
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--! Adder 0, 16 bit carry lookahead low adder.
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a0low : adder
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a0low : adder
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generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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port map (stage1p0(15 downto 0),stage1p1(15 downto 0),stageSRopcode,'0',stage1a0(15 downto 0),stage1_internalCarry(0));
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port map (stage1p0(15 downto 0),stage1p1(15 downto 0),stageSRopcode,'0',stage1a0(15 downto 0),stage1_internalCarry(0));
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--Adder 0, 16 bit carry lookahead high adder.
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--Adder 0, 16 bit carry lookahead high adder.
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a0high : adder
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a0high : adder
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generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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port map (stage1p0(31 downto 16),stage1p1(31 downto 16),stageSRopcode,stage1_internalCarry(0),stage1a0(31 downto 16),open);
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port map (stage1p0(31 downto 16),stage1p1(31 downto 16),stageSRopcode,stage1_internalCarry(0),stage1a0(31 downto 16),open);
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--! Adder 1, 16 bit carry lookahead low adder.
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--! Adder 1, 16 bit carry lookahead low adder.
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a1low : adder
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a1low : adder
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generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
|
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
|
port map (stage1p2(15 downto 0),stage1p3(15 downto 0),'1','0',stage1a1(15 downto 0),stage1_internalCarry(1));
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port map (stage1p2(15 downto 0),stage1p3(15 downto 0),'1','0',stage1a1(15 downto 0),stage1_internalCarry(1));
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--! Adder 1, 16 bit carry lookahead high adder.
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--! Adder 1, 16 bit carry lookahead high adder.
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a1high : adder
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a1high : adder
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generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
|
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
|
port map (stage1p2(31 downto 16),stage1p3(31 downto 16),'1',stage1_internalCarry(1),stage1a1(31 downto 16),open);
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port map (stage1p2(31 downto 16),stage1p3(31 downto 16),'1',stage1_internalCarry(1),stage1a1(31 downto 16),open);
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--! Adder 2, 16 bit carry lookahead low adder.
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--! Adder 2, 16 bit carry lookahead low adder.
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a2low : adder
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a2low : adder
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generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
|
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
|
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
|
port map (stage1p4(15 downto 0),stage1p5(15 downto 0),stageSRopcode,'0',stage1a2(15 downto 0),stage1_internalCarry(2));
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port map (stage1p4(15 downto 0),stage1p5(15 downto 0),stageSRopcode,'0',stage1a2(15 downto 0),stage1_internalCarry(2));
|
--! Adder 2, 16 bit carry lookahead high adder.
|
--! Adder 2, 16 bit carry lookahead high adder.
|
a2high : adder
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a2high : adder
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generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
|
generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
|
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
|
-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
|
port map (stage1p4(31 downto 16),stage1p5(31 downto 16),stageSRopcode,stage1_internalCarry(2),stage1a2(31 downto 16),open);
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port map (stage1p4(31 downto 16),stage1p5(31 downto 16),stageSRopcode,stage1_internalCarry(2),stage1a2(31 downto 16),open);
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-- Adder Instantiation (Stage 2)
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-- Adder Instantiation (Stage 2)
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--! Adder 3, 16 bit carry lookahead low adder.
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--! Adder 3, 16 bit carry lookahead low adder.
|
a3low : adder
|
a3low : adder
|
generic map (16,"CLA","NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
|
generic map (16,carry_logic,"NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
|
-- Dont instantiate Xor gates stage in the adder.
|
-- Dont instantiate Xor gates stage in the adder.
|
port map (stage2a0(15 downto 0),stage2p2(15 downto 0),'0','0',stage2a3(15 downto 0),stage2_internalCarry(0));
|
port map (stage2a0(15 downto 0),stage2p2(15 downto 0),'0','0',stage2a3(15 downto 0),stage2_internalCarry(0));
|
--Adder 3, 16 bit carry lookahead high adder.
|
--Adder 3, 16 bit carry lookahead high adder.
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a3high : adder
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a3high : adder
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generic map (16,"CLA","NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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generic map (16,carry_logic,"NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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-- Dont instantiate Xor gates stage in the adder.
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-- Dont instantiate Xor gates stage in the adder.
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port map (stage2a0(31 downto 16),stage2p2(31 downto 16),'0',stage2_internalCarry(0),stage2a3(31 downto 16),open);
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port map (stage2a0(31 downto 16),stage2p2(31 downto 16),'0',stage2_internalCarry(0),stage2a3(31 downto 16),open);
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--! Adder 4, 16 bit carry lookahead low adder.
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--! Adder 4, 16 bit carry lookahead low adder.
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a4low : adder
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a4low : adder
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generic map (16,"CLA","NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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generic map (16,carry_logic,"NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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-- Dont instantiate Xor gates stage in the adder.
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-- Dont instantiate Xor gates stage in the adder.
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port map (stage2p3(15 downto 0),stage2a2(15 downto 0),'0','0',stage2a4(15 downto 0),stage2_internalCarry(1));
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port map (stage2p3(15 downto 0),stage2a2(15 downto 0),'0','0',stage2a4(15 downto 0),stage2_internalCarry(1));
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--! Adder 4, 16 bit carry lookahead high adder.
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--! Adder 4, 16 bit carry lookahead high adder.
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a4high : adder
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a4high : adder
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generic map (16,"CLA","NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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generic map (16,carry_logic,"NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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-- Dont instantiate Xor gates stage in the adder.
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-- Dont instantiate Xor gates stage in the adder.
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port map (stage2p3(31 downto 16),stage2a2(31 downto 16),'0',stage2_internalCarry(1),stage2a4(31 downto 16),open);
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port map (stage2p3(31 downto 16),stage2a2(31 downto 16),'0',stage2_internalCarry(1),stage2a4(31 downto 16),open);
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|
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end generate dontUseIeee;
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end generate dontUseIeee;
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-- Incoming from opcoder.vhd signals into pipeline's stage 0.
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-- Incoming from opcoder.vhd signals into pipeline's stage 0.
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stage0mf00 <= m0f0;
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stage0mf00 <= m0f0;
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stage0mf01 <= m0f1;
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stage0mf01 <= m0f1;
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stage0mf10 <= m1f0;
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stage0mf10 <= m1f0;
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stage0mf11 <= m1f1;
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stage0mf11 <= m1f1;
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stage0mf20 <= m2f0;
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stage0mf20 <= m2f0;
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stage0mf21 <= m2f1;
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stage0mf21 <= m2f1;
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stage0mf30 <= m3f0;
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stage0mf30 <= m3f0;
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stage0mf31 <= m3f1;
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stage0mf31 <= m3f1;
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stage0mf40 <= m4f0;
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stage0mf40 <= m4f0;
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stage0mf41 <= m4f1;
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stage0mf41 <= m4f1;
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stage0mf50 <= m5f0;
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stage0mf50 <= m5f0;
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stage0mf51 <= m5f1;
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stage0mf51 <= m5f1;
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|
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-- Signal sequencing: as the multipliers use registered output and registered input is not necessary to write the sequence of stage 0 signals to stage 1 signals.
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-- Signal sequencing: as the multipliers use registered output and registered input is not necessary to write the sequence of stage 0 signals to stage 1 signals.
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-- so the simplistic path is taken: simply connect stage 0 to stage 1 lines. However this would not apply for the opcode signal
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-- so the simplistic path is taken: simply connect stage 0 to stage 1 lines. However this would not apply for the opcode signal
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stage1p0 <= stage0p0;
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stage1p0 <= stage0p0;
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stage1p1 <= stage0p1;
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stage1p1 <= stage0p1;
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stage1p2 <= stage0p2;
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stage1p2 <= stage0p2;
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stage1p3 <= stage0p3;
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stage1p3 <= stage0p3;
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stage1p4 <= stage0p4;
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stage1p4 <= stage0p4;
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stage1p5 <= stage0p5;
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stage1p5 <= stage0p5;
|
|
|
|
|
--Outcoming to the rest of the system (by the time i wrote this i dont know where this leads to... jeje)
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--Outcoming to the rest of the system (by the time i wrote this i dont know where this leads to... jeje)
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cpx <= stage1a0;
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cpx <= stage1a0;
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cpy <= stage1a1;
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cpy <= stage1a1;
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cpz <= stage1a2;
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cpz <= stage1a2;
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dp0 <= stage2a3;
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dp0 <= stage2a3;
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dp1 <= stage2a4;
|
dp1 <= stage2a4;
|
|
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-- Looking into the design the stage 1 to stage 2 are the sequences pipe stages that must be controlled in this particular HDL.
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-- Looking into the design the stage 1 to stage 2 are the sequences pipe stages that must be controlled in this particular HDL.
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--! Este proceso describe la manera en que se organizan las etapas de pipe.
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--! Este proceso describe la manera en que se organizan las etapas de pipe.
|
--! Todas las señales internas en las etapas de pipe, en el momento en que la entrada rst alcanza el nivel rstMasterValue, se colocan en '0'. Nótese que, salvo stageMopcode<=stageSRopcode, las señales que vienen desde la entrada hacia los multiplicadores en la etapa 0 y desde la salida de los multiplicadores desde la etapa0 hacia la etapa 1, no están siendo descritas en este proceso, la explicación de es simple: Los multiplicadores que se están instanciado tienen registros a la entrada y la salida, permitiendo así, registrar las entradas y registrar los productos o salidas de los multiplicadores, hacia la etapa 1 o etapa de sumadores/restadores.
|
--! Todas las señales internas en las etapas de pipe, en el momento en que la entrada rst alcanza el nivel rstMasterValue, se colocan en '0'. Nótese que, salvo stageMopcode<=stageSRopcode, las señales que vienen desde la entrada hacia los multiplicadores en la etapa 0 y desde la salida de los multiplicadores desde la etapa0 hacia la etapa 1, no están siendo descritas en este proceso, la explicación de es simple: Los multiplicadores que se están instanciado tienen registros a la entrada y la salida, permitiendo así, registrar las entradas y registrar los productos o salidas de los multiplicadores, hacia la etapa 1 o etapa de sumadores/restadores.
|
|
|
uf_seq: process (clk,rst)
|
uf_seq: process (clk,rst)
|
begin
|
begin
|
|
|
if rst=rstMasterValue then
|
if rst=rstMasterValue then
|
stageMopcode <= '0';
|
stageMopcode <= '0';
|
stageSRopcode <= '0';
|
stageSRopcode <= '0';
|
|
|
stage2a2 <= (others => '0');
|
stage2a2 <= (others => '0');
|
stage2p3 <= (others => '0');
|
stage2p3 <= (others => '0');
|
stage2p2 <= (others => '0');
|
stage2p2 <= (others => '0');
|
stage2a0 <= (others => '0');
|
stage2a0 <= (others => '0');
|
|
|
elsif clk'event and clk = '1' then
|
elsif clk'event and clk = '1' then
|
|
|
stage2a2 <= stage1a2;
|
stage2a2 <= stage1a2;
|
stage2p3 <= stage1p3;
|
stage2p3 <= stage1p3;
|
stage2p2 <= stage1p2;
|
stage2p2 <= stage1p2;
|
stage2a0 <= stage1a0;
|
stage2a0 <= stage1a0;
|
|
|
-- Opcode control sequence
|
-- Opcode control sequence
|
stageMopcode <= opcode;
|
stageMopcode <= opcode;
|
stageSRopcode <= stageMopcode;
|
stageSRopcode <= stageMopcode;
|
|
|
end if;
|
end if;
|
end process uf_seq;
|
end process uf_seq;
|
|
|
|
|
|
|
end uf_arch;
|
end uf_arch;
|
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