`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2016-2022 Robert Finch, Waterloo
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// \\__/ o\ (C) 2016-2022 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// rf68000_mmu.sv
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// rf68000_mmu.sv
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//
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//
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//
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//
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// BSD 3-Clause License
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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// 1. Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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// list of conditions and the following disclaimer.
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//
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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// this software without specific prior written permission.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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`define LOW 1'b0
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`define LOW 1'b0
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`define HIGH 1'b1
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`define HIGH 1'b1
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module rf68000_mmu(rst_i, clk_i, s_ex_i, s_cs_i, s_cyc_i, s_stb_i, s_ack_o, s_we_i,
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module rf68000_mmu(rst_i, clk_i, s_ex_i, s_cs_i, s_cyc_i, s_stb_i, s_ack_o, s_we_i,
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s_asid_i, s_adr_i, s_dat_i, s_dat_o,
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s_asid_i, s_adr_i, s_dat_i, s_dat_o,
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pea_o, cyc_o, stb_o, we_o, pdat_o,
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pea_o, cyc_o, stb_o, we_o, pdat_o,
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exv_o, rdv_o, wrv_o);
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exv_o, rdv_o, wrv_o);
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input rst_i;
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input rst_i;
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input clk_i;
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input clk_i;
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input s_ex_i; // executable address
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input s_ex_i; // executable address
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input s_cs_i;
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input s_cs_i;
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input s_cyc_i;
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input s_cyc_i;
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input s_stb_i;
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input s_stb_i;
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input s_we_i; // write strobe
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input s_we_i; // write strobe
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output s_ack_o;
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output s_ack_o;
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input [7:0] s_asid_i;
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input [7:0] s_asid_i;
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input [31:0] s_adr_i; // virtual address
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input [31:0] s_adr_i; // virtual address
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input [31:0] s_dat_i;
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input [31:0] s_dat_i;
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output reg [31:0] s_dat_o;
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output reg [31:0] s_dat_o;
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output reg [31:0] pea_o;
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output reg [31:0] pea_o;
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output reg cyc_o;
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output reg cyc_o;
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output reg stb_o;
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output reg stb_o;
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output reg we_o;
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output reg we_o;
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output reg [31:0] pdat_o;
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output reg [31:0] pdat_o;
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output reg exv_o; // execute violation
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output reg exv_o; // execute violation
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output reg rdv_o; // read violation
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output reg rdv_o; // read violation
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output reg wrv_o; // write violation
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output reg wrv_o; // write violation
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wire cs = s_cyc_i && s_stb_i && s_cs_i;
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wire cs = s_cyc_i && s_stb_i && s_cs_i;
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wire [5:0] okey = s_asid_i[5:0];
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wire [5:0] okey = s_asid_i[5:0];
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wire [5:0] akey = s_asid_i[5:0];
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wire [5:0] akey = s_asid_i[5:0];
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ack_gen #(
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ack_gen #(
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.READ_STAGES(3),
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.READ_STAGES(3),
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.WRITE_STAGES(0),
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.WRITE_STAGES(0),
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.REGISTER_OUTPUT(1)
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.REGISTER_OUTPUT(1)
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) uag1
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) uag1
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(
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(
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.rst_i(rst_i),
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.rst_i(rst_i),
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.clk_i(clk_i),
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.clk_i(clk_i),
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.ce_i(1'b1),
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.ce_i(1'b1),
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.i(cs & ~s_we_i),
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.i(cs & ~s_we_i),
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.we_i(cs & s_we_i),
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.we_i(cs & s_we_i),
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.o(s_ack_o),
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.o(s_ack_o),
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.rid_i(0),
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.rid_i(0),
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.wid_i(0),
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.wid_i(0),
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.rid_o(),
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.rid_o(),
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.wid_o()
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.wid_o()
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);
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);
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reg cyc1,cyc2,stb1,stb2;
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reg cyc1,cyc2,stb1,stb2;
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wire [17:0] douta;
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wire [17:0] douta;
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wire [17:0] doutb;
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wire [17:0] doutb;
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wire [1:0] wx = doutb[17:16];
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wire [1:0] wx = doutb[17:16];
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always @(posedge clk_i)
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always @(posedge clk_i)
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exv_o <= s_ex_i & ~wx[0] & cyc2 & stb2;
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exv_o <= s_ex_i & ~wx[0] & cyc2 & stb2;
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always @(posedge clk_i)
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always @(posedge clk_i)
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rdv_o <= 1'b0;
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rdv_o <= 1'b0;
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always @(posedge clk_i)
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always @(posedge clk_i)
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wrv_o <= s_we_i & ~wx[1] & cyc2 & stb2;
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wrv_o <= s_we_i & ~wx[1] & cyc2 & stb2;
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wire [14:0] addra = {akey[5:0],s_adr_i[10: 2]};
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wire [14:0] addra = {akey[5:0],s_adr_i[10: 2]};
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wire [14:0] addrb = {okey[5:0],s_adr_i[24:16]};
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wire [14:0] addrb = {okey[5:0],s_adr_i[24:16]};
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wire clka = clk_i;
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wire clka = clk_i;
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wire clkb = clk_i;
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wire clkb = clk_i;
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wire [17:0] dina = s_dat_i[17:0];
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wire [17:0] dina = s_dat_i[17:0];
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wire [17:0] dinb = 18'h0;
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wire [17:0] dinb = 18'h0;
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wire ena = cs;
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wire ena = cs;
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wire enb = 1'b1;
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wire enb = 1'b1;
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wire wea = s_we_i;
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wire wea = s_we_i;
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wire web = 1'b0;
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wire web = 1'b0;
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// xpm_memory_tdpram: True Dual Port RAM
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// xpm_memory_tdpram: True Dual Port RAM
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// Xilinx Parameterized Macro, version 2022.2
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// Xilinx Parameterized Macro, version 2022.2
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xpm_memory_tdpram #(
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xpm_memory_tdpram #(
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.ADDR_WIDTH_A(15), // DECIMAL
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.ADDR_WIDTH_A(15), // DECIMAL
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.ADDR_WIDTH_B(15), // DECIMAL
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.ADDR_WIDTH_B(15), // DECIMAL
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.AUTO_SLEEP_TIME(0), // DECIMAL
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.AUTO_SLEEP_TIME(0), // DECIMAL
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.BYTE_WRITE_WIDTH_A(18), // DECIMAL
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.BYTE_WRITE_WIDTH_A(18), // DECIMAL
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.BYTE_WRITE_WIDTH_B(18), // DECIMAL
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.BYTE_WRITE_WIDTH_B(18), // DECIMAL
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.CASCADE_HEIGHT(0), // DECIMAL
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.CASCADE_HEIGHT(0), // DECIMAL
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.CLOCKING_MODE("common_clock"), // String
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.CLOCKING_MODE("common_clock"), // String
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.ECC_MODE("no_ecc"), // String
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.ECC_MODE("no_ecc"), // String
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.MEMORY_INIT_FILE("none"), // String
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.MEMORY_INIT_FILE("none"), // String
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.MEMORY_INIT_PARAM("0"), // String
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.MEMORY_INIT_PARAM("0"), // String
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.MEMORY_OPTIMIZATION("true"), // String
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.MEMORY_OPTIMIZATION("true"), // String
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.MEMORY_PRIMITIVE("auto"), // String
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.MEMORY_PRIMITIVE("auto"), // String
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.MEMORY_SIZE(589824), // DECIMAL
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.MEMORY_SIZE(589824), // DECIMAL
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.MESSAGE_CONTROL(0), // DECIMAL
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.MESSAGE_CONTROL(0), // DECIMAL
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.READ_DATA_WIDTH_A(18), // DECIMAL
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.READ_DATA_WIDTH_A(18), // DECIMAL
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.READ_DATA_WIDTH_B(18), // DECIMAL
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.READ_DATA_WIDTH_B(18), // DECIMAL
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.READ_LATENCY_A(2), // DECIMAL
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.READ_LATENCY_A(2), // DECIMAL
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.READ_LATENCY_B(1), // DECIMAL
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.READ_LATENCY_B(1), // DECIMAL
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.READ_RESET_VALUE_A("0"), // String
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.READ_RESET_VALUE_A("0"), // String
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.READ_RESET_VALUE_B("0"), // String
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.READ_RESET_VALUE_B("0"), // String
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.RST_MODE_A("SYNC"), // String
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.RST_MODE_A("SYNC"), // String
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.RST_MODE_B("SYNC"), // String
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.RST_MODE_B("SYNC"), // String
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.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
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.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
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.USE_EMBEDDED_CONSTRAINT(0), // DECIMAL
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.USE_EMBEDDED_CONSTRAINT(0), // DECIMAL
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.USE_MEM_INIT(1), // DECIMAL
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.USE_MEM_INIT(1), // DECIMAL
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.USE_MEM_INIT_MMI(0), // DECIMAL
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.USE_MEM_INIT_MMI(0), // DECIMAL
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.WAKEUP_TIME("disable_sleep"), // String
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.WAKEUP_TIME("disable_sleep"), // String
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.WRITE_DATA_WIDTH_A(18), // DECIMAL
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.WRITE_DATA_WIDTH_A(18), // DECIMAL
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.WRITE_DATA_WIDTH_B(18), // DECIMAL
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.WRITE_DATA_WIDTH_B(18), // DECIMAL
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.WRITE_MODE_A("no_change"), // String
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.WRITE_MODE_A("no_change"), // String
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.WRITE_MODE_B("no_change"), // String
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.WRITE_MODE_B("no_change"), // String
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.WRITE_PROTECT(1) // DECIMAL
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.WRITE_PROTECT(1) // DECIMAL
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)
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)
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xpm_memory_tdpram_inst (
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xpm_memory_tdpram_inst (
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.dbiterra(), // 1-bit output: Status signal to indicate double bit error occurrence
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.dbiterra(), // 1-bit output: Status signal to indicate double bit error occurrence
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// on the data output of port A.
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// on the data output of port A.
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.dbiterrb(), // 1-bit output: Status signal to indicate double bit error occurrence
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.dbiterrb(), // 1-bit output: Status signal to indicate double bit error occurrence
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// on the data output of port A.
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// on the data output of port A.
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.douta(douta), // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
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.douta(douta), // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
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.doutb(doutb), // READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
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.doutb(doutb), // READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
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.sbiterra(), // 1-bit output: Status signal to indicate single bit error occurrence
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.sbiterra(), // 1-bit output: Status signal to indicate single bit error occurrence
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// on the data output of port A.
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// on the data output of port A.
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.sbiterrb(), // 1-bit output: Status signal to indicate single bit error occurrence
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.sbiterrb(), // 1-bit output: Status signal to indicate single bit error occurrence
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// on the data output of port B.
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// on the data output of port B.
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.addra(addra), // ADDR_WIDTH_A-bit input: Address for port A write and read operations.
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.addra(addra), // ADDR_WIDTH_A-bit input: Address for port A write and read operations.
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.addrb(addrb), // ADDR_WIDTH_B-bit input: Address for port B write and read operations.
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.addrb(addrb), // ADDR_WIDTH_B-bit input: Address for port B write and read operations.
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.clka(clka), // 1-bit input: Clock signal for port A. Also clocks port B when
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.clka(clka), // 1-bit input: Clock signal for port A. Also clocks port B when
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// parameter CLOCKING_MODE is "common_clock".
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// parameter CLOCKING_MODE is "common_clock".
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.clkb(clkb), // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is
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.clkb(clkb), // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is
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// "independent_clock". Unused when parameter CLOCKING_MODE is
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// "independent_clock". Unused when parameter CLOCKING_MODE is
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// "common_clock".
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// "common_clock".
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.dina(dina), // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
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.dina(dina), // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
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.dinb(dinb), // WRITE_DATA_WIDTH_B-bit input: Data input for port B write operations.
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.dinb(dinb), // WRITE_DATA_WIDTH_B-bit input: Data input for port B write operations.
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.ena(ena), // 1-bit input: Memory enable signal for port A. Must be high on clock
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.ena(ena), // 1-bit input: Memory enable signal for port A. Must be high on clock
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// cycles when read or write operations are initiated. Pipelined
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// cycles when read or write operations are initiated. Pipelined
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// internally.
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// internally.
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.enb(enb), // 1-bit input: Memory enable signal for port B. Must be high on clock
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.enb(enb), // 1-bit input: Memory enable signal for port B. Must be high on clock
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// cycles when read or write operations are initiated. Pipelined
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// cycles when read or write operations are initiated. Pipelined
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// internally.
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// internally.
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.injectdbiterra(1'b0), // 1-bit input: Controls double bit error injection on input data when
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.injectdbiterra(1'b0), // 1-bit input: Controls double bit error injection on input data when
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// ECC enabled (Error injection capability is not available in
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// ECC enabled (Error injection capability is not available in
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// "decode_only" mode).
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// "decode_only" mode).
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.injectdbiterrb(1'b0), // 1-bit input: Controls double bit error injection on input data when
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.injectdbiterrb(1'b0), // 1-bit input: Controls double bit error injection on input data when
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// ECC enabled (Error injection capability is not available in
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// ECC enabled (Error injection capability is not available in
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// "decode_only" mode).
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// "decode_only" mode).
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.injectsbiterra(1'b0), // 1-bit input: Controls single bit error injection on input data when
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.injectsbiterra(1'b0), // 1-bit input: Controls single bit error injection on input data when
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// ECC enabled (Error injection capability is not available in
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// ECC enabled (Error injection capability is not available in
|
// "decode_only" mode).
|
// "decode_only" mode).
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|
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.injectsbiterrb(1'b0), // 1-bit input: Controls single bit error injection on input data when
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.injectsbiterrb(1'b0), // 1-bit input: Controls single bit error injection on input data when
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// ECC enabled (Error injection capability is not available in
|
// ECC enabled (Error injection capability is not available in
|
// "decode_only" mode).
|
// "decode_only" mode).
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|
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.regcea(1'b1), // 1-bit input: Clock Enable for the last register stage on the output
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.regcea(1'b1), // 1-bit input: Clock Enable for the last register stage on the output
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// data path.
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// data path.
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|
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.regceb(1'b1), // 1-bit input: Clock Enable for the last register stage on the output
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.regceb(1'b1), // 1-bit input: Clock Enable for the last register stage on the output
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// data path.
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// data path.
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|
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.rsta(1'b0), // 1-bit input: Reset signal for the final port A output register stage.
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.rsta(1'b0), // 1-bit input: Reset signal for the final port A output register stage.
|
// Synchronously resets output port douta to the value specified by
|
// Synchronously resets output port douta to the value specified by
|
// parameter READ_RESET_VALUE_A.
|
// parameter READ_RESET_VALUE_A.
|
|
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.rstb(1'b0), // 1-bit input: Reset signal for the final port B output register stage.
|
.rstb(1'b0), // 1-bit input: Reset signal for the final port B output register stage.
|
// Synchronously resets output port doutb to the value specified by
|
// Synchronously resets output port doutb to the value specified by
|
// parameter READ_RESET_VALUE_B.
|
// parameter READ_RESET_VALUE_B.
|
|
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.sleep(1'b0), // 1-bit input: sleep signal to enable the dynamic power saving feature.
|
.sleep(1'b0), // 1-bit input: sleep signal to enable the dynamic power saving feature.
|
.wea(wea), // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
|
.wea(wea), // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
|
// for port A input data port dina. 1 bit wide when word-wide writes are
|
// for port A input data port dina. 1 bit wide when word-wide writes are
|
// used. In byte-wide write configurations, each bit controls the
|
// used. In byte-wide write configurations, each bit controls the
|
// writing one byte of dina to address addra. For example, to
|
// writing one byte of dina to address addra. For example, to
|
// synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
|
// synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
|
// is 32, wea would be 4'b0010.
|
// is 32, wea would be 4'b0010.
|
|
|
.web(web) // WRITE_DATA_WIDTH_B/BYTE_WRITE_WIDTH_B-bit input: Write enable vector
|
.web(web) // WRITE_DATA_WIDTH_B/BYTE_WRITE_WIDTH_B-bit input: Write enable vector
|
// for port B input data port dinb. 1 bit wide when word-wide writes are
|
// for port B input data port dinb. 1 bit wide when word-wide writes are
|
// used. In byte-wide write configurations, each bit controls the
|
// used. In byte-wide write configurations, each bit controls the
|
// writing one byte of dinb to address addrb. For example, to
|
// writing one byte of dinb to address addrb. For example, to
|
// synchronously write only bits [15-8] of dinb when WRITE_DATA_WIDTH_B
|
// synchronously write only bits [15-8] of dinb when WRITE_DATA_WIDTH_B
|
// is 32, web would be 4'b0010.
|
// is 32, web would be 4'b0010.
|
|
|
);
|
);
|
|
|
always_ff @(posedge clk_i)
|
always_ff @(posedge clk_i)
|
if (s_cs_i)
|
if (s_cs_i)
|
s_dat_o <= {14'h0,douta};
|
s_dat_o <= {14'h0,douta};
|
else
|
else
|
s_dat_o <= 32'h0;
|
s_dat_o <= 32'h0;
|
|
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
if (rst_i) begin
|
if (rst_i) begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
pea_o <= 32'h0;
|
pea_o <= 32'h0;
|
pdat_o <= 'd0;
|
pdat_o <= 'd0;
|
end
|
end
|
else begin
|
else begin
|
pea_o[15: 0] <= s_adr_i[15:0];
|
pea_o[15: 0] <= s_adr_i[15:0];
|
pea_o[31:16] <= doutb[15:0];
|
pea_o[31:16] <= doutb[15:0];
|
pdat_o <= s_dat_i;
|
pdat_o <= s_dat_i;
|
|
if (s_cs_i)
|
|
pea_o <= 'd0;
|
if (cs) begin
|
if (cs) begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
end
|
end
|
else begin
|
else begin
|
cyc_o <= s_cyc_i;
|
cyc_o <= s_cyc_i;
|
stb_o <= s_stb_i;
|
stb_o <= s_stb_i;
|
end
|
end
|
end
|
end
|
always_comb
|
always_comb
|
we_o <= wx[1] & s_we_i;
|
we_o <= wx[1] & s_we_i;
|
|
|
endmodule
|
endmodule
|
|
|