`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2013-2022 Robert Finch, Waterloo
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// \\__/ o\ (C) 2013-2022 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// BSD 3-Clause License
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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// 1. Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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// list of conditions and the following disclaimer.
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//
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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// this software without specific prior written permission.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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//
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//
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// Encodes discrete interrupt request signals into five
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// Encodes discrete interrupt request signals into five
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// bit code using a priority encoder.
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// bit code using a priority encoder.
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//
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//
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// reg
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// reg
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// 0x00 - encoded request number (read / write)
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// 0x00 - encoded request number (read / write)
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// This register contains the number identifying
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// This register contains the number identifying
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// the current requester in bits 0 to 4
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// the current requester in bits 0 to 4
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// If there is no
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// If there is no
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// active request, then this number will be
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// active request, then this number will be
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// zero.
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// zero.
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// bits 8 to 15 set the base number for the vector
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// bits 8 to 15 set the base number for the vector
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//
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//
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// 0x04 - request enable (read / write)
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// 0x04 - request enable (read / write)
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// this register contains request enable bits
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// this register contains request enable bits
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// for each request line. 1 = request
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// for each request line. 1 = request
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// enabled, 0 = request disabled. On reset this
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// enabled, 0 = request disabled. On reset this
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// register is set to zero (disable all ints).
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// register is set to zero (disable all ints).
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// bit zero is specially reserved for nmi
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// bit zero is specially reserved for nmi
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//
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//
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// 0x08 - write only
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// 0x08 - write only
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// this register disables the interrupt indicated
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// this register disables the interrupt indicated
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// by the low order five bits of the input data
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// by the low order five bits of the input data
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//
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//
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// 0x0C - write only
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// 0x0C - write only
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// this register enables the interrupt indicated
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// this register enables the interrupt indicated
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// by the low order five bits of the input data
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// by the low order five bits of the input data
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//
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//
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// 0x10 - write only
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// 0x10 - write only
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// this register indicates which interrupt inputs are
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// this register indicates which interrupt inputs are
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// edge sensitive
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// edge sensitive
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//
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//
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// 0x14 - write only
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// 0x14 - write only
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// This register resets the edge sense circuitry
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// This register resets the edge sense circuitry
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// indicated by the low order five bits of the input data.
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// indicated by the low order five bits of the input data.
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//
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//
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// 0x18 - write only
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// 0x18 - write only
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// This register triggers the interrupt indicated by the low
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// This register triggers the interrupt indicated by the low
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// order five bits of the input data.
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// order five bits of the input data.
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//
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//
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// 0x80 - irq control for irq #0
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// 0x80 - irq control for irq #0
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// 0x84 - irq control for irq #1
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// 0x84 - irq control for irq #1
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// bits 0 to 7 = cause code to issue
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// bits 0 to 7 = cause code to issue
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// bits 8 to 11 = irq level to issue
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// bits 8 to 11 = irq level to issue
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// bit 16 = irq enable
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// bit 16 = irq enable
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// bit 17 = edge sensitivity
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// bit 17 = edge sensitivity
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//=============================================================================
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//=============================================================================
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import rf6809_pkg::*;
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import rf6809_pkg::*;
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module rf6809_pic
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module rf6809_pic
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(
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(
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input rst_i, // reset
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input rst_i, // reset
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input clk_i, // system clock
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input clk_i, // system clock
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input cs_i,
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input cs_i,
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input cyc_i,
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input cyc_i,
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input stb_i,
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input stb_i,
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output ack_o, // controller is ready
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output ack_o, // controller is ready
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input wr_i, // write
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input wr_i, // write
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input [7:0] adr_i, // address
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input [7:0] adr_i, // address
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input [BPB:0] dat_i,
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input [BPB:0] dat_i,
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output reg [BPB:0] dat_o,
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output reg [BPB:0] dat_o,
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output vol_o, // volatile register selected
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output vol_o, // volatile register selected
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input i1, i2, i3, i4, i5, i6, i7,
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input i1, i2, i3, i4, i5, i6, i7,
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i8, i9, i10, i11, i12, i13, i14, i15,
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i8, i9, i10, i11, i12, i13, i14, i15,
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i16, i17, i18, i19, i20, i21, i22, i23,
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i16, i17, i18, i19, i20, i21, i22, i23,
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i24, i25, i26, i27, i28, i29, i30, i31,
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i24, i25, i26, i27, i28, i29, i30, i31,
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output reg [3:0] irqo, // normally connected to the processor irq
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output reg [3:0] irqo, // normally connected to the processor irq
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input nmii, // nmi input connected to nmi requester
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input nmii, // nmi input connected to nmi requester
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output reg nmio, // normally connected to the nmi of cpu
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output reg nmio, // normally connected to the nmi of cpu
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output reg [BPB:0] causeo,
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output reg [BPB:0] causeo,
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output reg [5:0] server_o
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output reg [5:0] server_o
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);
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);
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wire clk;
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wire clk;
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reg [31:0] trig;
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reg [31:0] trig;
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reg [31:0] ie; // interrupt enable register
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reg [31:0] ie; // interrupt enable register
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reg rdy1;
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reg rdy1;
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reg [4:0] irqenc;
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reg [4:0] irqenc;
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wire [31:0] i = { i31,i30,i29,i28,i27,i26,i25,i24,i23,i22,i21,i20,i19,i18,i17,i16,
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wire [31:0] i = { i31,i30,i29,i28,i27,i26,i25,i24,i23,i22,i21,i20,i19,i18,i17,i16,
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i15,i14,i13,i12,i11,i10,i9,i8,i7,i6,i5,i4,i3,i2,i1,nmii};
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i15,i14,i13,i12,i11,i10,i9,i8,i7,i6,i5,i4,i3,i2,i1,nmii};
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reg [31:0] ib;
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reg [31:0] ib;
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reg [31:0] iedge;
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reg [31:0] iedge;
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reg [31:0] rste;
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reg [31:0] rste;
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reg [31:0] es;
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reg [31:0] es;
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reg [31:0] irq_active;
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reg [3:0] irq [0:31];
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reg [3:0] irq [0:31];
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reg [BPB:0] cause [0:31];
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reg [BPB:0] cause [0:31];
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reg [5:0] server [0:31];
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reg [5:0] server [0:31];
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integer n;
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integer n;
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initial begin
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initial begin
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ie <= 32'h0;
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ie <= 32'h0;
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es <= 32'hFFFFFFFF;
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es <= 32'hFFFFFFFF;
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rste <= 32'h0;
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rste <= 32'h0;
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for (n = 0; n < 32; n = n + 1) begin
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for (n = 0; n < 32; n = n + 1) begin
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cause[n] <= {BPB{1'b0}};
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cause[n] <= {BPB{1'b0}};
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irq[n] <= 4'h8;
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irq[n] <= 4'h8;
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server[n] <= 6'd2;
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server[n] <= 6'd2;
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end
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end
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end
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end
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wire cs = cyc_i && stb_i && cs_i;
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wire cs = cyc_i && stb_i && cs_i;
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assign vol_o = cs;
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assign vol_o = cs;
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assign clk = clk_i;
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assign clk = clk_i;
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//BUFH ucb1 (.I(clk_i), .O(clk));
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//BUFH ucb1 (.I(clk_i), .O(clk));
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always @(posedge clk)
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always @(posedge clk)
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rdy1 <= cs;
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rdy1 <= cs;
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assign ack_o = cs ? (wr_i ? 1'b1 : rdy1) : 1'b0;
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assign ack_o = cs ? (wr_i ? 1'b1 : rdy1) : 1'b0;
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// write registers
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// write registers
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always @(posedge clk)
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always @(posedge clk)
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if (rst_i) begin
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if (rst_i) begin
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ie <= 32'h0;
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ie <= 32'h0;
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rste <= 32'h0;
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rste <= 32'h0;
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trig <= 32'h0;
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trig <= 32'h0;
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end
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end
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else begin
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else begin
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rste <= 32'h0;
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rste <= 32'h0;
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trig <= 32'h0;
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trig <= 32'h0;
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if (cs & wr_i) begin
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if (cs & wr_i) begin
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casez (adr_i[7:0])
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casez (adr_i[7:0])
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8'd0: ;
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8'd0: ;
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8'd4: ie[31:24] <= dat_i;
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8'd4: ie[31:24] <= dat_i;
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8'd5: ie[23:16] <= dat_i;
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8'd5: ie[23:16] <= dat_i;
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8'd6: ie[15: 8] <= dat_i;
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8'd6: ie[15: 8] <= dat_i;
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8'd7: ie[ 7: 0] <= dat_i;
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8'd7: ie[ 7: 0] <= dat_i;
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8'd8,8'd9:
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8'd8,8'd9:
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ie[dat_i[4:0]] <= adr_i[0];
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ie[dat_i[4:0]] <= adr_i[0];
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8'd12: es[31:24] <= dat_i;
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8'd12: es[31:24] <= dat_i;
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8'd13: es[23:16] <= dat_i;
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8'd13: es[23:16] <= dat_i;
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8'd14: es[15: 8] <= dat_i;
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8'd14: es[15: 8] <= dat_i;
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8'd15: es[ 7: 0] <= dat_i;
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8'd15: es[ 7: 0] <= dat_i;
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8'd16: rste[dat_i[4:0]] <= 1'b1;
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8'd16: rste[dat_i[4:0]] <= 1'b1;
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8'd17: trig[dat_i[4:0]] <= 1'b1;
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8'd17: trig[dat_i[4:0]] <= 1'b1;
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8'b1?????00:
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8'b1?????00:
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cause[adr_i[6:2]] <= dat_i;
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cause[adr_i[6:2]] <= dat_i;
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8'b1?????01:
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8'b1?????01:
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begin
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begin
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irq[adr_i[6:2]] <= dat_i[3:0];
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irq[adr_i[6:2]] <= dat_i[3:0];
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ie[adr_i[6:2]] <= dat_i[6];
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ie[adr_i[6:2]] <= dat_i[6];
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es[adr_i[6:2]] <= dat_i[7];
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es[adr_i[6:2]] <= dat_i[7];
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end
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end
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8'b1?????10:
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8'b1?????10:
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server[adr_i[6:2]] <= dat_i[5:0];
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server[adr_i[6:2]] <= dat_i[5:0];
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default: ;
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default: ;
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endcase
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endcase
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end
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end
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end
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end
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// read registers
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// read registers
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (irqenc!=5'd0)
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if (irqenc!=5'd0)
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$display("PIC: %d",irqenc);
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$display("PIC: %d",irqenc);
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if (cs)
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if (cs)
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casez (adr_i[7:0])
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casez (adr_i[7:0])
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8'd0: dat_o <= cause[irqenc];
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8'd0: dat_o <= cause[irqenc];
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8'd4: dat_o <= ie[31:24];
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8'd4: dat_o <= ie[31:24];
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8'd5: dat_o <= ie[23:16];
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8'd5: dat_o <= ie[23:16];
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8'd6: dat_o <= ie[15: 8];
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8'd6: dat_o <= ie[15: 8];
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8'd7: dat_o <= ie[ 7: 0];
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8'd7: dat_o <= ie[ 7: 0];
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8'b1?????00: dat_o <= cause[adr_i[6:2]];
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8'b1?????00: dat_o <= cause[adr_i[6:2]];
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8'b1?????01: dat_o <= {es[adr_i[6:2]],ie[adr_i[6:2]],2'b0,irq[adr_i[6:2]]};
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8'b1?????01: dat_o <= {es[adr_i[6:2]],ie[adr_i[6:2]],2'b0,irq[adr_i[6:2]]};
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8'b1?????10: dat_o <= {2'b0,server[adr_i[6:2]]};
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8'b1?????10: dat_o <= {2'b0,server[adr_i[6:2]]};
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8'b1?????11: dat_o <= irq_active[adr_i[6:2]];
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default: dat_o <= 12'h00;
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default: dat_o <= 12'h00;
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endcase
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endcase
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else
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else
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dat_o <= 12'h00;
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dat_o <= 12'h00;
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end
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end
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always @(posedge clk)
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always @(posedge clk)
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irqo <= (irqenc == 5'h0) ? 4'd0 : irq[irqenc] & {4{ie[irqenc]}};
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irqo <= (irqenc == 5'h0) ? 4'd0 : irq[irqenc] & {4{ie[irqenc]}};
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always @(posedge clk)
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always @(posedge clk)
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causeo <= (irqenc == 5'h0) ? 8'd0 : cause[irqenc];
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causeo <= (irqenc == 5'h0) ? 8'd0 : cause[irqenc];
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always @(posedge clk)
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always @(posedge clk)
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server_o <= (irqenc == 5'h0) ? 6'd0 : server[irqenc];
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server_o <= (irqenc == 5'h0) ? 6'd0 : server[irqenc];
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always @(posedge clk)
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always @(posedge clk)
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nmio <= nmii & ie[0];
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nmio <= nmii & ie[0];
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// Edge detect circuit
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// Edge detect circuit
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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for (n = 1; n < 32; n = n + 1)
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for (n = 1; n < 32; n = n + 1)
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begin
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begin
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ib[n] <= i[n];
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ib[n] <= i[n];
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if (trig[n]) iedge[n] <= 1'b1;
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if (trig[n]) iedge[n] <= 1'b1;
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if (i[n] & !ib[n]) iedge[n] <= 1'b1;
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if (i[n] & !ib[n]) iedge[n] <= 1'b1;
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if (rste[n]) iedge[n] <= 1'b0;
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if (rste[n]) iedge[n] <= 1'b0;
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end
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end
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end
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end
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// irq requests are latched on every rising clock edge to prevent
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// irq requests are latched on every rising clock edge to prevent
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// misreads
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// misreads
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// nmi is not encoded
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// nmi is not encoded
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always @(posedge clk)
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always @(posedge clk)
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begin
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if (rst_i)
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irq_active <= 32'd0;
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else begin
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irqenc <= 5'd0;
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irqenc <= 5'd0;
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for (n = 31; n > 0; n = n - 1)
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for (n = 31; n > 0; n = n - 1) begin
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if ((es[n] ? iedge[n] : i[n])) irqenc <= n;
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if ((es[n] ? iedge[n] : i[n])) irqenc <= n;
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if ((es[n] ? iedge[n] : i[n])) irq_active[n] <= 1'b1;
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end
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if (cs && wr_i && adr_i[7] && &adr_i[1:0])
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irq_active[adr_i[6:2]] <= dat_i[0];
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end
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end
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endmodule
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endmodule
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