/**
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/**
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* @file
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* @file
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* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
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* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
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* @author Sergey Khabarov - sergeykhbr@gmail.com
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* @author Sergey Khabarov - sergeykhbr@gmail.com
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* @brief Memory Cache Top level.
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* @brief Memory Cache Top level.
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*/
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*/
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#ifndef __DEBUGGER_RIVERLIB_CACHE_TOP_H__
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#ifndef __DEBUGGER_RIVERLIB_CACHE_TOP_H__
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#define __DEBUGGER_RIVERLIB_CACHE_TOP_H__
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#define __DEBUGGER_RIVERLIB_CACHE_TOP_H__
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#include <systemc.h>
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#include <systemc.h>
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#include "../river_cfg.h"
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#include "../river_cfg.h"
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#include "icache.h"
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#include "icache.h"
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#include "dcache.h"
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#include "dcache.h"
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namespace debugger {
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namespace debugger {
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SC_MODULE(CacheTop) {
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SC_MODULE(CacheTop) {
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sc_in<bool> i_clk; // CPU clock
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sc_in<bool> i_clk; // CPU clock
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sc_in<bool> i_nrst; // Reset active LOW
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sc_in<bool> i_nrst; // Reset active LOW
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// Control path:
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// Control path:
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sc_in<bool> i_req_ctrl_valid; // Control request from CPU Core is valid
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sc_in<bool> i_req_ctrl_valid; // Control request from CPU Core is valid
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sc_in<sc_uint<BUS_ADDR_WIDTH>> i_req_ctrl_addr; // Control request address
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sc_in<sc_uint<BUS_ADDR_WIDTH>> i_req_ctrl_addr; // Control request address
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sc_out<bool> o_req_ctrl_ready; // Control request from CPU Core is accepted
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sc_out<bool> o_req_ctrl_ready; // Control request from CPU Core is accepted
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sc_out<bool> o_resp_ctrl_valid; // ICache response is valid and can be accepted
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sc_out<bool> o_resp_ctrl_valid; // ICache response is valid and can be accepted
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sc_out<sc_uint<BUS_ADDR_WIDTH>> o_resp_ctrl_addr; // ICache response address
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sc_out<sc_uint<BUS_ADDR_WIDTH>> o_resp_ctrl_addr; // ICache response address
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sc_out<sc_uint<32>> o_resp_ctrl_data; // ICache read data
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sc_out<sc_uint<32>> o_resp_ctrl_data; // ICache read data
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sc_in<bool> i_resp_ctrl_ready; // CPU Core is ready to accept ICache response
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sc_in<bool> i_resp_ctrl_ready; // CPU Core is ready to accept ICache response
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// Data path:
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// Data path:
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sc_in<bool> i_req_data_valid; // Data path request from CPU Core is valid
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sc_in<bool> i_req_data_valid; // Data path request from CPU Core is valid
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sc_in<bool> i_req_data_write; // Data write memopy operation flag
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sc_in<bool> i_req_data_write; // Data write memopy operation flag
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sc_in<sc_uint<2>> i_req_data_size; // Memory operation size: 0=1B; 1=2B; 2=4B; 3=8B
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sc_in<sc_uint<2>> i_req_data_size; // Memory operation size: 0=1B; 1=2B; 2=4B; 3=8B
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sc_in<sc_uint<BUS_ADDR_WIDTH>> i_req_data_addr; // Memory operation address
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sc_in<sc_uint<BUS_ADDR_WIDTH>> i_req_data_addr; // Memory operation address
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sc_in<sc_uint<RISCV_ARCH>> i_req_data_data; // Memory operation write value
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sc_in<sc_uint<RISCV_ARCH>> i_req_data_data; // Memory operation write value
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sc_out<bool> o_req_data_ready; // Memory operation request accepted by DCache
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sc_out<bool> o_req_data_ready; // Memory operation request accepted by DCache
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sc_out<bool> o_resp_data_valid; // DCache response is ready
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sc_out<bool> o_resp_data_valid; // DCache response is ready
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sc_out<sc_uint<BUS_ADDR_WIDTH>> o_resp_data_addr; // DCache response address
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sc_out<sc_uint<BUS_ADDR_WIDTH>> o_resp_data_addr; // DCache response address
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sc_out<sc_uint<RISCV_ARCH>> o_resp_data_data; // DCache response read data
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sc_out<sc_uint<RISCV_ARCH>> o_resp_data_data; // DCache response read data
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sc_in<bool> i_resp_data_ready; // CPU Core is ready to accept DCache repsonse
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sc_in<bool> i_resp_data_ready; // CPU Core is ready to accept DCache repsonse
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// Memory interface:
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// Memory interface:
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sc_in<bool> i_req_mem_ready; // System Bus (AXI) is available
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sc_in<bool> i_req_mem_ready; // System Bus (AXI) is available
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sc_out<bool> o_req_mem_valid; // Memory operation to system bus is valid
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sc_out<bool> o_req_mem_valid; // Memory operation to system bus is valid
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sc_out<bool> o_req_mem_write; // Memory operation write flag
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sc_out<bool> o_req_mem_write; // Memory operation write flag
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sc_out<sc_uint<BUS_ADDR_WIDTH>> o_req_mem_addr; // Requesting address
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sc_out<sc_uint<BUS_ADDR_WIDTH>> o_req_mem_addr; // Requesting address
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sc_out<sc_uint<BUS_DATA_BYTES>> o_req_mem_strob; // Writing strob 1 bit per 1 byte (AXI compliance)
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sc_out<sc_uint<BUS_DATA_BYTES>> o_req_mem_strob; // Writing strob 1 bit per 1 byte (AXI compliance)
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sc_out<sc_uint<BUS_DATA_WIDTH>> o_req_mem_data; // Writing value
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sc_out<sc_uint<BUS_DATA_WIDTH>> o_req_mem_data; // Writing value
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sc_in<bool> i_resp_mem_data_valid; // Memory operation from system bus is completed
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sc_in<bool> i_resp_mem_data_valid; // Memory operation from system bus is completed
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sc_in<sc_uint<BUS_DATA_WIDTH>> i_resp_mem_data; // Read value
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sc_in<sc_uint<BUS_DATA_WIDTH>> i_resp_mem_data; // Read value
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// Debug signals:
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// Debug signals:
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sc_out<sc_uint<2>> o_istate; // ICache state machine value
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sc_out<sc_uint<2>> o_istate; // ICache state machine value
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sc_out<sc_uint<2>> o_dstate; // DCache state machine value
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sc_out<sc_uint<2>> o_dstate; // DCache state machine value
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sc_out<sc_uint<2>> o_cstate; // cachetop state machine value
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sc_out<sc_uint<2>> o_cstate; // cachetop state machine value
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void comb();
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void comb();
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void registers();
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void registers();
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SC_HAS_PROCESS(CacheTop);
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SC_HAS_PROCESS(CacheTop);
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CacheTop(sc_module_name name_);
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CacheTop(sc_module_name name_);
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virtual ~CacheTop();
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virtual ~CacheTop();
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void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
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void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
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private:
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private:
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static const uint8_t State_Idle = 0;
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static const uint8_t State_Idle = 0;
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static const uint8_t State_IMem = 1;
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static const uint8_t State_IMem = 1;
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static const uint8_t State_DMem = 2;
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static const uint8_t State_DMem = 2;
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struct CacheOutputType {
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struct CacheOutputType {
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sc_signal<bool> req_mem_valid;
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sc_signal<bool> req_mem_valid;
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sc_signal<bool> req_mem_write;
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sc_signal<bool> req_mem_write;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> req_mem_addr;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> req_mem_addr;
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sc_signal<sc_uint<BUS_DATA_BYTES>> req_mem_strob;
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sc_signal<sc_uint<BUS_DATA_BYTES>> req_mem_strob;
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sc_signal<sc_uint<BUS_DATA_WIDTH>> req_mem_wdata;
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sc_signal<sc_uint<BUS_DATA_WIDTH>> req_mem_wdata;
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};
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};
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struct RegistersType {
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struct RegistersType {
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sc_signal<sc_uint<2>> state;
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sc_signal<sc_uint<2>> state;
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} v, r;
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} v, r;
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CacheOutputType i, d;
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CacheOutputType i, d;
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// Memory Control interface:
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// Memory Control interface:
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sc_signal<bool> w_ctrl_resp_mem_data_valid;
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sc_signal<bool> w_ctrl_resp_mem_data_valid;
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sc_signal<sc_uint<BUS_DATA_WIDTH>> wb_ctrl_resp_mem_data;
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sc_signal<sc_uint<BUS_DATA_WIDTH>> wb_ctrl_resp_mem_data;
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sc_signal<bool> w_ctrl_req_ready;
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sc_signal<bool> w_ctrl_req_ready;
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// Memory Data interface:
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// Memory Data interface:
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sc_signal<bool> w_data_resp_mem_data_valid;
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sc_signal<bool> w_data_resp_mem_data_valid;
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sc_signal<sc_uint<BUS_DATA_WIDTH>> wb_data_resp_mem_data;
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sc_signal<sc_uint<BUS_DATA_WIDTH>> wb_data_resp_mem_data;
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sc_signal<bool> w_data_req_ready;
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sc_signal<bool> w_data_req_ready;
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ICache *i0;
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ICache *i0;
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DCache *d0;
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DCache *d0;
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#ifdef DBG_ICACHE_TB
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#ifdef DBG_ICACHE_TB
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ICache_tb *i0_tb;
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ICache_tb *i0_tb;
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#endif
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#endif
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};
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};
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} // namespace debugger
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} // namespace debugger
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#endif // __DEBUGGER_RIVERLIB_CACHE_TOP_H__
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#endif // __DEBUGGER_RIVERLIB_CACHE_TOP_H__
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