/**
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/*
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* @file
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* Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
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* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
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*
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* @author Sergey Khabarov - sergeykhbr@gmail.com
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* Licensed under the Apache License, Version 2.0 (the "License");
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* @brief Branch predictor.
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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*/
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#ifndef __DEBUGGER_RIVERLIB_BR_PREDIC_H__
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#ifndef __DEBUGGER_RIVERLIB_BR_PREDIC_H__
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#define __DEBUGGER_RIVERLIB_BR_PREDIC_H__
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#define __DEBUGGER_RIVERLIB_BR_PREDIC_H__
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#include <systemc.h>
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#include <systemc.h>
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#include "../river_cfg.h"
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#include "../river_cfg.h"
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namespace debugger {
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namespace debugger {
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SC_MODULE(BranchPredictor) {
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SC_MODULE(BranchPredictor) {
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sc_in<bool> i_clk; // CPU clock
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sc_in<bool> i_clk; // CPU clock
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sc_in<bool> i_nrst; // Reset. Active LOW.
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sc_in<bool> i_nrst; // Reset. Active LOW.
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sc_in<bool> i_req_mem_fire; // Memory request was accepted
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sc_in<bool> i_req_mem_fire; // Memory request was accepted
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sc_in<bool> i_resp_mem_valid; // Memory response from ICache is valid
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sc_in<bool> i_resp_mem_valid; // Memory response from ICache is valid
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sc_in<sc_uint<BUS_ADDR_WIDTH>> i_resp_mem_addr; // Memory response address
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sc_in<sc_uint<BUS_ADDR_WIDTH>> i_resp_mem_addr; // Memory response address
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sc_in<sc_uint<32>> i_resp_mem_data; // Memory response value
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sc_in<sc_uint<32>> i_resp_mem_data; // Memory response value
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sc_in<bool> i_f_predic_miss; // Fetch modul detects deviation between predicted and valid pc.
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sc_in<bool> i_f_predic_miss; // Fetch modul detects deviation between predicted and valid pc.
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sc_in<sc_uint<32>> i_e_npc; // Valid instruction value awaited by 'Executor'
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sc_in<sc_uint<32>> i_e_npc; // Valid instruction value awaited by 'Executor'
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sc_in<sc_uint<RISCV_ARCH>> i_ra; // Return address register value
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sc_in<sc_uint<RISCV_ARCH>> i_ra; // Return address register value
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sc_out<sc_uint<32>> o_npc_predict; // Predicted next instruction address
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sc_out<sc_uint<32>> o_npc_predict; // Predicted next instruction address
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void comb();
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void comb();
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void registers();
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void registers();
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SC_HAS_PROCESS(BranchPredictor);
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SC_HAS_PROCESS(BranchPredictor);
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BranchPredictor(sc_module_name name_);
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BranchPredictor(sc_module_name name_);
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void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
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void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
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private:
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private:
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struct RegistersType {
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struct RegistersType {
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> npc;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> npc;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> resp_mem_addr;
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sc_signal<sc_uint<32>> resp_mem_data;
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} v, r;
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} v, r;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> wb_npc;
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sc_uint<BUS_ADDR_WIDTH> wb_npc;
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};
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};
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} // namespace debugger
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} // namespace debugger
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#endif // __DEBUGGER_RIVERLIB_BR_PREDIC_H__
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#endif // __DEBUGGER_RIVERLIB_BR_PREDIC_H__
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