/**
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/**
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* @file
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* @file
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* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
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* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
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* @author Sergey Khabarov - sergeykhbr@gmail.com
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* @author Sergey Khabarov - sergeykhbr@gmail.com
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* @brief CPU Instruction Execution stage.
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* @brief CPU Instruction Execution stage.
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*/
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*/
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#ifndef __DEBUGGER_RIVERLIB_EXECUTE_H__
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#ifndef __DEBUGGER_RIVERLIB_EXECUTE_H__
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#define __DEBUGGER_RIVERLIB_EXECUTE_H__
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#define __DEBUGGER_RIVERLIB_EXECUTE_H__
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#include <systemc.h>
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#include <systemc.h>
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#include "../river_cfg.h"
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#include "../river_cfg.h"
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#include "arith/int_div.h"
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#include "arith/int_div.h"
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#include "arith/int_mul.h"
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#include "arith/int_mul.h"
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#include "arith/shift.h"
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#include "arith/shift.h"
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namespace debugger {
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namespace debugger {
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SC_MODULE(InstrExecute) {
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SC_MODULE(InstrExecute) {
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sc_in<bool> i_clk;
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sc_in<bool> i_clk;
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sc_in<bool> i_nrst; // Reset active LOW
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sc_in<bool> i_nrst; // Reset active LOW
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sc_in<bool> i_pipeline_hold; // Hold execution by any reason
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sc_in<bool> i_pipeline_hold; // Hold execution by any reason
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sc_in<bool> i_d_valid; // Decoded instruction is valid
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sc_in<bool> i_d_valid; // Decoded instruction is valid
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sc_in<sc_uint<BUS_ADDR_WIDTH>> i_d_pc; // Instruction pointer on decoded instruction
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sc_in<sc_uint<BUS_ADDR_WIDTH>> i_d_pc; // Instruction pointer on decoded instruction
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sc_in<sc_uint<32>> i_d_instr; // Decoded instruction value
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sc_in<sc_uint<32>> i_d_instr; // Decoded instruction value
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sc_in<bool> i_wb_done; // write back done (Used to clear hazardness)
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sc_in<bool> i_wb_done; // write back done (Used to clear hazardness)
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sc_in<bool> i_memop_store; // Store to memory operation
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sc_in<bool> i_memop_store; // Store to memory operation
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sc_in<bool> i_memop_load; // Load from memoru operation
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sc_in<bool> i_memop_load; // Load from memoru operation
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sc_in<bool> i_memop_sign_ext; // Load memory value with sign extending
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sc_in<bool> i_memop_sign_ext; // Load memory value with sign extending
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sc_in<sc_uint<2>> i_memop_size; // Memory transaction size
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sc_in<sc_uint<2>> i_memop_size; // Memory transaction size
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sc_in<bool> i_unsigned_op; // Unsigned operands
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sc_in<bool> i_unsigned_op; // Unsigned operands
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sc_in<bool> i_rv32; // 32-bits instruction
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sc_in<bool> i_rv32; // 32-bits instruction
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sc_in<sc_bv<ISA_Total>> i_isa_type; // Type of the instruction's structure (ISA spec.)
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sc_in<sc_bv<ISA_Total>> i_isa_type; // Type of the instruction's structure (ISA spec.)
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sc_in<sc_bv<Instr_Total>> i_ivec; // One pulse per supported instruction.
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sc_in<sc_bv<Instr_Total>> i_ivec; // One pulse per supported instruction.
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sc_in<bool> i_ie; // Interrupt enable bit
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sc_in<bool> i_ie; // Interrupt enable bit
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sc_in<sc_uint<BUS_ADDR_WIDTH>> i_mtvec; // Interrupt descriptor table
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sc_in<sc_uint<BUS_ADDR_WIDTH>> i_mtvec; // Interrupt descriptor table
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sc_in<sc_uint<2>> i_mode; // Current processor mode
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sc_in<sc_uint<2>> i_mode; // Current processor mode
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sc_in<bool> i_break_mode; // Behaviour on EBREAK instruction: 0 = halt; 1 = generate trap
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sc_in<bool> i_break_mode; // Behaviour on EBREAK instruction: 0 = halt; 1 = generate trap
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sc_in<bool> i_unsup_exception; // Unsupported instruction exception
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sc_in<bool> i_unsup_exception; // Unsupported instruction exception
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sc_in<bool> i_ext_irq; // External interrupt from PLIC (todo: timer & software interrupts)
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sc_in<bool> i_ext_irq; // External interrupt from PLIC (todo: timer & software interrupts)
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sc_in<bool> i_dport_npc_write; // Write npc value from debug port
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sc_in<bool> i_dport_npc_write; // Write npc value from debug port
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sc_in<sc_uint<BUS_ADDR_WIDTH>> i_dport_npc; // Debug port npc value to write
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sc_in<sc_uint<BUS_ADDR_WIDTH>> i_dport_npc; // Debug port npc value to write
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sc_out<sc_uint<5>> o_radr1; // Integer register index 1
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sc_out<sc_uint<5>> o_radr1; // Integer register index 1
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sc_in<sc_uint<RISCV_ARCH>> i_rdata1; // Integer register value 1
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sc_in<sc_uint<RISCV_ARCH>> i_rdata1; // Integer register value 1
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sc_out<sc_uint<5>> o_radr2; // Integer register index 2
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sc_out<sc_uint<5>> o_radr2; // Integer register index 2
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sc_in<sc_uint<RISCV_ARCH>> i_rdata2; // Integer register value 2
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sc_in<sc_uint<RISCV_ARCH>> i_rdata2; // Integer register value 2
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sc_out<sc_uint<5>> o_res_addr; // Address to store result of the instruction (0=do not store)
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sc_out<sc_uint<5>> o_res_addr; // Address to store result of the instruction (0=do not store)
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sc_out<sc_uint<RISCV_ARCH>> o_res_data; // Value to store
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sc_out<sc_uint<RISCV_ARCH>> o_res_data; // Value to store
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sc_out<bool> o_pipeline_hold; // Hold pipeline while 'writeback' not done or multi-clock instruction.
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sc_out<bool> o_pipeline_hold; // Hold pipeline while 'writeback' not done or multi-clock instruction.
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sc_out<bool> o_xret; // XRET instruction: MRET, URET or other.
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sc_out<bool> o_xret; // XRET instruction: MRET, URET or other.
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sc_out<sc_uint<12>> o_csr_addr; // CSR address. 0 if not a CSR instruction with xret signals mode switching
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sc_out<sc_uint<12>> o_csr_addr; // CSR address. 0 if not a CSR instruction with xret signals mode switching
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sc_out<bool> o_csr_wena; // Write new CSR value
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sc_out<bool> o_csr_wena; // Write new CSR value
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sc_in<sc_uint<RISCV_ARCH>> i_csr_rdata; // CSR current value
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sc_in<sc_uint<RISCV_ARCH>> i_csr_rdata; // CSR current value
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sc_out<sc_uint<RISCV_ARCH>> o_csr_wdata; // CSR new value
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sc_out<sc_uint<RISCV_ARCH>> o_csr_wdata; // CSR new value
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sc_out<bool> o_trap_ena; // Trap occurs pulse
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sc_out<bool> o_trap_ena; // Trap occurs pulse
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sc_out<sc_uint<5>> o_trap_code; // bit[4] : 1=interrupt; 0=exception; bits[3:0]=code
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sc_out<sc_uint<5>> o_trap_code; // bit[4] : 1=interrupt; 0=exception; bits[3:0]=code
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sc_out<sc_uint<BUS_ADDR_WIDTH>> o_trap_pc; // trap on pc
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sc_out<sc_uint<BUS_ADDR_WIDTH>> o_trap_pc; // trap on pc
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sc_out<bool> o_memop_sign_ext; // Load data with sign extending
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sc_out<bool> o_memop_sign_ext; // Load data with sign extending
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sc_out<bool> o_memop_load; // Load data instruction
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sc_out<bool> o_memop_load; // Load data instruction
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sc_out<bool> o_memop_store; // Store data instruction
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sc_out<bool> o_memop_store; // Store data instruction
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sc_out<sc_uint<2>> o_memop_size; // 0=1bytes; 1=2bytes; 2=4bytes; 3=8bytes
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sc_out<sc_uint<2>> o_memop_size; // 0=1bytes; 1=2bytes; 2=4bytes; 3=8bytes
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sc_out<sc_uint<BUS_ADDR_WIDTH>> o_memop_addr;// Memory access address
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sc_out<sc_uint<BUS_ADDR_WIDTH>> o_memop_addr;// Memory access address
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sc_out<bool> o_valid; // Output is valid
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sc_out<bool> o_valid; // Output is valid
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sc_out<sc_uint<BUS_ADDR_WIDTH>> o_pc; // Valid instruction pointer
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sc_out<sc_uint<BUS_ADDR_WIDTH>> o_pc; // Valid instruction pointer
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sc_out<sc_uint<BUS_ADDR_WIDTH>> o_npc; // Next instruction pointer. Next decoded pc must match to this value or will be ignored.
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sc_out<sc_uint<BUS_ADDR_WIDTH>> o_npc; // Next instruction pointer. Next decoded pc must match to this value or will be ignored.
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sc_out<sc_uint<32>> o_instr; // Valid instruction value
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sc_out<sc_uint<32>> o_instr; // Valid instruction value
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sc_out<bool> o_breakpoint; // ebreak instruction
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sc_out<bool> o_breakpoint; // ebreak instruction
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sc_out<bool> o_call; // CALL pseudo instruction detected
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sc_out<bool> o_call; // CALL pseudo instruction detected
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sc_out<bool> o_ret; // RET pseudoinstruction detected
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sc_out<bool> o_ret; // RET pseudoinstruction detected
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void comb();
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void comb();
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void registers();
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void registers();
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SC_HAS_PROCESS(InstrExecute);
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SC_HAS_PROCESS(InstrExecute);
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InstrExecute(sc_module_name name_);
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InstrExecute(sc_module_name name_);
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virtual ~InstrExecute();
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virtual ~InstrExecute();
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void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
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void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
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private:
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private:
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enum EMultiCycleInstruction {
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enum EMultiCycleInstruction {
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Multi_MUL,
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Multi_MUL,
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Multi_DIV,
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Multi_DIV,
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Multi_Total
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Multi_Total
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};
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};
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struct multi_arith_type {
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struct multi_arith_type {
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sc_signal<sc_uint<RISCV_ARCH>> arr[Multi_Total];
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sc_signal<sc_uint<RISCV_ARCH>> arr[Multi_Total];
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};
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};
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struct RegistersType {
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struct RegistersType {
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sc_signal<bool> d_valid; // Valid decoded instruction latch
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sc_signal<bool> d_valid; // Valid decoded instruction latch
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> pc;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> pc;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> npc;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> npc;
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sc_signal<sc_uint<32>> instr;
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sc_signal<sc_uint<32>> instr;
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sc_uint<5> res_addr;
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sc_uint<5> res_addr;
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sc_signal<sc_uint<RISCV_ARCH>> res_val;
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sc_signal<sc_uint<RISCV_ARCH>> res_val;
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sc_signal<bool> memop_load;
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sc_signal<bool> memop_load;
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sc_signal<bool> memop_store;
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sc_signal<bool> memop_store;
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bool memop_sign_ext;
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bool memop_sign_ext;
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sc_uint<2> memop_size;
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sc_uint<2> memop_size;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> memop_addr;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> memop_addr;
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sc_signal<sc_uint<5>> multi_res_addr; // latched output reg. address while multi-cycle instruction
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sc_signal<sc_uint<5>> multi_res_addr; // latched output reg. address while multi-cycle instruction
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> multi_pc; // latched pc-value while multi-cycle instruction
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> multi_pc; // latched pc-value while multi-cycle instruction
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> multi_npc; // latched npc-value while multi-cycle instruction
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> multi_npc; // latched npc-value while multi-cycle instruction
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sc_signal<sc_uint<32>> multi_instr; // Multi-cycle instruction is under processing
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sc_signal<sc_uint<32>> multi_instr; // Multi-cycle instruction is under processing
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sc_signal<bool> multi_ena[Multi_Total]; // Enable pulse for Operation that takes more than 1 clock
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sc_signal<bool> multi_ena[Multi_Total]; // Enable pulse for Operation that takes more than 1 clock
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sc_signal<bool> multi_rv32; // Long operation with 32-bits operands
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sc_signal<bool> multi_rv32; // Long operation with 32-bits operands
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sc_signal<bool> multi_unsigned; // Long operation with unsiged operands
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sc_signal<bool> multi_unsigned; // Long operation with unsiged operands
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sc_signal<bool> multi_residual_high; // Flag for Divider module: 0=divsion output; 1=residual output
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sc_signal<bool> multi_residual_high; // Flag for Divider module: 0=divsion output; 1=residual output
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// Flag for multiplier: 0=usual; 1=get high bits
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// Flag for multiplier: 0=usual; 1=get high bits
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sc_signal<bool> multiclock_ena;
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sc_signal<bool> multiclock_ena;
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sc_signal<sc_uint<RISCV_ARCH>> multi_a1; // Multi-cycle operand 1
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sc_signal<sc_uint<RISCV_ARCH>> multi_a1; // Multi-cycle operand 1
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sc_signal<sc_uint<RISCV_ARCH>> multi_a2; // Multi-cycle operand 2
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sc_signal<sc_uint<RISCV_ARCH>> multi_a2; // Multi-cycle operand 2
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sc_signal<sc_uint<5>> hazard_addr0; // Updated register address on previous step
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sc_signal<sc_uint<5>> hazard_addr0; // Updated register address on previous step
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sc_signal<sc_uint<5>> hazard_addr1; // Updated register address on pre-previous step
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sc_signal<sc_uint<5>> hazard_addr1; // Updated register address on pre-previous step
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sc_signal<sc_uint<2>> hazard_depth; // Number of modificated registers that wasn't done yet
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sc_signal<sc_uint<2>> hazard_depth; // Number of modificated registers that wasn't done yet
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sc_signal<bool> ext_irq_pulser; // Form 1 clock pulse from strob
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sc_signal<bool> ext_irq_pulser; // Form 1 clock pulse from strob
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sc_signal<bool> trap_ena; // Trap occur, switch mode
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sc_signal<bool> trap_ena; // Trap occur, switch mode
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sc_signal<bool> breakpoint;
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sc_signal<bool> breakpoint;
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sc_uint<5> trap_code_waiting; // To avoid multi-cycle instruction collision
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sc_uint<5> trap_code_waiting; // To avoid multi-cycle instruction collision
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sc_signal<sc_uint<5>> trap_code; // bit[4] : 1 = interrupt; 0 = exception
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sc_signal<sc_uint<5>> trap_code; // bit[4] : 1 = interrupt; 0 = exception
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// bit[3:0] : trap code
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// bit[3:0] : trap code
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> trap_pc; // pc that caused a trap
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> trap_pc; // pc that caused a trap
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sc_signal<bool> call;
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sc_signal<bool> call;
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sc_signal<bool> ret;
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sc_signal<bool> ret;
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} v, r;
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} v, r;
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sc_signal<bool> w_hazard_detected;
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sc_signal<bool> w_hazard_detected;
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multi_arith_type wb_arith_res;
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multi_arith_type wb_arith_res;
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sc_signal<bool> w_arith_valid[Multi_Total];
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sc_signal<bool> w_arith_valid[Multi_Total];
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sc_signal<bool> w_arith_busy[Multi_Total];
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sc_signal<bool> w_arith_busy[Multi_Total];
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bool w_interrupt;
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bool w_interrupt;
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bool w_exception;
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bool w_exception;
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bool w_exception_store;
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bool w_exception_store;
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bool w_exception_load;
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bool w_exception_load;
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bool w_exception_xret;
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bool w_exception_xret;
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sc_uint<5> wb_exception_code;
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sc_uint<5> wb_exception_code;
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sc_signal<sc_uint<RISCV_ARCH>> wb_shifter_a1; // Shifters operand 1
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sc_signal<sc_uint<RISCV_ARCH>> wb_shifter_a1; // Shifters operand 1
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sc_signal<sc_uint<6>> wb_shifter_a2; // Shifters operand 2
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sc_signal<sc_uint<6>> wb_shifter_a2; // Shifters operand 2
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sc_signal<sc_uint<RISCV_ARCH>> wb_sll;
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sc_signal<sc_uint<RISCV_ARCH>> wb_sll;
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sc_signal<sc_uint<RISCV_ARCH>> wb_sllw;
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sc_signal<sc_uint<RISCV_ARCH>> wb_sllw;
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sc_signal<sc_uint<RISCV_ARCH>> wb_srl;
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sc_signal<sc_uint<RISCV_ARCH>> wb_srl;
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sc_signal<sc_uint<RISCV_ARCH>> wb_srlw;
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sc_signal<sc_uint<RISCV_ARCH>> wb_srlw;
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sc_signal<sc_uint<RISCV_ARCH>> wb_sra;
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sc_signal<sc_uint<RISCV_ARCH>> wb_sra;
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sc_signal<sc_uint<RISCV_ARCH>> wb_sraw;
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sc_signal<sc_uint<RISCV_ARCH>> wb_sraw;
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IntMul *mul0;
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IntMul *mul0;
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IntDiv *div0;
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IntDiv *div0;
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Shifter *sh0;
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Shifter *sh0;
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};
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};
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} // namespace debugger
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} // namespace debugger
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#endif // __DEBUGGER_RIVERLIB_EXECUTE_H__
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#endif // __DEBUGGER_RIVERLIB_EXECUTE_H__
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