-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File: ex_stage.vhd
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-- File: ex_stage.vhd
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-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
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-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
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-- Created: 2006-11-29
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-- Created: 2006-11-29
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-- Last updated: 2006-11-29
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-- Last updated: 2006-11-29
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-- Description:
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-- Description:
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-- Barrel shifter
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-- Barrel shifter
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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use IEEE.NUMERIC_STD.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use ieee.STD_LOGIC_UNSIGNED.all;
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use ieee.STD_LOGIC_UNSIGNED.all;
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use WORK.RISE_PACK.all;
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use WORK.RISE_PACK.all;
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use WORK.RISE_PACK_SPECIFIC.all;
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use WORK.RISE_PACK_SPECIFIC.all;
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library UNISIM;
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library UNISIM;
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use UNISIM.VComponents.all;
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use UNISIM.VComponents.all;
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use WORK.RISE_PACK.all;
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use WORK.RISE_PACK.all;
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use work.RISE_PACK_SPECIFIC.all;
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use work.RISE_PACK_SPECIFIC.all;
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entity barrel_shifter is
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entity barrel_shifter is
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port (reg_a : in std_logic_vector(15 downto 0);
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port (reg_a : in std_logic_vector(15 downto 0);
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reg_b : in REGISTER_T;
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reg_b : in REGISTER_T;
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left : in std_logic;
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left : in std_logic;
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arithmetic : in std_logic;
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arithmetic : in std_logic;
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reg_q : out REGISTER_T);
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reg_q : out REGISTER_T);
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end barrel_shifter;
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end barrel_shifter;
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architecture barrel_shifter_rtl of barrel_shifter is
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architecture barrel_shifter_rtl of barrel_shifter is
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signal shifter_value : REGISTER_T;
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signal shifter_value : REGISTER_T;
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signal mult_b_in : std_logic_vector(17 downto 0);
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signal mult_b_in : std_logic_vector(17 downto 0);
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signal mult_a_in : std_logic_vector(17 downto 0);
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signal mult_a_in : std_logic_vector(17 downto 0);
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signal mult_p_out : std_logic_vector(35 downto 0);
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signal mult_p_out : std_logic_vector(35 downto 0);
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component MULT18X18
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component MULT18X18
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port (A : in std_logic_vector(17 downto 0);
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port (A : in std_logic_vector(17 downto 0);
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B : in std_logic_vector(17 downto 0);
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B : in std_logic_vector(17 downto 0);
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P : out std_logic_vector(35 downto 0)
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P : out std_logic_vector(35 downto 0)
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);
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);
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end component;
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end component;
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function reverse_register (reg_in : REGISTER_T) return REGISTER_T is
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function reverse_register (reg_in : REGISTER_T) return REGISTER_T is
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variable reversed : REGISTER_T;
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variable reversed : REGISTER_T;
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begin
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begin
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for i in 0 to (ARCHITECTURE_WIDTH - 1) loop
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for i in 0 to (ARCHITECTURE_WIDTH - 1) loop
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reversed(i) := reg_in (ARCHITECTURE_WIDTH - 1 - i);
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reversed(i) := reg_in (ARCHITECTURE_WIDTH - 1 - i);
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end loop;
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end loop;
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return reversed;
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return reversed;
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end reverse_register;
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end reverse_register;
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begin
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begin
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MULT18X18_inst : MULT18X18
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MULT18X18_inst : MULT18X18
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port map (
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port map (
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P => mult_p_out, -- 36-bit multiplier output
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P => mult_p_out, -- 36-bit multiplier output
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A => mult_b_in, -- 18-bit multiplier input
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A => mult_b_in, -- 18-bit multiplier input
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B => mult_a_in -- 18-bit multiplier input
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B => mult_a_in -- 18-bit multiplier input
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);
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);
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process(reg_b)
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process(reg_b)
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variable index : integer range 0 to 15;
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variable index : integer range 0 to 15;
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begin
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begin
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shifter_value <= x"0000";
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shifter_value <= x"0000";
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index := to_integer(ieee.numeric_std.unsigned(reg_b(3 downto 0)));
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index := to_integer(ieee.numeric_std.unsigned(reg_b(3 downto 0)));
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shifter_value(index) <= '1';
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shifter_value(index) <= '1';
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end process;
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end process;
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process(shifter_value, reg_a, left)
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process(shifter_value, reg_a, left)
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begin
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begin
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mult_b_in <= "00" & shifter_value;
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mult_b_in <= "00" & shifter_value;
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if left = '1' then
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if left = '1' then
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mult_a_in <= "00" & reg_a;
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mult_a_in <= "00" & reg_a;
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else
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else
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mult_a_in <= "00" & reverse_register(reg_a);
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mult_a_in <= "00" & reverse_register(reg_a);
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end if;
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end if;
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end process;
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end process;
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process(mult_p_out, left, arithmetic, reg_a, reg_b)
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process(mult_p_out, left, arithmetic, reg_a, reg_b)
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begin
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begin
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if left = '1' then
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if left = '1' then
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reg_q <= mult_p_out(ARCHITECTURE_WIDTH - 1 downto 0);
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reg_q <= mult_p_out(ARCHITECTURE_WIDTH - 1 downto 0);
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else
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else
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reg_q <= reverse_register(mult_p_out(ARCHITECTURE_WIDTH - 1 downto 0));
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reg_q <= reverse_register(mult_p_out(ARCHITECTURE_WIDTH - 1 downto 0));
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if arithmetic = '1' and reg_a(ARCHITECTURE_WIDTH - 1) = '1' then
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if arithmetic = '1' and reg_a(ARCHITECTURE_WIDTH - 1) = '1' then
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for index in 0 to ARCHITECTURE_WIDTH - 1 loop
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for index in 0 to ARCHITECTURE_WIDTH - 1 loop
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if index < reg_b then
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if index < reg_b then
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reg_q(ARCHITECTURE_WIDTH - 1 - index) <= '1';
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reg_q(ARCHITECTURE_WIDTH - 1 - index) <= '1';
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end if;
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end if;
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end loop;
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end loop;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end architecture;
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end architecture;
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