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-- File: if_stage.vhd
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-- File: if_stage.vhd
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-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
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-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
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-- Created: 2006-11-29
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-- Created: 2006-11-29
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-- Last updated: 2006-11-29
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-- Last updated: 2006-11-29
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-- Description:
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-- Description:
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-- Instruction fetch stage
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-- Instruction fetch stage
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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use IEEE.NUMERIC_STD.all;
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use WORK.RISE_PACK.all;
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use WORK.RISE_PACK.all;
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use WORK.RISE_PACK_SPECIFIC.all;
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use WORK.RISE_PACK_SPECIFIC.all;
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entity if_stage is
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entity if_stage is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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if_id_register : out IF_ID_REGISTER_T;
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if_id_register : out IF_ID_REGISTER_T;
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branch : in std_logic;
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branch : in std_logic;
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branch_target : in PC_REGISTER_T;
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branch_target : in PC_REGISTER_T;
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clear_in : in std_logic;
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clear_in : in std_logic;
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stall_in : in std_logic;
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stall_in : in std_logic;
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pc : in PC_REGISTER_T;
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pc : in PC_REGISTER_T;
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pc_next : out PC_REGISTER_T;
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pc_next : out PC_REGISTER_T;
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imem_addr : out MEM_ADDR_T;
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imem_addr : out MEM_ADDR_T;
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imem_data : in MEM_DATA_T);
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imem_data : in MEM_DATA_T);
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end if_stage;
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end if_stage;
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-- This is a simple hardcoded IF unit for the RISE processor. It does not
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-- This is a simple hardcoded IF unit for the RISE processor. It does not
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-- use the memory and contains a hardcoded program.
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-- use the memory and contains a hardcoded program.
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architecture if_state_behavioral of if_stage is
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architecture if_state_behavioral of if_stage is
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signal if_id_register_int : IF_ID_REGISTER_T := (others => (others => '0'));
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signal if_id_register_int : IF_ID_REGISTER_T := (others => (others => '0'));
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signal if_id_register_next : IF_ID_REGISTER_T := (others => (others => '0'));
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signal if_id_register_next : IF_ID_REGISTER_T := (others => (others => '0'));
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signal cur_pc : PC_REGISTER_T;
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signal cur_pc : PC_REGISTER_T;
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component pgrom
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component pgrom
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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addr : in std_logic_vector(15 downto 0);
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addr : in std_logic_vector(15 downto 0);
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data : out std_logic_vector(15 downto 0)
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data : out std_logic_vector(15 downto 0)
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);
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);
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end component;
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end component;
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begin
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begin
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if_id_register <= if_id_register_int;
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if_id_register <= if_id_register_int;
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cur_pc <= pc when branch = '0' else branch_target;
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cur_pc <= pc when branch = '0' else branch_target;
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process (clk, reset, clear_in)
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process (clk, reset, clear_in)
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begin
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begin
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if reset = '0' then
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if reset = '0' then
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if_id_register_int.pc <= PC_RESET_VECTOR;
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if_id_register_int.pc <= PC_RESET_VECTOR;
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if_id_register_int.ir <= (others => '0');
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if_id_register_int.ir <= (others => '0');
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elsif clk'event and clk = '1' then
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elsif clk'event and clk = '1' then
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if stall_in = '0' then
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if stall_in = '0' then
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if_id_register_int <= if_id_register_next;
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if_id_register_int <= if_id_register_next;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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process (reset, branch, branch_target, cur_pc, stall_in)
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process (reset, branch, branch_target, cur_pc, stall_in)
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begin
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begin
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if reset = '0' then
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if reset = '0' then
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if_id_register_next.pc <= PC_RESET_VECTOR;
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if_id_register_next.pc <= PC_RESET_VECTOR;
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pc_next <= PC_RESET_VECTOR;
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pc_next <= PC_RESET_VECTOR;
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else
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else
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if_id_register_next.pc <= cur_pc;
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if_id_register_next.pc <= cur_pc;
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if stall_in = '0' then
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if stall_in = '0' then
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pc_next <= std_logic_vector(unsigned(cur_pc) + 2);
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pc_next <= std_logic_vector(unsigned(cur_pc) + 2);
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else
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else
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pc_next <= cur_pc;
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pc_next <= cur_pc;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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pgrom_ut : pgrom port map(
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pgrom_ut : pgrom port map(
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clk => clk,
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clk => clk,
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addr => cur_pc,
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addr => cur_pc,
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data => if_id_register_next.ir
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data => if_id_register_next.ir
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);
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);
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end if_state_behavioral;
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end if_state_behavioral;
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