-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File: rise.vhd
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-- File: rise.vhd
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-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
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-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
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-- Created: 2006-11-29
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-- Created: 2006-11-29
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-- Last updated: 2006-11-29
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-- Last updated: 2006-11-29
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-- Description:
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-- Description:
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-- Top-Level entity of RISE CPU
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-- Top-Level entity of RISE CPU
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use WORK.RISE_PACK.all;
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use WORK.RISE_PACK.all;
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use work.RISE_PACK_SPECIFIC.all;
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use work.RISE_PACK_SPECIFIC.all;
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entity rise is
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entity rise is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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-- uart
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-- uart
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rx : in std_logic;
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rx : in std_logic;
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tx : out std_logic);
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tx : out std_logic);
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end rise;
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end rise;
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architecture rise_rtl of rise is
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architecture rise_rtl of rise is
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-- if_stage signals
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-- if_stage signals
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signal if_id_register_sig : IF_ID_REGISTER_T;
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signal if_id_register_sig : IF_ID_REGISTER_T;
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signal branch_sig : std_logic;
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signal branch_sig : std_logic;
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signal branch_target_sig : PC_REGISTER_T;
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signal branch_target_sig : PC_REGISTER_T;
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signal stall_in_if_sig : std_logic;
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signal stall_in_if_sig : std_logic;
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signal clear_in_if_sig : std_logic;
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signal clear_in_if_sig : std_logic;
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signal pc_if_sig : PC_REGISTER_T;
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signal pc_if_sig : PC_REGISTER_T;
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signal pc_next_if_sig : PC_REGISTER_T;
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signal pc_next_if_sig : PC_REGISTER_T;
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signal imem_addr_sig : MEM_ADDR_T;
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signal imem_addr_sig : MEM_ADDR_T;
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signal imem_data_sig : MEM_DATA_T;
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signal imem_data_sig : MEM_DATA_T;
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-- id_stage signals
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-- id_stage signals
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signal id_ex_register_sig : ID_EX_REGISTER_T;
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signal id_ex_register_sig : ID_EX_REGISTER_T;
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signal rx_addr_sig : REGISTER_ADDR_T;
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signal rx_addr_sig : REGISTER_ADDR_T;
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signal ry_addr_sig : REGISTER_ADDR_T;
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signal ry_addr_sig : REGISTER_ADDR_T;
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signal rz_addr_sig : REGISTER_ADDR_T;
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signal rz_addr_sig : REGISTER_ADDR_T;
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signal rx_sig : REGISTER_T;
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signal rx_sig : REGISTER_T;
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signal ry_sig : REGISTER_T;
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signal ry_sig : REGISTER_T;
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signal rz_sig : REGISTER_T;
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signal rz_sig : REGISTER_T;
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signal sr_id_sig : SR_REGISTER_T;
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signal sr_id_sig : SR_REGISTER_T;
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signal lock_register_sig : LOCK_REGISTER_T;
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signal lock_register_sig : LOCK_REGISTER_T;
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signal stall_in_id_sig : std_logic;
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signal stall_in_id_sig : std_logic;
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signal stall_out_id_sig : std_logic;
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signal stall_out_id_sig : std_logic;
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signal clear_in_id_sig : std_logic;
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signal clear_in_id_sig : std_logic;
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-- ex_stage signals
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-- ex_stage signals
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signal ex_mem_register_sig : EX_MEM_REGISTER_T;
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signal ex_mem_register_sig : EX_MEM_REGISTER_T;
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signal stall_in_ex_sig : std_logic;
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signal stall_in_ex_sig : std_logic;
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signal clear_in_ex_sig : std_logic;
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signal clear_in_ex_sig : std_logic;
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signal clear_out_ex_sig : std_logic;
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signal clear_out_ex_sig : std_logic;
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signal clear_locks_sig : std_logic;
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signal clear_locks_sig : std_logic;
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-- mem_stage signals
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-- mem_stage signals
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signal mem_wb_register_sig : MEM_WB_REGISTER_T;
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signal mem_wb_register_sig : MEM_WB_REGISTER_T;
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signal dmem_addr_sig : MEM_ADDR_T;
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signal dmem_addr_sig : MEM_ADDR_T;
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signal dmem_data_in_sig : MEM_DATA_T;
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signal dmem_data_in_sig : MEM_DATA_T;
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signal dmem_data_out_sig : MEM_DATA_T;
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signal dmem_data_out_sig : MEM_DATA_T;
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signal stall_out_mem_sig : std_logic;
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signal stall_out_mem_sig : std_logic;
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signal clear_in_mem_sig : std_logic;
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signal clear_in_mem_sig : std_logic;
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signal clear_out_mem_sig : std_logic;
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signal clear_out_mem_sig : std_logic;
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-- wb_stage signals
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-- wb_stage signals
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signal dreg_addr_sig : REGISTER_ADDR_T;
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signal dreg_addr_sig : REGISTER_ADDR_T;
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signal dreg_sig : REGISTER_T;
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signal dreg_sig : REGISTER_T;
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signal dreg_enable_sig : std_logic;
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signal dreg_enable_sig : std_logic;
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signal lr_sig : PC_REGISTER_T;
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signal lr_sig : PC_REGISTER_T;
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signal lr_enable_sig : std_logic;
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signal lr_enable_sig : std_logic;
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signal sr_wb_sig : SR_REGISTER_T;
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signal sr_wb_sig : SR_REGISTER_T;
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signal sr_enable_sig : std_logic;
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signal sr_enable_sig : std_logic;
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signal clear_out_wb_sig : std_logic;
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signal clear_out_wb_sig : std_logic;
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-- imem signals
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-- imem signals
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signal data_in_imem_sig : MEM_DATA_T; -- unused at the moment
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signal data_in_imem_sig : MEM_DATA_T; -- unused at the moment
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signal wr_enable_imem_sig : std_logic; -- unused at the moment
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signal wr_enable_imem_sig : std_logic; -- unused at the moment
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-- dmem signals
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-- dmem signals
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signal wr_enable_dmem_sig : std_logic;
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signal wr_enable_dmem_sig : std_logic;
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signal dmem_rxd_sig : std_logic;
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signal dmem_rxd_sig : std_logic;
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signal dmem_txd_sig : std_logic;
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signal dmem_txd_sig : std_logic;
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-- rlu signals
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-- rlu signals
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signal clear_lock0_sig : std_logic := '0';
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signal clear_lock0_sig : std_logic := '0';
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signal clear_lock_addr0_sig : REGISTER_ADDR_T;
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signal clear_lock_addr0_sig : REGISTER_ADDR_T;
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signal clear_lock1_sig : std_logic := '0';
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signal clear_lock1_sig : std_logic := '0';
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signal clear_lock_addr1_sig : REGISTER_ADDR_T;
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signal clear_lock_addr1_sig : REGISTER_ADDR_T;
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signal set_lock0_sig : std_logic := '0';
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signal set_lock0_sig : std_logic := '0';
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signal set_lock_addr0_sig : REGISTER_ADDR_T;
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signal set_lock_addr0_sig : REGISTER_ADDR_T;
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signal set_lock1_sig : std_logic := '0';
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signal set_lock1_sig : std_logic := '0';
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signal set_lock_addr1_sig : REGISTER_ADDR_T;
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signal set_lock_addr1_sig : REGISTER_ADDR_T;
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component if_stage
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component if_stage
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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if_id_register : out IF_ID_REGISTER_T;
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if_id_register : out IF_ID_REGISTER_T;
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branch : in std_logic;
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branch : in std_logic;
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branch_target : in PC_REGISTER_T;
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branch_target : in PC_REGISTER_T;
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clear_in : in std_logic;
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clear_in : in std_logic;
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stall_in : in std_logic;
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stall_in : in std_logic;
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pc : in PC_REGISTER_T;
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pc : in PC_REGISTER_T;
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pc_next : out PC_REGISTER_T;
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pc_next : out PC_REGISTER_T;
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imem_addr : out MEM_ADDR_T;
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imem_addr : out MEM_ADDR_T;
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imem_data : in MEM_DATA_T);
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imem_data : in MEM_DATA_T);
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end component;
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end component;
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component id_stage
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component id_stage
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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if_id_register : in IF_ID_REGISTER_T;
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if_id_register : in IF_ID_REGISTER_T;
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id_ex_register : out ID_EX_REGISTER_T;
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id_ex_register : out ID_EX_REGISTER_T;
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rx_addr : out REGISTER_ADDR_T;
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rx_addr : out REGISTER_ADDR_T;
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ry_addr : out REGISTER_ADDR_T;
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ry_addr : out REGISTER_ADDR_T;
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rz_addr : out REGISTER_ADDR_T;
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rz_addr : out REGISTER_ADDR_T;
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rx : in REGISTER_T;
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rx : in REGISTER_T;
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ry : in REGISTER_T;
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ry : in REGISTER_T;
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rz : in REGISTER_T;
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rz : in REGISTER_T;
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sr : in SR_REGISTER_T;
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sr : in SR_REGISTER_T;
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lock_register : in LOCK_REGISTER_T;
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lock_register : in LOCK_REGISTER_T;
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set_reg_lock0 : out std_logic;
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set_reg_lock0 : out std_logic;
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lock_reg_addr0 : out REGISTER_ADDR_T;
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lock_reg_addr0 : out REGISTER_ADDR_T;
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set_reg_lock1 : out std_logic;
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set_reg_lock1 : out std_logic;
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lock_reg_addr1 : out REGISTER_ADDR_T;
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lock_reg_addr1 : out REGISTER_ADDR_T;
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stall_in : in std_logic;
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stall_in : in std_logic;
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stall_out : out std_logic;
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stall_out : out std_logic;
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clear_in : in std_logic);
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clear_in : in std_logic);
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end component;
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end component;
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component ex_stage
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component ex_stage
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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id_ex_register : in ID_EX_REGISTER_T;
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id_ex_register : in ID_EX_REGISTER_T;
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ex_mem_register : out EX_MEM_REGISTER_T;
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ex_mem_register : out EX_MEM_REGISTER_T;
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branch : out std_logic;
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branch : out std_logic;
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stall_in : in std_logic;
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stall_in : in std_logic;
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clear_in : in std_logic;
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clear_in : in std_logic;
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clear_out : out std_logic;
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clear_out : out std_logic;
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clear_locks : out std_logic);
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clear_locks : out std_logic);
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end component;
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end component;
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component mem_stage
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component mem_stage
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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ex_mem_register : in EX_MEM_REGISTER_T;
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ex_mem_register : in EX_MEM_REGISTER_T;
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mem_wb_register : out MEM_WB_REGISTER_T;
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mem_wb_register : out MEM_WB_REGISTER_T;
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dmem_addr : out MEM_ADDR_T;
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dmem_addr : out MEM_ADDR_T;
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dmem_data_in : in MEM_DATA_T;
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dmem_data_in : in MEM_DATA_T;
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dmem_data_out : out MEM_DATA_T;
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dmem_data_out : out MEM_DATA_T;
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dmem_wr_enable : out std_logic;
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dmem_wr_enable : out std_logic;
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stall_out : out std_logic;
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stall_out : out std_logic;
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clear_in : in std_logic;
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clear_in : in std_logic;
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clear_out : out std_logic);
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clear_out : out std_logic);
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end component;
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end component;
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component wb_stage
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component wb_stage
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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mem_wb_register : in MEM_WB_REGISTER_T;
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mem_wb_register : in MEM_WB_REGISTER_T;
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dreg_addr : out REGISTER_ADDR_T;
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dreg_addr : out REGISTER_ADDR_T;
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dreg : out REGISTER_T;
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dreg : out REGISTER_T;
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dreg_enable : out std_logic;
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dreg_enable : out std_logic;
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lr : out PC_REGISTER_T;
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lr : out PC_REGISTER_T;
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lr_enable : out std_logic;
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lr_enable : out std_logic;
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sr : out SR_REGISTER_T;
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sr : out SR_REGISTER_T;
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sr_enable : out std_logic;
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sr_enable : out std_logic;
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clear_out : out std_logic;
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clear_out : out std_logic;
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clear_reg_lock0 : out std_logic;
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clear_reg_lock0 : out std_logic;
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lock_reg_addr0 : out REGISTER_ADDR_T;
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lock_reg_addr0 : out REGISTER_ADDR_T;
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clear_reg_lock1 : out std_logic;
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clear_reg_lock1 : out std_logic;
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lock_reg_addr1 : out REGISTER_ADDR_T);
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lock_reg_addr1 : out REGISTER_ADDR_T);
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end component;
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end component;
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component register_file
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component register_file
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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rx_addr : in REGISTER_ADDR_T;
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rx_addr : in REGISTER_ADDR_T;
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ry_addr : in REGISTER_ADDR_T;
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ry_addr : in REGISTER_ADDR_T;
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rz_addr : in REGISTER_ADDR_T;
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rz_addr : in REGISTER_ADDR_T;
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rx_read : out REGISTER_T;
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rx_read : out REGISTER_T;
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ry_read : out REGISTER_T;
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ry_read : out REGISTER_T;
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rz_read : out REGISTER_T;
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rz_read : out REGISTER_T;
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dreg_addr : in REGISTER_ADDR_T;
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dreg_addr : in REGISTER_ADDR_T;
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dreg_write : in REGISTER_T;
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dreg_write : in REGISTER_T;
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dreg_enable : in std_logic;
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dreg_enable : in std_logic;
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sr_read : out SR_REGISTER_T;
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sr_read : out SR_REGISTER_T;
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sr_write : in SR_REGISTER_T;
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sr_write : in SR_REGISTER_T;
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sr_enable : in std_logic;
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sr_enable : in std_logic;
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lr_write : in PC_REGISTER_T;
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lr_write : in PC_REGISTER_T;
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lr_enable : in std_logic;
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lr_enable : in std_logic;
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pc_write : in PC_REGISTER_T;
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pc_write : in PC_REGISTER_T;
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pc_read : out PC_REGISTER_T);
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pc_read : out PC_REGISTER_T);
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end component;
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end component;
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component imem
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component imem
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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wr_enable : in std_logic;
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wr_enable : in std_logic;
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addr : in MEM_ADDR_T;
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addr : in MEM_ADDR_T;
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data_in : in MEM_DATA_T;
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data_in : in MEM_DATA_T;
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data_out : out MEM_DATA_T);
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data_out : out MEM_DATA_T);
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end component;
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end component;
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component dmem
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component dmem
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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wr_enable : in std_logic;
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wr_enable : in std_logic;
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addr : in MEM_ADDR_T;
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addr : in MEM_ADDR_T;
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data_in : in MEM_DATA_T;
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data_in : in MEM_DATA_T;
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data_out : out MEM_DATA_T;
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data_out : out MEM_DATA_T;
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uart_txd : out std_logic;
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uart_txd : out std_logic;
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uart_rxd : in std_logic);
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uart_rxd : in std_logic);
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end component;
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end component;
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component rlu
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component rlu
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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clear_locks : in std_logic;
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clear_locks : in std_logic;
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lock_register : out LOCK_REGISTER_T;
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lock_register : out LOCK_REGISTER_T;
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set_lock0 : in std_logic;
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set_lock0 : in std_logic;
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set_lock_addr0 : in REGISTER_ADDR_T;
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set_lock_addr0 : in REGISTER_ADDR_T;
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set_lock1 : in std_logic;
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set_lock1 : in std_logic;
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set_lock_addr1 : in REGISTER_ADDR_T;
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set_lock_addr1 : in REGISTER_ADDR_T;
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clear_lock0 : in std_logic;
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clear_lock0 : in std_logic;
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clear_lock_addr0 : in REGISTER_ADDR_T;
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clear_lock_addr0 : in REGISTER_ADDR_T;
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clear_lock1 : in std_logic;
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clear_lock1 : in std_logic;
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clear_lock_addr1 : in REGISTER_ADDR_T);
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clear_lock_addr1 : in REGISTER_ADDR_T);
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|
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end component;
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end component;
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begin -- rise_rtl
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begin -- rise_rtl
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if_stage_unit : if_stage
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if_stage_unit : if_stage
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port map (
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port map (
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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if_id_register => if_id_register_sig,
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if_id_register => if_id_register_sig,
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branch => branch_sig,
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branch => branch_sig,
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branch_target => branch_target_sig,
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branch_target => branch_target_sig,
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clear_in => clear_in_if_sig,
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clear_in => clear_in_if_sig,
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stall_in => stall_in_if_sig,
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stall_in => stall_in_if_sig,
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|
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pc => pc_if_sig,
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pc => pc_if_sig,
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pc_next => pc_next_if_sig,
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pc_next => pc_next_if_sig,
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imem_addr => imem_addr_sig,
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imem_addr => imem_addr_sig,
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imem_data => imem_data_sig);
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imem_data => imem_data_sig);
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id_stage_unit : id_stage
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id_stage_unit : id_stage
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port map (
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port map (
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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if_id_register => if_id_register_sig,
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if_id_register => if_id_register_sig,
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id_ex_register => id_ex_register_sig,
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id_ex_register => id_ex_register_sig,
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|
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rx_addr => rx_addr_sig,
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rx_addr => rx_addr_sig,
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ry_addr => ry_addr_sig,
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ry_addr => ry_addr_sig,
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rz_addr => rz_addr_sig,
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rz_addr => rz_addr_sig,
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|
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rx => rx_sig,
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rx => rx_sig,
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ry => ry_sig,
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ry => ry_sig,
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rz => rz_sig,
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rz => rz_sig,
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sr => sr_id_sig,
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sr => sr_id_sig,
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lock_register => lock_register_sig,
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lock_register => lock_register_sig,
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set_reg_lock0 => set_lock0_sig,
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set_reg_lock0 => set_lock0_sig,
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lock_reg_addr0 => set_lock_addr0_sig,
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lock_reg_addr0 => set_lock_addr0_sig,
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set_reg_lock1 => set_lock1_sig,
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set_reg_lock1 => set_lock1_sig,
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lock_reg_addr1 => set_lock_addr1_sig,
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lock_reg_addr1 => set_lock_addr1_sig,
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|
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stall_in => stall_in_id_sig,
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stall_in => stall_in_id_sig,
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stall_out => stall_out_id_sig,
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stall_out => stall_out_id_sig,
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clear_in => clear_in_id_sig);
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clear_in => clear_in_id_sig);
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|
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ex_stage_unit : ex_stage
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ex_stage_unit : ex_stage
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port map (
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port map (
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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|
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id_ex_register => id_ex_register_sig,
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id_ex_register => id_ex_register_sig,
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ex_mem_register => ex_mem_register_sig,
|
ex_mem_register => ex_mem_register_sig,
|
|
|
branch => branch_sig,
|
branch => branch_sig,
|
stall_in => stall_in_ex_sig,
|
stall_in => stall_in_ex_sig,
|
clear_in => clear_in_ex_sig,
|
clear_in => clear_in_ex_sig,
|
clear_out => clear_out_ex_sig,
|
clear_out => clear_out_ex_sig,
|
clear_locks => clear_locks_sig);
|
clear_locks => clear_locks_sig);
|
|
|
mem_stage_unit : mem_stage
|
mem_stage_unit : mem_stage
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
reset => reset,
|
reset => reset,
|
|
|
ex_mem_register => ex_mem_register_sig,
|
ex_mem_register => ex_mem_register_sig,
|
mem_wb_register => mem_wb_register_sig,
|
mem_wb_register => mem_wb_register_sig,
|
|
|
dmem_addr => dmem_addr_sig,
|
dmem_addr => dmem_addr_sig,
|
dmem_data_in => dmem_data_in_sig,
|
dmem_data_in => dmem_data_in_sig,
|
dmem_data_out => dmem_data_out_sig,
|
dmem_data_out => dmem_data_out_sig,
|
dmem_wr_enable => wr_enable_dmem_sig,
|
dmem_wr_enable => wr_enable_dmem_sig,
|
|
|
stall_out => stall_out_mem_sig,
|
stall_out => stall_out_mem_sig,
|
clear_in => clear_in_mem_sig,
|
clear_in => clear_in_mem_sig,
|
clear_out => clear_out_mem_sig);
|
clear_out => clear_out_mem_sig);
|
|
|
wb_stage_unit : wb_stage
|
wb_stage_unit : wb_stage
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
reset => reset,
|
reset => reset,
|
|
|
mem_wb_register => mem_wb_register_sig,
|
mem_wb_register => mem_wb_register_sig,
|
|
|
dreg_addr => dreg_addr_sig,
|
dreg_addr => dreg_addr_sig,
|
dreg => dreg_sig,
|
dreg => dreg_sig,
|
dreg_enable => dreg_enable_sig,
|
dreg_enable => dreg_enable_sig,
|
|
|
lr => lr_sig,
|
lr => lr_sig,
|
lr_enable => lr_enable_sig,
|
lr_enable => lr_enable_sig,
|
|
|
sr => sr_wb_sig,
|
sr => sr_wb_sig,
|
sr_enable => sr_enable_sig,
|
sr_enable => sr_enable_sig,
|
|
|
clear_out => clear_out_wb_sig,
|
clear_out => clear_out_wb_sig,
|
|
|
clear_reg_lock0 => clear_lock0_sig,
|
clear_reg_lock0 => clear_lock0_sig,
|
lock_reg_addr0 => clear_lock_addr0_sig,
|
lock_reg_addr0 => clear_lock_addr0_sig,
|
clear_reg_lock1 => clear_lock1_sig,
|
clear_reg_lock1 => clear_lock1_sig,
|
lock_reg_addr1 => clear_lock_addr1_sig);
|
lock_reg_addr1 => clear_lock_addr1_sig);
|
|
|
register_file_unit : register_file
|
register_file_unit : register_file
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
reset => reset,
|
reset => reset,
|
|
|
rx_addr => rx_addr_sig,
|
rx_addr => rx_addr_sig,
|
ry_addr => ry_addr_sig,
|
ry_addr => ry_addr_sig,
|
rz_addr => rz_addr_sig,
|
rz_addr => rz_addr_sig,
|
|
|
rx_read => rx_sig,
|
rx_read => rx_sig,
|
ry_read => ry_sig,
|
ry_read => ry_sig,
|
rz_read => rz_sig,
|
rz_read => rz_sig,
|
|
|
dreg_addr => dreg_addr_sig,
|
dreg_addr => dreg_addr_sig,
|
dreg_write => dreg_sig,
|
dreg_write => dreg_sig,
|
dreg_enable => dreg_enable_sig,
|
dreg_enable => dreg_enable_sig,
|
|
|
sr_read => sr_id_sig,
|
sr_read => sr_id_sig,
|
sr_write => sr_wb_sig,
|
sr_write => sr_wb_sig,
|
sr_enable => sr_enable_sig,
|
sr_enable => sr_enable_sig,
|
|
|
lr_write => lr_sig,
|
lr_write => lr_sig,
|
lr_enable => lr_enable_sig,
|
lr_enable => lr_enable_sig,
|
|
|
pc_write => pc_next_if_sig,
|
pc_write => pc_next_if_sig,
|
pc_read => pc_if_sig);
|
pc_read => pc_if_sig);
|
|
|
imem_unit : imem
|
imem_unit : imem
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
reset => reset,
|
reset => reset,
|
wr_enable => wr_enable_imem_sig,
|
wr_enable => wr_enable_imem_sig,
|
addr => imem_addr_sig,
|
addr => imem_addr_sig,
|
data_in => data_in_imem_sig,
|
data_in => data_in_imem_sig,
|
data_out => imem_data_sig);
|
data_out => imem_data_sig);
|
|
|
dmem_unit : dmem
|
dmem_unit : dmem
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
reset => reset,
|
reset => reset,
|
wr_enable => wr_enable_dmem_sig,
|
wr_enable => wr_enable_dmem_sig,
|
addr => dmem_addr_sig,
|
addr => dmem_addr_sig,
|
data_in => dmem_data_out_sig,
|
data_in => dmem_data_out_sig,
|
data_out => dmem_data_in_sig,
|
data_out => dmem_data_in_sig,
|
uart_txd => dmem_txd_sig,
|
uart_txd => dmem_txd_sig,
|
uart_rxd => dmem_rxd_sig);
|
uart_rxd => dmem_rxd_sig);
|
|
|
rlu_unit : rlu port map(
|
rlu_unit : rlu port map(
|
clk => clk,
|
clk => clk,
|
reset => reset,
|
reset => reset,
|
clear_locks => clear_locks_sig,
|
clear_locks => clear_locks_sig,
|
|
|
lock_register => lock_register_sig,
|
lock_register => lock_register_sig,
|
|
|
set_lock0 => set_lock0_sig,
|
set_lock0 => set_lock0_sig,
|
set_lock_addr0 => set_lock_addr0_sig,
|
set_lock_addr0 => set_lock_addr0_sig,
|
|
|
set_lock1 => set_lock1_sig,
|
set_lock1 => set_lock1_sig,
|
set_lock_addr1 => set_lock_addr1_sig,
|
set_lock_addr1 => set_lock_addr1_sig,
|
|
|
clear_lock0 => clear_lock0_sig,
|
clear_lock0 => clear_lock0_sig,
|
clear_lock_addr0 => clear_lock_addr0_sig,
|
clear_lock_addr0 => clear_lock_addr0_sig,
|
|
|
clear_lock1 => clear_lock1_sig,
|
clear_lock1 => clear_lock1_sig,
|
clear_lock_addr1 => clear_lock_addr1_sig);
|
clear_lock_addr1 => clear_lock_addr1_sig);
|
|
|
|
|
clear_in_if_sig <= clear_out_ex_sig or clear_out_mem_sig or clear_out_wb_sig;
|
clear_in_if_sig <= clear_out_ex_sig or clear_out_mem_sig or clear_out_wb_sig;
|
clear_in_id_sig <= clear_in_if_sig;
|
clear_in_id_sig <= clear_in_if_sig;
|
clear_in_ex_sig <= clear_out_mem_sig or clear_out_wb_sig;
|
clear_in_ex_sig <= clear_out_mem_sig or clear_out_wb_sig;
|
clear_in_mem_sig <= clear_out_wb_sig;
|
clear_in_mem_sig <= clear_out_wb_sig;
|
|
|
stall_in_if_sig <= stall_out_id_sig or stall_out_mem_sig;
|
stall_in_if_sig <= stall_out_id_sig or stall_out_mem_sig;
|
stall_in_id_sig <= stall_out_mem_sig;
|
stall_in_id_sig <= stall_out_mem_sig;
|
stall_in_ex_sig <= stall_out_mem_sig;
|
stall_in_ex_sig <= stall_out_mem_sig;
|
|
|
branch_target_sig <= ex_mem_register_sig.alu;
|
branch_target_sig <= ex_mem_register_sig.alu;
|
|
|
data_in_imem_sig <= (others => '-'); -- unused at the moment
|
data_in_imem_sig <= (others => '-'); -- unused at the moment
|
wr_enable_imem_sig <= '-'; -- unused at the moment
|
wr_enable_imem_sig <= '-'; -- unused at the moment
|
|
|
-- ports of top level entity
|
-- ports of top level entity
|
tx <= dmem_txd_sig;
|
tx <= dmem_txd_sig;
|
dmem_rxd_sig <= rx;
|
dmem_rxd_sig <= rx;
|
|
|
end rise_rtl;
|
end rise_rtl;
|
|
|