-- File: ex_stage.vhd
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-- File: ex_stage.vhd
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-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
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-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
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-- Created: 2006-11-29
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-- Created: 2006-11-29
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-- Last updated: 2006-11-29
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-- Last updated: 2006-11-29
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-- Description:
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-- Description:
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-- Execute stage
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-- Execute stage
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.rise_pack.all;
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use work.rise_pack.all;
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use work.RISE_PACK_SPECIFIC.all;
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use work.RISE_PACK_SPECIFIC.all;
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entity tb_rise_vhd is
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entity tb_rise_vhd is
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end tb_rise_vhd;
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end tb_rise_vhd;
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architecture behavior of tb_rise_vhd is
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architecture behavior of tb_rise_vhd is
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component rise
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component rise
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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rx : in std_logic;
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rx : in std_logic;
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tx : out std_logic
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tx : out std_logic
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);
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);
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end component;
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end component;
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--Inputs
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--Inputs
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signal clk : std_logic := '0';
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signal clk : std_logic := '0';
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signal reset : std_logic := '0';
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signal reset : std_logic := '0';
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signal rx : std_logic := '1';
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signal rx : std_logic := '1';
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--Outputs
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--Outputs
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signal tx : std_logic;
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signal tx : std_logic;
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begin
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begin
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut : rise port map(
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uut : rise port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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rx => rx,
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rx => rx,
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tx => tx
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tx => tx
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);
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);
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clk_gen : process
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clk_gen : process
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begin
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begin
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clk <= '1';
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clk <= '1';
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wait for 10 ns;
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wait for 10 ns;
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clk <= '0';
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clk <= '0';
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wait for 10 ns;
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wait for 10 ns;
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end process;
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end process;
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tb : process
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tb : process
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begin
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begin
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wait for 5 ns;
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wait for 5 ns;
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-- Place stimulus here
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-- Place stimulus here
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reset <= '1';
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reset <= '1';
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-- Let the simulation run for 200 ns;
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-- Let the simulation run for 200 ns;
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wait for 200 ns;
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wait for 200 ns;
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rx <= '0'; --startbit
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rx <= '0'; --startbit
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wait for 8600 ns; -- zellenzeit 8,6 us
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wait for 8600 ns; -- zellenzeit 8,6 us
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rx <= '0'; -- 8 datenbits
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rx <= '0'; -- 8 datenbits
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wait for 8600ns;
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wait for 8600ns;
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rx <= '1'; -- 8 datenbits
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rx <= '1'; -- 8 datenbits
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wait for 8600ns;
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wait for 8600ns;
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rx <= '0'; -- 8 datenbits
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rx <= '0'; -- 8 datenbits
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wait for 8600ns;
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wait for 8600ns;
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rx <= '0'; -- 8 datenbits
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rx <= '0'; -- 8 datenbits
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wait for 8600ns;
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wait for 8600ns;
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rx <= '0'; -- 8 datenbits
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rx <= '0'; -- 8 datenbits
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wait for 8600ns;
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wait for 8600ns;
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rx <= '1'; -- 8 datenbits
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rx <= '1'; -- 8 datenbits
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wait for 8600ns;
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wait for 8600ns;
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rx <= '1'; -- 8 datenbits
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rx <= '1'; -- 8 datenbits
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wait for 8600ns;
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wait for 8600ns;
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rx <= '0'; -- 8 datenbits
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rx <= '0'; -- 8 datenbits
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wait for 8600ns;
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wait for 8600ns;
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rx <= '1'; -- 8 stopbit
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rx <= '1'; -- 8 stopbit
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wait for 8600ns;
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wait for 8600ns;
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wait for 20us;
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wait for 20us;
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-- send a 'CR' = 0x0A
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-- send a 'CR' = 0x0A
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rx <= '0'; -- 8 startbit
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rx <= '0'; -- 8 startbit
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wait for 8600ns;
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wait for 8600ns;
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rx <= '0'; -- 8 datenbits
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rx <= '0'; -- 8 datenbits
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wait for 8600ns;
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wait for 8600ns;
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rx <= '1'; -- 8 datenbits
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rx <= '1'; -- 8 datenbits
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wait for 8600ns;
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wait for 8600ns;
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rx <= '0'; -- 8 datenbits
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rx <= '0'; -- 8 datenbits
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wait for 8600ns;
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wait for 8600ns;
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rx <= '1'; -- 8 datenbits
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rx <= '1'; -- 8 datenbits
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wait for 8600ns;
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wait for 8600ns;
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rx <= '0'; -- 8 datenbits
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rx <= '0'; -- 8 datenbits
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wait for 8600ns;
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wait for 8600ns;
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rx <= '0'; -- 8 datenbits
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rx <= '0'; -- 8 datenbits
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wait for 8600ns;
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wait for 8600ns;
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rx <= '0'; -- 8 datenbits
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rx <= '0'; -- 8 datenbits
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wait for 8600ns;
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wait for 8600ns;
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rx <= '0'; -- 8 datenbits
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rx <= '0'; -- 8 datenbits
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wait for 8600ns;
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wait for 8600ns;
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rx <= '1'; -- 8 stopbit
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rx <= '1'; -- 8 stopbit
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wait for 8600ns;
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wait for 8600ns;
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wait;
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wait;
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end process;
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end process;
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end;
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end;
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