/////////////////////////////////////////////////////////////////////
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<##//////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Author: Eyal Hochberg ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// eyal@provartec.com ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////##>
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INCLUDE def_axi2ahb.txt
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INCLUDE def_axi2ahb.txt
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OUTFILE PREFIX_rd_fifo.v
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OUTFILE PREFIX_rd_fifo.v
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module PREFIX_rd_fifo (PORTS);
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module PREFIX_rd_fifo (PORTS);
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parameter FIFO_LINES = EXPR(2 * 16); //double buffer of max burst
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parameter FIFO_LINES = EXPR(2 * 16); //double buffer of max burst
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parameter RESP_SLVERR = 2'b10;
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parameter RESP_SLVERR = 2'b10;
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input clk;
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input clk;
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input reset;
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input reset;
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port RGROUP_AXI_R;
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port RGROUP_AXI_R;
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input [DATA_BITS-1:0] HRDATA;
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input [DATA_BITS-1:0] HRDATA;
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input HREADY;
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input HREADY;
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input [1:0] HTRANS;
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input [1:0] HTRANS;
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input HRESP;
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input HRESP;
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input [ID_BITS-1:0] cmd_id;
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input [ID_BITS-1:0] cmd_id;
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input cmd_err;
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input cmd_err;
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input rdata_phase;
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input rdata_phase;
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output rdata_ready;
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output rdata_ready;
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input data_last;
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input data_last;
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wire data_push;
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wire data_push;
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wire data_pop;
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wire data_pop;
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wire data_empty;
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wire data_empty;
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wire data_full;
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wire data_full;
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reg RVALID;
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reg RVALID;
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reg [LOG2(CMD_DEPTH):0] burst_cnt;
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reg [LOG2(CMD_DEPTH):0] burst_cnt;
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wire axi_last;
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wire axi_last;
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wire ahb_last;
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wire ahb_last;
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wire [1:0] cmd_resp;
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wire [1:0] cmd_resp;
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assign cmd_resp = cmd_err | HRESP ? RESP_SLVERR : 2'b00;
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assign cmd_resp = cmd_err | HRESP ? RESP_SLVERR : 2'b00;
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assign rdata_ready = burst_cnt < 'd2;
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assign rdata_ready = burst_cnt < 'd2;
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assign data_push = rdata_phase & HREADY;
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assign data_push = rdata_phase & HREADY;
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assign data_pop = RVALID & RREADY;
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assign data_pop = RVALID & RREADY;
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assign axi_last = RVALID & RREADY & RLAST;
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assign axi_last = RVALID & RREADY & RLAST;
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assign ahb_last = rdata_phase & data_last;
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assign ahb_last = rdata_phase & data_last;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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burst_cnt <= #FFD 'd0;
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burst_cnt <= #FFD 'd0;
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else if (axi_last | ahb_last)
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else if (axi_last | ahb_last)
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burst_cnt <= #FFD burst_cnt - axi_last + ahb_last;
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burst_cnt <= #FFD burst_cnt - axi_last + ahb_last;
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prgen_fifo #(DATA_BITS+ID_BITS+2+1, FIFO_LINES)
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prgen_fifo #(DATA_BITS+ID_BITS+2+1, FIFO_LINES)
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data_fifo(
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data_fifo(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.push(data_push),
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.push(data_push),
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.pop(data_pop),
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.pop(data_pop),
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.din({HRDATA,
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.din({HRDATA,
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cmd_id,
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cmd_id,
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cmd_resp,
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cmd_resp,
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ahb_last
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ahb_last
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}
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}
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),
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),
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.dout({RDATA,
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.dout({RDATA,
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RID,
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RID,
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RRESP,
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RRESP,
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RLAST
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RLAST
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}
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}
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),
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),
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.empty(data_empty),
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.empty(data_empty),
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.full(data_full)
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.full(data_full)
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);
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);
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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RVALID <= #FFD 1'b0;
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RVALID <= #FFD 1'b0;
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else if (axi_last)
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else if (axi_last)
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RVALID <= #FFD 1'b0;
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RVALID <= #FFD 1'b0;
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else if (burst_cnt > 'd0)
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else if (burst_cnt > 'd0)
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RVALID <= #FFD 1'b1;
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RVALID <= #FFD 1'b1;
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else
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else
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RVALID <= #FFD 1'b0;
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RVALID <= #FFD 1'b0;
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endmodule
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endmodule
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