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<##//////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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//////////////////////////////////////////////////////////////////##>
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INCLUDE def_axi2apb.txt
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INCLUDE def_axi2apb.txt
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OUTFILE PREFIX_axi2apb.v
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OUTFILE PREFIX_axi2apb.v
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ITER SX
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ITER SX
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module PREFIX_axi2apb (PORTS);
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module PREFIX_axi2apb (PORTS);
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input clk;
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input clk;
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input reset;
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input reset;
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port GROUP_APB_AXI;
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port GROUP_APB_AXI;
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//apb slaves
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//apb slaves
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output penable;
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output penable;
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output pwrite;
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output pwrite;
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output [ADDR_BITS-1:0] paddr;
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output [ADDR_BITS-1:0] paddr;
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output [31:0] pwdata;
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output [31:0] pwdata;
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output pselSX;
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output pselSX;
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input [31:0] prdataSX;
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input [31:0] prdataSX;
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input preadySX;
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input preadySX;
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input pslverrSX;
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input pslverrSX;
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wire GROUP_APB3;
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wire GROUP_APB3;
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//outputs of cmd
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//outputs of cmd
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wire cmd_empty;
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wire cmd_empty;
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wire cmd_read;
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wire cmd_read;
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wire [ID_BITS-1:0] cmd_id;
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wire [ID_BITS-1:0] cmd_id;
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wire [ADDR_BITS-1:0] cmd_addr;
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wire [ADDR_BITS-1:0] cmd_addr;
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wire cmd_err;
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wire cmd_err;
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//outputs of rd / wr
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//outputs of rd / wr
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wire finish_wr;
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wire finish_wr;
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wire finish_rd;
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wire finish_rd;
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assign paddr = cmd_addr;
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assign paddr = cmd_addr;
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assign pwdata = WDATA;
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assign pwdata = WDATA;
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CREATE axi2apb_cmd.v
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CREATE axi2apb_cmd.v
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PREFIX_axi2apb_cmd PREFIX_axi2apb_cmd(
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PREFIX_axi2apb_cmd PREFIX_axi2apb_cmd(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.AWGROUP_APB_AXI_A(AWGROUP_APB_AXI_A),
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.AWGROUP_APB_AXI_A(AWGROUP_APB_AXI_A),
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.ARGROUP_APB_AXI_A(ARGROUP_APB_AXI_A),
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.ARGROUP_APB_AXI_A(ARGROUP_APB_AXI_A),
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.finish_wr(finish_wr),
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.finish_wr(finish_wr),
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.finish_rd(finish_rd),
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.finish_rd(finish_rd),
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.cmd_empty(cmd_empty),
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.cmd_empty(cmd_empty),
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.cmd_read(cmd_read),
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.cmd_read(cmd_read),
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.cmd_id(cmd_id),
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.cmd_id(cmd_id),
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.cmd_addr(cmd_addr),
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.cmd_addr(cmd_addr),
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.cmd_err(cmd_err)
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.cmd_err(cmd_err)
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);
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);
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CREATE axi2apb_rd.v
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CREATE axi2apb_rd.v
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PREFIX_axi2apb_rd PREFIX_axi2apb_rd(
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PREFIX_axi2apb_rd PREFIX_axi2apb_rd(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.GROUP_APB3(GROUP_APB3),
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.GROUP_APB3(GROUP_APB3),
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.cmd_err(cmd_err),
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.cmd_err(cmd_err),
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.cmd_id(cmd_id),
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.cmd_id(cmd_id),
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.finish_rd(finish_rd),
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.finish_rd(finish_rd),
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.RGROUP_APB_AXI_R(RGROUP_APB_AXI_R),
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.RGROUP_APB_AXI_R(RGROUP_APB_AXI_R),
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STOMP ,
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STOMP ,
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);
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);
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CREATE axi2apb_wr.v
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CREATE axi2apb_wr.v
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PREFIX_axi2apb_wr PREFIX_axi2apb_wr(
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PREFIX_axi2apb_wr PREFIX_axi2apb_wr(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.GROUP_APB3(GROUP_APB3),
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.GROUP_APB3(GROUP_APB3),
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.cmd_err(cmd_err),
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.cmd_err(cmd_err),
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.cmd_id(cmd_id),
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.cmd_id(cmd_id),
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.finish_wr(finish_wr),
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.finish_wr(finish_wr),
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.WGROUP_APB_AXI_W(WGROUP_APB_AXI_W),
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.WGROUP_APB_AXI_W(WGROUP_APB_AXI_W),
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.BGROUP_APB_AXI_B(BGROUP_APB_AXI_B),
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.BGROUP_APB_AXI_B(BGROUP_APB_AXI_B),
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STOMP ,
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STOMP ,
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);
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);
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CREATE axi2apb_mux.v
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CREATE axi2apb_mux.v
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PREFIX_axi2apb_mux PREFIX_axi2apb_mux(
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PREFIX_axi2apb_mux PREFIX_axi2apb_mux(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.cmd_addr(cmd_addr),
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.cmd_addr(cmd_addr),
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.psel(psel),
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.psel(psel),
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.prdata(prdata),
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.prdata(prdata),
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.pready(pready),
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.pready(pready),
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.pslverr(pslverr),
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.pslverr(pslverr),
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.pselSX(pselSX),
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.pselSX(pselSX),
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.preadySX(preadySX),
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.preadySX(preadySX),
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.pslverrSX(pslverrSX),
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.pslverrSX(pslverrSX),
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.prdataSX(prdataSX),
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.prdataSX(prdataSX),
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STOMP ,
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STOMP ,
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);
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);
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CREATE axi2apb_ctrl.v
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CREATE axi2apb_ctrl.v
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PREFIX_axi2apb_ctrl PREFIX_axi2apb_ctrl(
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PREFIX_axi2apb_ctrl PREFIX_axi2apb_ctrl(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.finish_wr(finish_wr),
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.finish_wr(finish_wr),
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.finish_rd(finish_rd),
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.finish_rd(finish_rd),
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.cmd_empty(cmd_empty),
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.cmd_empty(cmd_empty),
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.cmd_read(cmd_read),
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.cmd_read(cmd_read),
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.WVALID(WVALID),
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.WVALID(WVALID),
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.psel(psel),
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.psel(psel),
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.penable(penable),
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.penable(penable),
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.pwrite(pwrite),
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.pwrite(pwrite),
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.pready(pready)
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.pready(pready)
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);
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);
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endmodule
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endmodule
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