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[/] [robust_axi2apb/] [trunk/] [src/] [base/] [def_axi2apb_static.txt] - Diff between revs 2 and 4
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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//////////////////////////////////////////////////////////////////##>
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SWAP SLV_BITS LOG2(EXPR(SLAVE_NUM+1)) ##one more for decerr slave
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SWAP SLV_BITS LOG2(EXPR(SLAVE_NUM+1)) ##one more for decerr slave
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LOOP SX SLAVE_NUM
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LOOP SX SLAVE_NUM
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GROUP APB3 is {
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GROUP APB3 is {
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psel 1 output
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psel 1 output
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penable 1 output
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penable 1 output
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pwrite 1 output
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pwrite 1 output
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paddr ADDR_BITS output
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paddr ADDR_BITS output
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pwdata 32 output
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pwdata 32 output
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prdata 32 input
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prdata 32 input
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pslverr 1 input
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pslverr 1 input
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pready 1 input
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pready 1 input
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}
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}
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GROUP APB_AXI_A is {
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GROUP APB_AXI_A is {
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ID ID_BITS input
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ID ID_BITS input
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ADDR ADDR_BITS input
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ADDR ADDR_BITS input
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LEN 4 input
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LEN 4 input
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SIZE 2 input
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SIZE 2 input
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VALID 1 input
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VALID 1 input
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READY 1 output
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READY 1 output
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}
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}
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GROUP APB_AXI_W is {
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GROUP APB_AXI_W is {
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ID ID_BITS input
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ID ID_BITS input
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DATA 32 input
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DATA 32 input
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STRB 4 input
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STRB 4 input
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LAST 1 input
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LAST 1 input
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VALID 1 input
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VALID 1 input
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READY 1 output
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READY 1 output
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}
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}
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GROUP APB_AXI_B is {
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GROUP APB_AXI_B is {
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ID ID_BITS output
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ID ID_BITS output
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RESP 2 output
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RESP 2 output
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VALID 1 output
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VALID 1 output
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READY 1 input
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READY 1 input
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}
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}
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GROUP APB_AXI_R is {
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GROUP APB_AXI_R is {
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ID ID_BITS output
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ID ID_BITS output
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DATA 32 output
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DATA 32 output
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RESP 2 output
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RESP 2 output
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LAST 1 output
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LAST 1 output
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VALID 1 output
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VALID 1 output
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READY 1 input
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READY 1 input
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}
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}
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GROUP APB_AXI joins {
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GROUP APB_AXI joins {
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GROUP APB_AXI_A prefix_AW
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GROUP APB_AXI_A prefix_AW
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GROUP APB_AXI_W prefix_W
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GROUP APB_AXI_W prefix_W
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GROUP APB_AXI_B prefix_B
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GROUP APB_AXI_B prefix_B
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GROUP APB_AXI_A prefix_AR
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GROUP APB_AXI_A prefix_AR
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GROUP APB_AXI_R prefix_R
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GROUP APB_AXI_R prefix_R
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}
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}
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