<##//////////////////////////////////////////////////////////////////
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<##//////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Author: Eyal Hochberg ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// eyal@provartec.com ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////##>
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//////////////////////////////////////////////////////////////////##>
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OUTFILE fir_serial_TOPO.v
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OUTFILE PREFIX_serial_TOPO.v
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ITER OX ORDER
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ITER OX ORDER
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ITER CX COEFF_NUM
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ITER CX COEFF_NUM
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ITER SX ADD_STAGES
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ITER SX ADD_STAGES
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// Built In Parameters:
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// Built In Parameters:
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//
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//
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// Filter Order = ORDER
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// Filter Order = ORDER
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// Input Precision = DIN_BITS
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// Input Precision = DIN_BITS
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// Coefficient Precision = COEFF_BITS
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// Coefficient Precision = COEFF_BITS
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// Sum of Products Latency = LATENCY
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// Sum of Products Latency = LATENCY
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module fir_serial_TOPO (PORTS);
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module PREFIX_serial_TOPO (PORTS);
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input clk;
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input clk;
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input reset;
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input reset;
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input clken;
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input clken;
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input [EXPR(COEFF_BITS-1):0] kCX;
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input [EXPR(COEFF_BITS-1):0] kCX;
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input [EXPR(DIN_BITS-1):0] data_in;
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input [EXPR(DIN_BITS-1):0] data_in;
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output [EXPR(DOUT_BITS-1):0] data_out;
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output [EXPR(DOUT_BITS-1):0] data_out;
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output valid;
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output valid;
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wire [EXPR(COEFF_BITS-1):0] k;
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wire [EXPR(COEFF_BITS-1):0] k;
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wire [EXPR(MULT_BITS-1):0] mult;
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wire [EXPR(MULT_BITS-1):0] mult;
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reg [EXPR(DOUT_BITS-1):0] multCX;
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reg [EXPR(DOUT_BITS-1):0] multCX;
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wire [EXPR(DOUT_BITS-1):0] add;
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wire [EXPR(DOUT_BITS-1):0] add;
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wire addCX;
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wire addCX;
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reg [EXPR(DOUT_BITS-1):0] mult_sum;
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reg [EXPR(DOUT_BITS-1):0] mult_sum;
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reg [EXPR(DOUT_BITS-1):0] data_out;
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reg [EXPR(DOUT_BITS-1):0] data_out;
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reg valid;
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reg valid;
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reg active;
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reg active;
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reg [EXPR(ADD_STAGES-1):0] phase;
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reg [EXPR(ADD_STAGES-1):0] phase;
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reg [EXPR(ADD_STAGES-1):0] cycle;
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reg [EXPR(ADD_STAGES-1):0] cycle;
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wire phaseCX;
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wire phaseCX;
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wire cycleCX;
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wire cycleCX;
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assign phaseCX = phase == 'dCX;
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assign phaseCX = phase == 'dCX;
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assign cycleCX = cycle == 'dCX;
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assign cycleCX = cycle == 'dCX;
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assign k =
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assign k =
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phaseOX ? kOX :
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phaseOX ? kOX :
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kORDER;
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kORDER;
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//a single multiplayer and a single adder
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//a single multiplayer and a single adder
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assign mult = k * data_in;
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assign mult = k * data_in;
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assign add = mult + (
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assign add = mult + (
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addOX ? multOX :
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addOX ? multOX :
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multORDER);
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multORDER);
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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active <= #FFD 1'b0;
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active <= #FFD 1'b0;
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else if (clken)
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else if (clken)
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active <= #FFD 1'b1;
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active <= #FFD 1'b1;
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else if (phase == 'dORDER)
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else if (phase == 'dORDER)
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active <= #FFD 1'b0;
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active <= #FFD 1'b0;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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phase <= #FFD {ADD_STAGES{1'b0}};
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phase <= #FFD {ADD_STAGES{1'b0}};
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else if (phase == 'dORDER)
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else if (phase == 'dORDER)
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phase <= #FFD {ADD_STAGES{1'b0}};
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phase <= #FFD {ADD_STAGES{1'b0}};
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else if (active)
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else if (active)
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phase <= #FFD phase + 1'b1;
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phase <= #FFD phase + 1'b1;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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cycle <= #FFD {ADD_STAGES{1'b0}};
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cycle <= #FFD {ADD_STAGES{1'b0}};
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else if (phase == 'dORDER)
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else if (phase == 'dORDER)
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begin
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begin
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if (cycle == 'dORDER)
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if (cycle == 'dORDER)
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cycle <= #FFD {ADD_STAGES{1'b0}};
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cycle <= #FFD {ADD_STAGES{1'b0}};
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else
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else
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cycle <= cycle + 1'b1;
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cycle <= cycle + 1'b1;
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end
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end
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LOOP PX COEFF_NUM
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LOOP PX COEFF_NUM
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assign addPX = active & (
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assign addPX = active & (
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(phaseEXPR((COEFF_NUM+PX-CX)%COEFF_NUM) && cycleCX) ||
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(phaseEXPR((COEFF_NUM+PX-CX)%COEFF_NUM) && cycleCX) ||
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STOMP || );
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STOMP || );
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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multPX <= #FFD {MULT_BITS{1'b0}};
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multPX <= #FFD {MULT_BITS{1'b0}};
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else if (phase1 && cyclePX)
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else if (phase1 && cyclePX)
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multPX <= #FFD {MULT_BITS{1'b0}};
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multPX <= #FFD {MULT_BITS{1'b0}};
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else if (addPX)
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else if (addPX)
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multPX <= #FFD add;
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multPX <= #FFD add;
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ENDLOOP PX
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ENDLOOP PX
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//sample when valid
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//sample when valid
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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mult_sum <= #FFD {DOUT_BITS{1'b0}};
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mult_sum <= #FFD {DOUT_BITS{1'b0}};
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else if (phase1)
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else if (phase1)
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begin
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begin
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LOOP CX COEFF_NUM
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LOOP CX COEFF_NUM
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if (cycleCX)
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if (cycleCX)
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mult_sum <= #FFD multCX;
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mult_sum <= #FFD multCX;
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else
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else
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STOMP NEWLINE
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STOMP NEWLINE
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ENDLOOP CX
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ENDLOOP CX
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STOMP else
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STOMP else
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end
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end
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//sync to clock enable
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//sync to clock enable
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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begin
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begin
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data_out <= #FFD {DOUT_BITS{1'b0}};
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data_out <= #FFD {DOUT_BITS{1'b0}};
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valid <= #FFD 1'b0;
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valid <= #FFD 1'b0;
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end
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end
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else if (clken)
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else if (clken)
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begin
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begin
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data_out <= #FFD mult_sum;
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data_out <= #FFD mult_sum;
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valid <= #FFD 1'b1;
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valid <= #FFD 1'b1;
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end
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end
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else
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else
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begin
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begin
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valid <= #FFD 1'b0;
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valid <= #FFD 1'b0;
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end
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end
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endmodule
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endmodule
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