|
|
module MULT_BY_ALPHA51(b, z);
|
module MULT_BY_ALPHA51(b, z);
|
input [7:0] b;
|
input [7:0] b;
|
output [7:0] z;
|
output [7:0] z;
|
assign z[0] = b[5]^b[7];
|
assign z[0] = b[5]^b[7];
|
assign z[1] = b[0]^b[6];
|
assign z[1] = b[0]^b[6];
|
assign z[2] = b[1]^b[5];
|
assign z[2] = b[1]^b[5];
|
assign z[3] = b[0]^b[2]^b[5]^b[6]^b[7];
|
assign z[3] = b[0]^b[2]^b[5]^b[6]^b[7];
|
assign z[4] = b[1]^b[3]^b[5]^b[6]^b[7]^b[7];
|
assign z[4] = b[1]^b[3]^b[5]^b[6]^b[7]^b[7];
|
assign z[5] = b[2]^b[4]^b[6]^b[7];
|
assign z[5] = b[2]^b[4]^b[6]^b[7];
|
assign z[6] = b[3]^b[5]^b[7];
|
assign z[6] = b[3]^b[5]^b[7];
|
assign z[7] = b[4]^b[6];
|
assign z[7] = b[4]^b[6];
|
endmodule
|
endmodule
|
|
|
module SYN2ERR(SYND1_, SYND2_, LOC);
|
module SYN2ERR(SYND1_, SYND2_, LOC);
|
|
|
|
|
input [7:0] SYND1_, SYND2_;
|
input [7:0] SYND1_, SYND2_;
|
output [2:0] LOC;
|
output [2:0] LOC;
|
|
|
|
|
|
|
|
|
wire [7:0] SYND2_inv;
|
wire [7:0] SYND2_inv;
|
wire [7:0] mult_out;
|
wire [7:0] mult_out;
|
|
|
inv_gf256 inv_(.x(SYND2_), .y(SYND2_inv));
|
inv_gf256 inv_(.x(SYND2_), .y(SYND2_inv));
|
gf256mult mult_(.a(SYND1_), .b(SYND2_inv), .z(mult_out));
|
gf256mult mult_(.a(SYND1_), .b(SYND2_inv), .z(mult_out));
|
|
|
assign LOC[2] = ~(mult_out[1] | mult_out[2] );
|
assign LOC[2] = ~(mult_out[1] | mult_out[2] );
|
assign LOC[1] = mult_out[4];
|
assign LOC[1] = mult_out[4];
|
assign LOC[0] = mult_out[2];
|
assign LOC[0] = mult_out[2];
|
|
|
|
|
endmodule
|
endmodule
|
|
|
/******************************************************************/
|
/******************************************************************/
|
|
|
module gf256mult(a, b, z);
|
module gf256mult(a, b, z);
|
input [7:0] a;
|
input [7:0] a;
|
input [7:0] b;
|
input [7:0] b;
|
output [7:0] z;
|
output [7:0] z;
|
assign z[0] = b[0]&a[0]^b[1]&a[7]^b[2]&a[6]^b[3]&a[5]^b[4]&a[4]^b[5]&a[3]^b[5]&a[7]^b[6]&a[2]^b[6]&a[6]^b[6]&a[7]^b[7]&a[1]^b[7]&a[5]^b[7]&a[6]^b[7]&a[7];
|
assign z[0] = b[0]&a[0]^b[1]&a[7]^b[2]&a[6]^b[3]&a[5]^b[4]&a[4]^b[5]&a[3]^b[5]&a[7]^b[6]&a[2]^b[6]&a[6]^b[6]&a[7]^b[7]&a[1]^b[7]&a[5]^b[7]&a[6]^b[7]&a[7];
|
assign z[1] = b[0]&a[1]^b[1]&a[0]^b[2]&a[7]^b[3]&a[6]^b[4]&a[5]^b[5]&a[4]^b[6]&a[3]^b[6]&a[7]^b[7]&a[2]^b[7]&a[6]^b[7]&a[7];
|
assign z[1] = b[0]&a[1]^b[1]&a[0]^b[2]&a[7]^b[3]&a[6]^b[4]&a[5]^b[5]&a[4]^b[6]&a[3]^b[6]&a[7]^b[7]&a[2]^b[7]&a[6]^b[7]&a[7];
|
assign z[2] = b[0]&a[2]^b[1]&a[1]^b[1]&a[7]^b[2]&a[0]^b[2]&a[6]^b[3]&a[5]^b[3]&a[7]^b[4]&a[4]^b[4]&a[6]^b[5]&a[3]^b[5]&a[5]^b[5]&a[7]^b[6]&a[2]^b[6]&a[4]^b[6]&a[6]^b[6]&a[7]^b[7]&a[1]^b[7]&a[3]^b[7]&a[5]^b[7]&a[6];
|
assign z[2] = b[0]&a[2]^b[1]&a[1]^b[1]&a[7]^b[2]&a[0]^b[2]&a[6]^b[3]&a[5]^b[3]&a[7]^b[4]&a[4]^b[4]&a[6]^b[5]&a[3]^b[5]&a[5]^b[5]&a[7]^b[6]&a[2]^b[6]&a[4]^b[6]&a[6]^b[6]&a[7]^b[7]&a[1]^b[7]&a[3]^b[7]&a[5]^b[7]&a[6];
|
assign z[3] = b[0]&a[3]^b[1]&a[2]^b[1]&a[7]^b[2]&a[1]^b[2]&a[6]^b[2]&a[7]^b[3]&a[0]^b[3]&a[5]^b[3]&a[6]^b[4]&a[4]^b[4]&a[5]^b[4]&a[7]^b[5]&a[3]^b[5]&a[4]^b[5]&a[6]^b[5]&a[7]^b[6]&a[2]^b[6]&a[3]^b[6]&a[5]^b[6]&a[6]^b[7]&a[1]^b[7]&a[2]^b[7]&a[4]^b[7]&a[5];
|
assign z[3] = b[0]&a[3]^b[1]&a[2]^b[1]&a[7]^b[2]&a[1]^b[2]&a[6]^b[2]&a[7]^b[3]&a[0]^b[3]&a[5]^b[3]&a[6]^b[4]&a[4]^b[4]&a[5]^b[4]&a[7]^b[5]&a[3]^b[5]&a[4]^b[5]&a[6]^b[5]&a[7]^b[6]&a[2]^b[6]&a[3]^b[6]&a[5]^b[6]&a[6]^b[7]&a[1]^b[7]&a[2]^b[7]&a[4]^b[7]&a[5];
|
assign z[4] = b[0]&a[4]^b[1]&a[3]^b[1]&a[7]^b[2]&a[2]^b[2]&a[6]^b[2]&a[7]^b[3]&a[1]^b[3]&a[5]^b[3]&a[6]^b[3]&a[7]^b[4]&a[0]^b[4]&a[4]^b[4]&a[5]^b[4]&a[6]^b[5]&a[3]^b[5]&a[4]^b[5]&a[5]^b[6]&a[2]^b[6]&a[3]^b[6]&a[4]^b[7]&a[1]^b[7]&a[2]^b[7]&a[3]^b[7]&a[7];
|
assign z[4] = b[0]&a[4]^b[1]&a[3]^b[1]&a[7]^b[2]&a[2]^b[2]&a[6]^b[2]&a[7]^b[3]&a[1]^b[3]&a[5]^b[3]&a[6]^b[3]&a[7]^b[4]&a[0]^b[4]&a[4]^b[4]&a[5]^b[4]&a[6]^b[5]&a[3]^b[5]&a[4]^b[5]&a[5]^b[6]&a[2]^b[6]&a[3]^b[6]&a[4]^b[7]&a[1]^b[7]&a[2]^b[7]&a[3]^b[7]&a[7];
|
assign z[5] = b[0]&a[5]^b[1]&a[4]^b[2]&a[3]^b[2]&a[7]^b[3]&a[2]^b[3]&a[6]^b[3]&a[7]^b[4]&a[1]^b[4]&a[5]^b[4]&a[6]^b[4]&a[7]^b[5]&a[0]^b[5]&a[4]^b[5]&a[5]^b[5]&a[6]^b[6]&a[3]^b[6]&a[4]^b[6]&a[5]^b[7]&a[2]^b[7]&a[3]^b[7]&a[4];
|
assign z[5] = b[0]&a[5]^b[1]&a[4]^b[2]&a[3]^b[2]&a[7]^b[3]&a[2]^b[3]&a[6]^b[3]&a[7]^b[4]&a[1]^b[4]&a[5]^b[4]&a[6]^b[4]&a[7]^b[5]&a[0]^b[5]&a[4]^b[5]&a[5]^b[5]&a[6]^b[6]&a[3]^b[6]&a[4]^b[6]&a[5]^b[7]&a[2]^b[7]&a[3]^b[7]&a[4];
|
assign z[6] = b[0]&a[6]^b[1]&a[5]^b[2]&a[4]^b[3]&a[3]^b[3]&a[7]^b[4]&a[2]^b[4]&a[6]^b[4]&a[7]^b[5]&a[1]^b[5]&a[5]^b[5]&a[6]^b[5]&a[7]^b[6]&a[0]^b[6]&a[4]^b[6]&a[5]^b[6]&a[6]^b[7]&a[3]^b[7]&a[4]^b[7]&a[5];
|
assign z[6] = b[0]&a[6]^b[1]&a[5]^b[2]&a[4]^b[3]&a[3]^b[3]&a[7]^b[4]&a[2]^b[4]&a[6]^b[4]&a[7]^b[5]&a[1]^b[5]&a[5]^b[5]&a[6]^b[5]&a[7]^b[6]&a[0]^b[6]&a[4]^b[6]&a[5]^b[6]&a[6]^b[7]&a[3]^b[7]&a[4]^b[7]&a[5];
|
assign z[7] = b[0]&a[7]^b[1]&a[6]^b[2]&a[5]^b[3]&a[4]^b[4]&a[3]^b[4]&a[7]^b[5]&a[2]^b[5]&a[6]^b[5]&a[7]^b[6]&a[1]^b[6]&a[5]^b[6]&a[6]^b[6]&a[7]^b[7]&a[0]^b[7]&a[4]^b[7]&a[5]^b[7]&a[6];
|
assign z[7] = b[0]&a[7]^b[1]&a[6]^b[2]&a[5]^b[3]&a[4]^b[4]&a[3]^b[4]&a[7]^b[5]&a[2]^b[5]&a[6]^b[5]&a[7]^b[6]&a[1]^b[6]&a[5]^b[6]&a[6]^b[6]&a[7]^b[7]&a[0]^b[7]&a[4]^b[7]&a[5]^b[7]&a[6];
|
endmodule
|
endmodule
|
|
|
/******************************************************************/
|
/******************************************************************/
|
|
|
module inv_gf256(x, y);
|
module inv_gf256(x, y);
|
input [7:0] x;
|
input [7:0] x;
|
output [7:0] y;
|
output [7:0] y;
|
reg [7:0] y;
|
reg [7:0] y;
|
|
|
always@(x)
|
always@(x)
|
|
|
case(x)
|
case(x)
|
0: y<= 0;
|
0: y<= 0;
|
1: y<= 1;
|
1: y<= 1;
|
2: y<= 142;
|
2: y<= 142;
|
4: y<= 71;
|
4: y<= 71;
|
8: y<= 173;
|
8: y<= 173;
|
16: y<= 216;
|
16: y<= 216;
|
32: y<= 108;
|
32: y<= 108;
|
64: y<= 54;
|
64: y<= 54;
|
128: y<= 27;
|
128: y<= 27;
|
29: y<= 131;
|
29: y<= 131;
|
58: y<= 207;
|
58: y<= 207;
|
116: y<= 233;
|
116: y<= 233;
|
232: y<= 250;
|
232: y<= 250;
|
205: y<= 125;
|
205: y<= 125;
|
135: y<= 176;
|
135: y<= 176;
|
19: y<= 88;
|
19: y<= 88;
|
38: y<= 44;
|
38: y<= 44;
|
76: y<= 22;
|
76: y<= 22;
|
152: y<= 11;
|
152: y<= 11;
|
45: y<= 139;
|
45: y<= 139;
|
90: y<= 203;
|
90: y<= 203;
|
180: y<= 235;
|
180: y<= 235;
|
117: y<= 251;
|
117: y<= 251;
|
234: y<= 243;
|
234: y<= 243;
|
201: y<= 247;
|
201: y<= 247;
|
143: y<= 245;
|
143: y<= 245;
|
3: y<= 244;
|
3: y<= 244;
|
6: y<= 122;
|
6: y<= 122;
|
12: y<= 61;
|
12: y<= 61;
|
24: y<= 144;
|
24: y<= 144;
|
48: y<= 72;
|
48: y<= 72;
|
96: y<= 36;
|
96: y<= 36;
|
192: y<= 18;
|
192: y<= 18;
|
157: y<= 9;
|
157: y<= 9;
|
39: y<= 138;
|
39: y<= 138;
|
78: y<= 69;
|
78: y<= 69;
|
156: y<= 172;
|
156: y<= 172;
|
37: y<= 86;
|
37: y<= 86;
|
74: y<= 43;
|
74: y<= 43;
|
148: y<= 155;
|
148: y<= 155;
|
53: y<= 195;
|
53: y<= 195;
|
106: y<= 239;
|
106: y<= 239;
|
212: y<= 249;
|
212: y<= 249;
|
181: y<= 242;
|
181: y<= 242;
|
119: y<= 121;
|
119: y<= 121;
|
238: y<= 178;
|
238: y<= 178;
|
193: y<= 89;
|
193: y<= 89;
|
159: y<= 162;
|
159: y<= 162;
|
35: y<= 81;
|
35: y<= 81;
|
70: y<= 166;
|
70: y<= 166;
|
140: y<= 83;
|
140: y<= 83;
|
5: y<= 167;
|
5: y<= 167;
|
10: y<= 221;
|
10: y<= 221;
|
20: y<= 224;
|
20: y<= 224;
|
40: y<= 112;
|
40: y<= 112;
|
80: y<= 56;
|
80: y<= 56;
|
160: y<= 28;
|
160: y<= 28;
|
93: y<= 14;
|
93: y<= 14;
|
186: y<= 7;
|
186: y<= 7;
|
105: y<= 141;
|
105: y<= 141;
|
210: y<= 200;
|
210: y<= 200;
|
185: y<= 100;
|
185: y<= 100;
|
111: y<= 50;
|
111: y<= 50;
|
222: y<= 25;
|
222: y<= 25;
|
161: y<= 130;
|
161: y<= 130;
|
95: y<= 65;
|
95: y<= 65;
|
190: y<= 174;
|
190: y<= 174;
|
97: y<= 87;
|
97: y<= 87;
|
194: y<= 165;
|
194: y<= 165;
|
153: y<= 220;
|
153: y<= 220;
|
47: y<= 110;
|
47: y<= 110;
|
94: y<= 55;
|
94: y<= 55;
|
188: y<= 149;
|
188: y<= 149;
|
101: y<= 196;
|
101: y<= 196;
|
202: y<= 98;
|
202: y<= 98;
|
137: y<= 49;
|
137: y<= 49;
|
15: y<= 150;
|
15: y<= 150;
|
30: y<= 75;
|
30: y<= 75;
|
60: y<= 171;
|
60: y<= 171;
|
120: y<= 219;
|
120: y<= 219;
|
240: y<= 227;
|
240: y<= 227;
|
253: y<= 255;
|
253: y<= 255;
|
231: y<= 241;
|
231: y<= 241;
|
211: y<= 246;
|
211: y<= 246;
|
187: y<= 123;
|
187: y<= 123;
|
107: y<= 179;
|
107: y<= 179;
|
214: y<= 215;
|
214: y<= 215;
|
177: y<= 229;
|
177: y<= 229;
|
127: y<= 252;
|
127: y<= 252;
|
254: y<= 126;
|
254: y<= 126;
|
225: y<= 63;
|
225: y<= 63;
|
223: y<= 145;
|
223: y<= 145;
|
163: y<= 198;
|
163: y<= 198;
|
91: y<= 99;
|
91: y<= 99;
|
182: y<= 191;
|
182: y<= 191;
|
113: y<= 209;
|
113: y<= 209;
|
226: y<= 230;
|
226: y<= 230;
|
217: y<= 115;
|
217: y<= 115;
|
175: y<= 183;
|
175: y<= 183;
|
67: y<= 213;
|
67: y<= 213;
|
134: y<= 228;
|
134: y<= 228;
|
17: y<= 114;
|
17: y<= 114;
|
34: y<= 57;
|
34: y<= 57;
|
68: y<= 146;
|
68: y<= 146;
|
136: y<= 73;
|
136: y<= 73;
|
13: y<= 170;
|
13: y<= 170;
|
26: y<= 85;
|
26: y<= 85;
|
52: y<= 164;
|
52: y<= 164;
|
104: y<= 82;
|
104: y<= 82;
|
208: y<= 41;
|
208: y<= 41;
|
189: y<= 154;
|
189: y<= 154;
|
103: y<= 77;
|
103: y<= 77;
|
206: y<= 168;
|
206: y<= 168;
|
129: y<= 84;
|
129: y<= 84;
|
31: y<= 42;
|
31: y<= 42;
|
62: y<= 21;
|
62: y<= 21;
|
124: y<= 132;
|
124: y<= 132;
|
248: y<= 66;
|
248: y<= 66;
|
237: y<= 33;
|
237: y<= 33;
|
199: y<= 158;
|
199: y<= 158;
|
147: y<= 79;
|
147: y<= 79;
|
59: y<= 169;
|
59: y<= 169;
|
118: y<= 218;
|
118: y<= 218;
|
236: y<= 109;
|
236: y<= 109;
|
197: y<= 184;
|
197: y<= 184;
|
151: y<= 92;
|
151: y<= 92;
|
51: y<= 46;
|
51: y<= 46;
|
102: y<= 23;
|
102: y<= 23;
|
204: y<= 133;
|
204: y<= 133;
|
133: y<= 204;
|
133: y<= 204;
|
23: y<= 102;
|
23: y<= 102;
|
46: y<= 51;
|
46: y<= 51;
|
92: y<= 151;
|
92: y<= 151;
|
184: y<= 197;
|
184: y<= 197;
|
109: y<= 236;
|
109: y<= 236;
|
218: y<= 118;
|
218: y<= 118;
|
169: y<= 59;
|
169: y<= 59;
|
79: y<= 147;
|
79: y<= 147;
|
158: y<= 199;
|
158: y<= 199;
|
33: y<= 237;
|
33: y<= 237;
|
66: y<= 248;
|
66: y<= 248;
|
132: y<= 124;
|
132: y<= 124;
|
21: y<= 62;
|
21: y<= 62;
|
42: y<= 31;
|
42: y<= 31;
|
84: y<= 129;
|
84: y<= 129;
|
168: y<= 206;
|
168: y<= 206;
|
77: y<= 103;
|
77: y<= 103;
|
154: y<= 189;
|
154: y<= 189;
|
41: y<= 208;
|
41: y<= 208;
|
82: y<= 104;
|
82: y<= 104;
|
164: y<= 52;
|
164: y<= 52;
|
85: y<= 26;
|
85: y<= 26;
|
170: y<= 13;
|
170: y<= 13;
|
73: y<= 136;
|
73: y<= 136;
|
146: y<= 68;
|
146: y<= 68;
|
57: y<= 34;
|
57: y<= 34;
|
114: y<= 17;
|
114: y<= 17;
|
228: y<= 134;
|
228: y<= 134;
|
213: y<= 67;
|
213: y<= 67;
|
183: y<= 175;
|
183: y<= 175;
|
115: y<= 217;
|
115: y<= 217;
|
230: y<= 226;
|
230: y<= 226;
|
209: y<= 113;
|
209: y<= 113;
|
191: y<= 182;
|
191: y<= 182;
|
99: y<= 91;
|
99: y<= 91;
|
198: y<= 163;
|
198: y<= 163;
|
145: y<= 223;
|
145: y<= 223;
|
63: y<= 225;
|
63: y<= 225;
|
126: y<= 254;
|
126: y<= 254;
|
252: y<= 127;
|
252: y<= 127;
|
229: y<= 177;
|
229: y<= 177;
|
215: y<= 214;
|
215: y<= 214;
|
179: y<= 107;
|
179: y<= 107;
|
123: y<= 187;
|
123: y<= 187;
|
246: y<= 211;
|
246: y<= 211;
|
241: y<= 231;
|
241: y<= 231;
|
255: y<= 253;
|
255: y<= 253;
|
227: y<= 240;
|
227: y<= 240;
|
219: y<= 120;
|
219: y<= 120;
|
171: y<= 60;
|
171: y<= 60;
|
75: y<= 30;
|
75: y<= 30;
|
150: y<= 15;
|
150: y<= 15;
|
49: y<= 137;
|
49: y<= 137;
|
98: y<= 202;
|
98: y<= 202;
|
196: y<= 101;
|
196: y<= 101;
|
149: y<= 188;
|
149: y<= 188;
|
55: y<= 94;
|
55: y<= 94;
|
110: y<= 47;
|
110: y<= 47;
|
220: y<= 153;
|
220: y<= 153;
|
165: y<= 194;
|
165: y<= 194;
|
87: y<= 97;
|
87: y<= 97;
|
174: y<= 190;
|
174: y<= 190;
|
65: y<= 95;
|
65: y<= 95;
|
130: y<= 161;
|
130: y<= 161;
|
25: y<= 222;
|
25: y<= 222;
|
50: y<= 111;
|
50: y<= 111;
|
100: y<= 185;
|
100: y<= 185;
|
200: y<= 210;
|
200: y<= 210;
|
141: y<= 105;
|
141: y<= 105;
|
7: y<= 186;
|
7: y<= 186;
|
14: y<= 93;
|
14: y<= 93;
|
28: y<= 160;
|
28: y<= 160;
|
56: y<= 80;
|
56: y<= 80;
|
112: y<= 40;
|
112: y<= 40;
|
224: y<= 20;
|
224: y<= 20;
|
221: y<= 10;
|
221: y<= 10;
|
167: y<= 5;
|
167: y<= 5;
|
83: y<= 140;
|
83: y<= 140;
|
166: y<= 70;
|
166: y<= 70;
|
81: y<= 35;
|
81: y<= 35;
|
162: y<= 159;
|
162: y<= 159;
|
89: y<= 193;
|
89: y<= 193;
|
178: y<= 238;
|
178: y<= 238;
|
121: y<= 119;
|
121: y<= 119;
|
242: y<= 181;
|
242: y<= 181;
|
249: y<= 212;
|
249: y<= 212;
|
239: y<= 106;
|
239: y<= 106;
|
195: y<= 53;
|
195: y<= 53;
|
155: y<= 148;
|
155: y<= 148;
|
43: y<= 74;
|
43: y<= 74;
|
86: y<= 37;
|
86: y<= 37;
|
172: y<= 156;
|
172: y<= 156;
|
69: y<= 78;
|
69: y<= 78;
|
138: y<= 39;
|
138: y<= 39;
|
9: y<= 157;
|
9: y<= 157;
|
18: y<= 192;
|
18: y<= 192;
|
36: y<= 96;
|
36: y<= 96;
|
72: y<= 48;
|
72: y<= 48;
|
144: y<= 24;
|
144: y<= 24;
|
61: y<= 12;
|
61: y<= 12;
|
122: y<= 6;
|
122: y<= 6;
|
244: y<= 3;
|
244: y<= 3;
|
245: y<= 143;
|
245: y<= 143;
|
247: y<= 201;
|
247: y<= 201;
|
243: y<= 234;
|
243: y<= 234;
|
251: y<= 117;
|
251: y<= 117;
|
235: y<= 180;
|
235: y<= 180;
|
203: y<= 90;
|
203: y<= 90;
|
139: y<= 45;
|
139: y<= 45;
|
11: y<= 152;
|
11: y<= 152;
|
22: y<= 76;
|
22: y<= 76;
|
44: y<= 38;
|
44: y<= 38;
|
88: y<= 19;
|
88: y<= 19;
|
176: y<= 135;
|
176: y<= 135;
|
125: y<= 205;
|
125: y<= 205;
|
250: y<= 232;
|
250: y<= 232;
|
233: y<= 116;
|
233: y<= 116;
|
207: y<= 58;
|
207: y<= 58;
|
131: y<= 29;
|
131: y<= 29;
|
27: y<= 128;
|
27: y<= 128;
|
54: y<= 64;
|
54: y<= 64;
|
108: y<= 32;
|
108: y<= 32;
|
216: y<= 16;
|
216: y<= 16;
|
173: y<= 8;
|
173: y<= 8;
|
71: y<= 4;
|
71: y<= 4;
|
142: y<= 2;
|
142: y<= 2;
|
endcase
|
endcase
|
|
|
endmodule
|
endmodule
|
/******************************************************************/
|
/******************************************************************/
|
module RS_5_3_GF256(
|
module RS_5_3_GF256(
|
CLK,
|
CLK,
|
RESET,
|
RESET,
|
DATA_VALID_IN,
|
DATA_VALID_IN,
|
DATA_IN,
|
DATA_IN,
|
E_D,
|
E_D,
|
DATA_VALID_OUT,
|
DATA_VALID_OUT,
|
DATA_OUT);
|
DATA_OUT);
|
|
|
input
|
input
|
CLK,
|
CLK,
|
RESET,
|
RESET,
|
DATA_VALID_IN,
|
DATA_VALID_IN,
|
E_D;
|
E_D;
|
|
|
input [7:0] DATA_IN;
|
input [7:0] DATA_IN;
|
output DATA_VALID_OUT;
|
output DATA_VALID_OUT;
|
output [7:0] DATA_OUT;
|
output [7:0] DATA_OUT;
|
reg DATA_VALID_OUT;
|
reg DATA_VALID_OUT;
|
reg [7:0] DATA_OUT;
|
reg [7:0] DATA_OUT;
|
reg [3:0] cntr1_;
|
reg [3:0] cntr1_;
|
reg [2:0] cntr2_;
|
reg [2:0] cntr2_;
|
reg cntr2_en;
|
reg cntr2_en;
|
reg [7:0] SYND1_;
|
reg [7:0] SYND1_;
|
reg [7:0] SYND2_;
|
reg [7:0] SYND2_;
|
reg [7:0] VAL;
|
reg [7:0] VAL;
|
reg [2:0] LOC2_;
|
reg [2:0] LOC2_;
|
|
|
wire [7:0] MULT2_;
|
wire [7:0] MULT2_;
|
wire [7:0] ADD3_;
|
wire [7:0] ADD3_;
|
wire [2:0] LOC;
|
wire [2:0] LOC;
|
|
|
reg [7:0] FIFO0_;
|
reg [7:0] FIFO0_;
|
reg [7:0] FIFO1_;
|
reg [7:0] FIFO1_;
|
reg [7:0] FIFO2_;
|
reg [7:0] FIFO2_;
|
reg [7:0] FIFO3_;
|
reg [7:0] FIFO3_;
|
reg [7:0] FIFO4_;
|
reg [7:0] FIFO4_;
|
|
|
assign ADD3_ = (E_D) ? (SYND1_ ^ MULT2_) : MULT2_;
|
assign ADD3_ = (E_D) ? (SYND1_ ^ MULT2_) : MULT2_;
|
|
|
MULT_BY_ALPHA51 m0_(.b(SYND2_), .z(MULT2_));
|
MULT_BY_ALPHA51 m0_(.b(SYND2_), .z(MULT2_));
|
SYN2ERR s_( .SYND1_(SYND1_), .SYND2_(SYND2_), .LOC(LOC) );
|
SYN2ERR s_( .SYND1_(SYND1_), .SYND2_(SYND2_), .LOC(LOC) );
|
|
|
///////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////
|
|
|
always@(posedge CLK)
|
always@(posedge CLK)
|
|
|
if (cntr2_en)
|
if (cntr2_en)
|
begin
|
begin
|
VAL<=SYND1_;
|
VAL<=SYND1_;
|
LOC2_<=LOC;
|
LOC2_<=LOC;
|
end
|
end
|
|
|
|
|
|
|
|
|
|
|
///////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////
|
|
|
always@(posedge CLK or negedge RESET)
|
always@(posedge CLK or negedge RESET)
|
|
|
if (!RESET)
|
if (!RESET)
|
|
|
cntr1_<=0;
|
cntr1_<=0;
|
|
|
else
|
else
|
case(cntr1_)
|
case(cntr1_)
|
|
|
0: if (!DATA_VALID_IN)
|
0: if (!DATA_VALID_IN)
|
if (E_D)
|
if (E_D)
|
cntr1_<=1;
|
cntr1_<=1;
|
else
|
else
|
cntr1_<=5;
|
cntr1_<=5;
|
1: if (!DATA_VALID_IN) cntr1_<=2;
|
1: if (!DATA_VALID_IN) cntr1_<=2;
|
2: if (!DATA_VALID_IN) cntr1_<=3;
|
2: if (!DATA_VALID_IN) cntr1_<=3;
|
3: cntr1_<=4;
|
3: cntr1_<=4;
|
4: cntr1_<=0;
|
4: cntr1_<=0;
|
5: if (!DATA_VALID_IN) cntr1_<=6;
|
5: if (!DATA_VALID_IN) cntr1_<=6;
|
6: if (!DATA_VALID_IN) cntr1_<=7;
|
6: if (!DATA_VALID_IN) cntr1_<=7;
|
7: if (!DATA_VALID_IN) cntr1_<=8;
|
7: if (!DATA_VALID_IN) cntr1_<=8;
|
8: cntr1_<=0;
|
8: cntr1_<=0;
|
endcase
|
endcase
|
|
|
|
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
|
|
always@(posedge CLK or negedge RESET)
|
always@(posedge CLK or negedge RESET)
|
if (!RESET)
|
if (!RESET)
|
|
|
cntr2_<=0;
|
cntr2_<=0;
|
|
|
else if (cntr2_==0)
|
else if (cntr2_==0)
|
begin
|
begin
|
if (cntr2_en)
|
if (cntr2_en)
|
cntr2_<=cntr2_+1;
|
cntr2_<=cntr2_+1;
|
end
|
end
|
else if (cntr2_==4)
|
else if (cntr2_==4)
|
cntr2_<=0;
|
cntr2_<=0;
|
else
|
else
|
cntr2_<=cntr2_+1;
|
cntr2_<=cntr2_+1;
|
|
|
|
|
|
|
|
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
|
|
always@(posedge CLK or negedge RESET)
|
always@(posedge CLK or negedge RESET)
|
|
|
if (!RESET)
|
if (!RESET)
|
|
|
DATA_VALID_OUT<=1;
|
DATA_VALID_OUT<=1;
|
|
|
else if ((cntr1_==0)&&(E_D))
|
else if ((cntr1_==0)&&(E_D))
|
|
|
DATA_VALID_OUT<=DATA_VALID_IN;
|
DATA_VALID_OUT<=DATA_VALID_IN;
|
|
|
else if ( (cntr1_==1) || (cntr1_==2) )
|
else if ( (cntr1_==1) || (cntr1_==2) )
|
|
|
DATA_VALID_OUT<=DATA_VALID_IN;
|
DATA_VALID_OUT<=DATA_VALID_IN;
|
|
|
else if ((cntr1_==3) || (cntr1_==4))
|
else if ((cntr1_==3) || (cntr1_==4))
|
|
|
DATA_VALID_OUT<=0;
|
DATA_VALID_OUT<=0;
|
|
|
else if ((cntr2_en) || (cntr2_!=0))
|
else if ((cntr2_en) || (cntr2_!=0))
|
|
|
DATA_VALID_OUT<=0;
|
DATA_VALID_OUT<=0;
|
else
|
else
|
DATA_VALID_OUT<=1;
|
DATA_VALID_OUT<=1;
|
|
|
|
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
|
|
|
|
always@(posedge CLK or negedge RESET)
|
always@(posedge CLK or negedge RESET)
|
|
|
if (!RESET)
|
if (!RESET)
|
|
|
DATA_OUT<=0;
|
DATA_OUT<=0;
|
|
|
else if ((cntr1_==0)&&(E_D))
|
else if ((cntr1_==0)&&(E_D))
|
|
|
DATA_OUT<=DATA_IN;
|
DATA_OUT<=DATA_IN;
|
|
|
else if ( (cntr1_==1) || (cntr1_==2) )
|
else if ( (cntr1_==1) || (cntr1_==2) )
|
|
|
DATA_OUT<=DATA_IN;
|
DATA_OUT<=DATA_IN;
|
|
|
else if ((cntr1_==3) || (cntr1_==4))
|
else if ((cntr1_==3) || (cntr1_==4))
|
|
|
DATA_OUT<=ADD3_;
|
DATA_OUT<=ADD3_;
|
|
|
else if (cntr2_en)
|
else if (cntr2_en)
|
begin
|
begin
|
if(LOC==0)
|
if(LOC==0)
|
DATA_OUT<=FIFO4_ ^ SYND1_;
|
DATA_OUT<=FIFO4_ ^ SYND1_;
|
else
|
else
|
DATA_OUT<=FIFO4_;
|
DATA_OUT<=FIFO4_;
|
|
|
end
|
end
|
else if (cntr2_==LOC2_)
|
else if (cntr2_==LOC2_)
|
|
|
DATA_OUT<=FIFO4_ ^ VAL;
|
DATA_OUT<=FIFO4_ ^ VAL;
|
|
|
else
|
else
|
|
|
DATA_OUT<=FIFO4_;
|
DATA_OUT<=FIFO4_;
|
|
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
|
|
|
|
always@(posedge CLK or negedge RESET)
|
always@(posedge CLK or negedge RESET)
|
|
|
if (!RESET)
|
if (!RESET)
|
begin
|
begin
|
|
|
FIFO0_<=0;
|
FIFO0_<=0;
|
FIFO1_<=0;
|
FIFO1_<=0;
|
FIFO2_<=0;
|
FIFO2_<=0;
|
FIFO3_<=0;
|
FIFO3_<=0;
|
FIFO4_<=0;
|
FIFO4_<=0;
|
|
|
end
|
end
|
else if (((!DATA_VALID_OUT) && (!E_D)) || (cntr1_>=5) || (cntr1_<=8) || (cntr2_en) || (cntr2_!=0) )
|
else if (((!DATA_VALID_OUT) && (!E_D)) || (cntr1_>=5) || (cntr1_<=8) || (cntr2_en) || (cntr2_!=0) )
|
begin
|
begin
|
FIFO4_<=FIFO3_;
|
FIFO4_<=FIFO3_;
|
FIFO3_<=FIFO2_;
|
FIFO3_<=FIFO2_;
|
FIFO2_<=FIFO1_;
|
FIFO2_<=FIFO1_;
|
FIFO1_<=FIFO0_;
|
FIFO1_<=FIFO0_;
|
FIFO0_<=DATA_IN;
|
FIFO0_<=DATA_IN;
|
end
|
end
|
|
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
|
|
always@(posedge CLK or negedge RESET)
|
always@(posedge CLK or negedge RESET)
|
|
|
if (!RESET)
|
if (!RESET)
|
begin
|
begin
|
|
|
SYND1_<=0;
|
SYND1_<=0;
|
SYND2_<=0;
|
SYND2_<=0;
|
|
|
end
|
end
|
|
|
else if ( !DATA_VALID_IN )
|
else if ( !DATA_VALID_IN )
|
begin
|
begin
|
if (cntr1_==0)
|
if (cntr1_==0)
|
begin
|
begin
|
SYND1_<=DATA_IN;
|
SYND1_<=DATA_IN;
|
SYND2_<=DATA_IN;
|
SYND2_<=DATA_IN;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
SYND1_<=SYND1_^ DATA_IN;
|
SYND1_<=SYND1_^ DATA_IN;
|
SYND2_<=ADD3_^ DATA_IN;
|
SYND2_<=ADD3_^ DATA_IN;
|
end
|
end
|
end
|
end
|
else if ( (cntr1_==3) || (cntr1_==4) )
|
else if ( (cntr1_==3) || (cntr1_==4) )
|
|
|
begin
|
begin
|
SYND1_<=SYND1_^ ADD3_;
|
SYND1_<=SYND1_^ ADD3_;
|
SYND2_<=0;
|
SYND2_<=0;
|
end
|
end
|
|
|
|
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
|
|
always@(posedge CLK or negedge RESET)
|
always@(posedge CLK or negedge RESET)
|
|
|
if (!RESET)
|
if (!RESET)
|
|
|
cntr2_en<=0;
|
cntr2_en<=0;
|
|
|
else if (cntr1_==8)
|
else if (cntr1_==8)
|
|
|
cntr2_en<=1;
|
cntr2_en<=1;
|
|
|
else
|
else
|
|
|
cntr2_en<=0;
|
cntr2_en<=0;
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
/******************************************************************/
|
/******************************************************************/
|
/*
|
/*
|
This stimulus file
|
This stimulus file
|
- Creates 256^3 message symbols,
|
- Creates 256^3 message symbols,
|
- Encodes these message symbols into codewords
|
- Encodes these message symbols into codewords
|
- Then decodes them
|
- Then decodes them
|
- And compares the decoded message to the original message.
|
- And compares the decoded message to the original message.
|
- I there is a mismatch then the ERR output of the stimulus file is SET for 1 clock cycle.
|
- I there is a mismatch then the ERR output of the stimulus file is SET for 1 clock cycle.
|
*/
|
*/
|
|
|
|
|
|
|
|
|
module stimulus(
|
module stimulus(
|
CLK,
|
CLK,
|
RESET,
|
RESET,
|
DATA_VALID_IN,
|
DATA_VALID_IN,
|
DATA_IN,
|
DATA_IN,
|
E_D,
|
E_D,
|
ERR,
|
ERR,
|
DATA_VALID_OUT,
|
DATA_VALID_OUT,
|
DATA_OUT);
|
DATA_OUT);
|
|
|
|
|
|
|
input DATA_VALID_OUT;
|
input DATA_VALID_OUT;
|
input [7:0] DATA_OUT;
|
input [7:0] DATA_OUT;
|
output CLK, RESET, E_D, DATA_VALID_IN;
|
output CLK, RESET, E_D, DATA_VALID_IN;
|
output [7:0] DATA_IN;
|
output [7:0] DATA_IN;
|
output ERR;
|
output ERR;
|
|
|
reg ERR;
|
reg ERR;
|
reg [7:0] c4, c3, c2, c1, c0;
|
reg [7:0] c4, c3, c2, c1, c0;
|
reg CLK, RESET, E_D, DATA_VALID_IN;
|
reg CLK, RESET, E_D, DATA_VALID_IN;
|
reg [7:0] DATA_IN;
|
reg [7:0] DATA_IN;
|
|
|
integer i, j, k;
|
integer i, j, k;
|
|
|
RS_5_3_GF256 u0_(
|
RS_5_3_GF256 u0_(
|
.CLK(CLK),
|
.CLK(CLK),
|
.RESET(RESET),
|
.RESET(RESET),
|
.DATA_VALID_IN(DATA_VALID_IN),
|
.DATA_VALID_IN(DATA_VALID_IN),
|
.DATA_IN(DATA_IN),
|
.DATA_IN(DATA_IN),
|
.E_D(E_D),
|
.E_D(E_D),
|
.DATA_OUT(DATA_OUT),
|
.DATA_OUT(DATA_OUT),
|
.DATA_VALID_OUT(DATA_VALID_OUT));
|
.DATA_VALID_OUT(DATA_VALID_OUT));
|
|
|
|
|
///////////////////////// CLK SIGNAL ///////////////////////
|
///////////////////////// CLK SIGNAL ///////////////////////
|
|
|
initial CLK <= 0;
|
initial CLK <= 0;
|
always
|
always
|
begin
|
begin
|
#50
|
#50
|
CLK <= !CLK;
|
CLK <= !CLK;
|
end
|
end
|
|
|
|
|
///////////////////////// RESET SIGNAL ///////////////////////
|
///////////////////////// RESET SIGNAL ///////////////////////
|
|
|
initial
|
initial
|
begin
|
begin
|
RESET <= 0;
|
RESET <= 0;
|
#500
|
#500
|
RESET <= 1;
|
RESET <= 1;
|
end
|
end
|
|
|
|
|
///////////////////////// DATA_VALID_IN & DATA_IN & E_D ///////////////////////
|
///////////////////////// DATA_VALID_IN & DATA_IN & E_D ///////////////////////
|
|
|
initial
|
initial
|
begin
|
begin
|
DATA_VALID_IN<=1;
|
DATA_VALID_IN<=1;
|
E_D<=1;
|
E_D<=1;
|
DATA_IN<=0;
|
DATA_IN<=0;
|
ERR<=0;
|
ERR<=0;
|
#1000
|
#1000
|
|
|
for (i = 80; i < 256; i = i+1)
|
for (i = 80; i < 256; i = i+1)
|
for (j = 0; j < 256; j = j+1)
|
for (j = 0; j < 256; j = j+1)
|
for (k = 0; k < 256; k = k+1)
|
for (k = 0; k < 256; k = k+1)
|
begin
|
begin
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
DATA_VALID_IN<=0;
|
DATA_VALID_IN<=0;
|
E_D<=1;
|
E_D<=1;
|
DATA_IN<=i;
|
DATA_IN<=i;
|
#100
|
#100
|
DATA_IN<=j;
|
DATA_IN<=j;
|
#100
|
#100
|
DATA_IN<=k;
|
DATA_IN<=k;
|
#100
|
#100
|
DATA_IN<=0;
|
DATA_IN<=0;
|
DATA_VALID_IN<=1;
|
DATA_VALID_IN<=1;
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
#100
|
DATA_VALID_IN<=0;
|
DATA_VALID_IN<=0;
|
E_D<=0;
|
E_D<=0;
|
DATA_IN<=c4;
|
DATA_IN<=c4;
|
#100
|
#100
|
DATA_IN<=c3;
|
DATA_IN<=c3;
|
#100
|
#100
|
DATA_IN<=c2;
|
DATA_IN<=c2;
|
#100
|
#100
|
DATA_IN<=c1;
|
DATA_IN<=c1;
|
#100
|
#100
|
DATA_IN<=c0;
|
DATA_IN<=c0;
|
#100
|
#100
|
DATA_VALID_IN<=1;
|
DATA_VALID_IN<=1;
|
|
|
#150
|
#150
|
if (DATA_OUT!=i) begin ERR<=1; end
|
if (DATA_OUT!=i) begin ERR<=1; end
|
#100
|
#100
|
if (DATA_OUT!=j) begin ERR<=1; end
|
if (DATA_OUT!=j) begin ERR<=1; end
|
#100
|
#100
|
if (DATA_OUT!=k) begin ERR<=1; end
|
if (DATA_OUT!=k) begin ERR<=1; end
|
#50
|
#50
|
ERR<=0;
|
ERR<=0;
|
|
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
always@(posedge CLK or negedge RESET)
|
always@(posedge CLK or negedge RESET)
|
|
|
if (!RESET)
|
if (!RESET)
|
begin
|
begin
|
c0<=0;
|
c0<=0;
|
c1<=0;
|
c1<=0;
|
c2<=0;
|
c2<=0;
|
c3<=0;
|
c3<=0;
|
c4<=0;
|
c4<=0;
|
end
|
end
|
else if (!DATA_VALID_OUT)
|
else if (!DATA_VALID_OUT)
|
begin
|
begin
|
c0<=DATA_OUT;
|
c0<=DATA_OUT;
|
c1<=c0;
|
c1<=c0;
|
c2<=c1;
|
c2<=c1;
|
c3<=c2;
|
c3<=c2;
|
c4<=c3;
|
c4<=c3;
|
end
|
end
|
|
|
|
|
|
|
|
|
/////////////////////
|
/////////////////////
|
|
|
|
|
|
|
///////////////////////////////////////////////////////////////// DEC 2
|
///////////////////////////////////////////////////////////////// DEC 2
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
always
|
always
|
begin
|
begin
|
#1000000000
|
#1000000000
|
$finish;
|
$finish;
|
end
|
end
|
endmodule
|
endmodule
|
|
|
|
|
|
|
|
|
|
|
