----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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-- Company:
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-- Company:
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-- Engineer:
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-- Engineer:
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--
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--
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-- Create Date: 20:03:35 11/02/2009
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-- Create Date: 20:03:35 11/02/2009
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-- Design Name:
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-- Design Name:
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-- Module Name: etapas - Behavioral
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-- Module Name: etapas - Behavioral
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-- Project Name:
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-- Project Name:
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-- Target Devices:
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-- Target Devices:
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-- Tool versions:
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-- Tool versions:
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-- Description:
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-- Description:
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity montgomery_mult is
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entity montgomery_mult is
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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valid_in : in std_logic;
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valid_in : in std_logic;
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a : in std_logic_vector(15 downto 0);
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a : in std_logic_vector(15 downto 0);
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b : in std_logic_vector(15 downto 0);
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b : in std_logic_vector(15 downto 0);
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n : in std_logic_vector(15 downto 0);
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n : in std_logic_vector(15 downto 0);
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s_prev : in std_logic_vector(15 downto 0);
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s_prev : in std_logic_vector(15 downto 0);
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n_c : in std_logic_vector(15 downto 0);
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n_c : in std_logic_vector(15 downto 0);
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s : out std_logic_vector( 15 downto 0);
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s : out std_logic_vector( 15 downto 0);
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valid_out : out std_logic -- es le valid out TODO : cambiar nombre
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valid_out : out std_logic -- es le valid out TODO : cambiar nombre
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);
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);
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end montgomery_mult;
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end montgomery_mult;
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architecture Behavioral of montgomery_mult is
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architecture Behavioral of montgomery_mult is
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component montgomery_step is
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component montgomery_step is
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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valid_in : in std_logic;
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valid_in : in std_logic;
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a : in std_logic_vector(15 downto 0);
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a : in std_logic_vector(15 downto 0);
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b : in std_logic_vector(15 downto 0);
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b : in std_logic_vector(15 downto 0);
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n : in std_logic_vector(15 downto 0);
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n : in std_logic_vector(15 downto 0);
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s_prev : in std_logic_vector(15 downto 0);
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s_prev : in std_logic_vector(15 downto 0);
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n_c : in std_logic_vector(15 downto 0);
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n_c : in std_logic_vector(15 downto 0);
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s : out std_logic_vector( 15 downto 0);
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s : out std_logic_vector( 15 downto 0);
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valid_out : out std_logic; -- es le valid out TODO : cambiar nombre
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valid_out : out std_logic; -- es le valid out TODO : cambiar nombre
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busy : out std_logic;
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busy : out std_logic;
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b_req : out std_logic;
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b_req : out std_logic;
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a_out : out std_logic_vector(15 downto 0);
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a_out : out std_logic_vector(15 downto 0);
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n_out : out std_logic_vector(15 downto 0); --seńal que indica que el modulo está ocupado y no puede procesar nuevas peticiones
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n_out : out std_logic_vector(15 downto 0); --seńal que indica que el modulo está ocupado y no puede procesar nuevas peticiones
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c_step : out std_logic; --genera un pulso cuando termina su computo para avisar al modulo superior
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c_step : out std_logic; --genera un pulso cuando termina su computo para avisar al modulo superior
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stop : in std_logic
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stop : in std_logic
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);
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);
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end component;
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end component;
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component fifo_512_bram
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component fifo_512_bram
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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din : in std_logic_vector(15 downto 0);
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din : in std_logic_vector(15 downto 0);
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wr_en : in std_logic;
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wr_en : in std_logic;
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rd_en : in std_logic;
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rd_en : in std_logic;
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dout : out std_logic_vector(15 downto 0);
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dout : out std_logic_vector(15 downto 0);
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full : out std_logic;
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full : out std_logic;
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empty : out std_logic);
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empty : out std_logic);
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end component;
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end component;
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component fifo_256_feedback
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component fifo_256_feedback
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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din : in std_logic_vector(48 downto 0);
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din : in std_logic_vector(48 downto 0);
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wr_en : in std_logic;
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wr_en : in std_logic;
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rd_en : in std_logic;
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rd_en : in std_logic;
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dout : out std_logic_vector(48 downto 0);
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dout : out std_logic_vector(48 downto 0);
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full : out std_logic;
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full : out std_logic;
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empty : out std_logic);
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empty : out std_logic);
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end component;
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end component;
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type arr_dat_out is array(0 to 7) of std_logic_vector(15 downto 0);
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type arr_dat_out is array(0 to 7) of std_logic_vector(15 downto 0);
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type arr_val is array(0 to 7) of std_logic;
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type arr_val is array(0 to 7) of std_logic;
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type arr_b is array(0 to 7) of std_logic_vector(15 downto 0);
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type arr_b is array(0 to 7) of std_logic_vector(15 downto 0);
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signal b_reg, next_b_reg : arr_b;
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signal b_reg, next_b_reg : arr_b;
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signal valid_mid, fifo_reqs, fifo_reqs_reg, next_fifo_reqs_reg, stops : arr_val;
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signal valid_mid, fifo_reqs, fifo_reqs_reg, next_fifo_reqs_reg, stops : arr_val;
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signal a_out_mid, n_out_mid, s_out_mid : arr_dat_out; --std_logic_vector(15 downto 0);
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signal a_out_mid, n_out_mid, s_out_mid : arr_dat_out; --std_logic_vector(15 downto 0);
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--Seńales a la fifo
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--Seńales a la fifo
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signal wr_en, rd_en, empty : std_logic;
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signal wr_en, rd_en, empty : std_logic;
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signal fifo_out : std_logic_vector(15 downto 0);
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signal fifo_out : std_logic_vector(15 downto 0);
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signal fifo_out_feedback, fifo_in_feedback : std_logic_vector(48 downto 0);
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signal fifo_out_feedback, fifo_in_feedback : std_logic_vector(48 downto 0);
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signal read_fifo_feedback, empty_feedback : std_logic;
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signal read_fifo_feedback, empty_feedback : std_logic;
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--Seńales de entrada al primer PE
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--Seńales de entrada al primer PE
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signal a_in, s_in, n_in : std_logic_vector(15 downto 0);
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signal a_in, s_in, n_in : std_logic_vector(15 downto 0);
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signal f_valid, busy_pe : std_logic;
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signal f_valid, busy_pe : std_logic;
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--salida c_step del primer PE para ir contando y saber cuando sacar el valor correcto.
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--salida c_step del primer PE para ir contando y saber cuando sacar el valor correcto.
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signal c_step, reg_c_step : std_logic;
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signal c_step, reg_c_step : std_logic;
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--contador para saber cuando cońo acabamos :)
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--contador para saber cuando cońo acabamos :)
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signal count, next_count : std_logic_vector(7 downto 0);
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signal count, next_count : std_logic_vector(7 downto 0);
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--seńal para escribir el loopback en la fifo de entrada de feedback
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--seńal para escribir el loopback en la fifo de entrada de feedback
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signal wr_fifofeed : std_logic;
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signal wr_fifofeed : std_logic;
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type state_type is (wait_start, process_data, dump_feed);
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type state_type is (rst_fifos,wait_start, process_data, dump_feed);
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signal state, next_state : state_type;
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signal state, next_state : state_type;
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signal reg_busy : std_logic;
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signal reg_busy : std_logic;
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signal reset_fifos : std_logic;
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signal reset_fifos : std_logic;
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signal count_feedback, next_count_feedback : std_logic_vector(15 downto 0);
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signal count_feedback, next_count_feedback : std_logic_vector(15 downto 0);
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begin
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begin
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--Fifo para almacenar b
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--Fifo para almacenar b
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fifo_b : fifo_512_bram port map (
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fifo_b : fifo_512_bram port map (
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clk => clk,
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clk => clk,
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rst => reset_fifos,
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rst => reset_fifos,
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din => b,
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din => b,
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wr_en => wr_en,
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wr_en => wr_en,
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rd_en => rd_en,
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rd_en => rd_en,
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dout => fifo_out,
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dout => fifo_out,
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empty => empty
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empty => empty
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);
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);
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--Fifo para el feedback al primer PE
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--Fifo para el feedback al primer PE
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fifo_feed : fifo_256_feedback port map (
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fifo_feed : fifo_256_feedback port map (
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clk => clk,
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clk => clk,
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rst => reset_fifos,
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rst => reset_fifos,
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din => fifo_in_feedback,
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din => fifo_in_feedback,
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wr_en => wr_fifofeed,
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wr_en => wr_fifofeed,
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rd_en => read_fifo_feedback,
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rd_en => read_fifo_feedback,
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dout => fifo_out_feedback,
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dout => fifo_out_feedback,
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empty => empty_feedback
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empty => empty_feedback
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);
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);
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--Primer PE
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--Primer PE
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et_first : montgomery_step port map(
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et_first : montgomery_step port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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valid_in => f_valid,
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valid_in => f_valid,
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a => a_in,
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a => a_in,
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b => b_reg(0),
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b => b_reg(0),
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n => n_in,
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n => n_in,
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s_prev => s_in,
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s_prev => s_in,
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n_c => n_c,
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n_c => n_c,
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s => s_out_mid(0),
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s => s_out_mid(0),
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valid_out => valid_mid(0),
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valid_out => valid_mid(0),
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busy => busy_pe,
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busy => busy_pe,
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b_req => fifo_reqs(0),
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b_req => fifo_reqs(0),
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a_out => a_out_mid(0),
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a_out => a_out_mid(0),
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n_out => n_out_mid(0),
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n_out => n_out_mid(0),
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c_step => c_step,
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c_step => c_step,
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stop => stops(0)
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stop => stops(0)
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);
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);
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--Ultimo PE
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--Ultimo PE
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et_last : montgomery_step port map(
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et_last : montgomery_step port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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valid_in => valid_mid(6),
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valid_in => valid_mid(6),
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a => a_out_mid(6),
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a => a_out_mid(6),
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b => b_reg(7),
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b => b_reg(7),
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n => n_out_mid(6),
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n => n_out_mid(6),
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s_prev => s_out_mid(6),
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s_prev => s_out_mid(6),
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n_c => n_c,
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n_c => n_c,
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s => s_out_mid(7),
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s => s_out_mid(7),
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valid_out => valid_mid(7),
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valid_out => valid_mid(7),
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b_req => fifo_reqs(7),
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b_req => fifo_reqs(7),
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a_out => a_out_mid(7),
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a_out => a_out_mid(7),
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n_out => n_out_mid(7),
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n_out => n_out_mid(7),
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stop => stops(7)
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stop => stops(7)
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);
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);
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g1 : for i in 1 to 6 generate
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g1 : for i in 1 to 6 generate
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et_i : montgomery_step port map(
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et_i : montgomery_step port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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valid_in => valid_mid(i-1),
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valid_in => valid_mid(i-1),
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a => a_out_mid(i-1),
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a => a_out_mid(i-1),
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b => b_reg(i),
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b => b_reg(i),
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n => n_out_mid(i-1),
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n => n_out_mid(i-1),
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s_prev => s_out_mid(i-1),
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s_prev => s_out_mid(i-1),
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n_c => n_c,
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n_c => n_c,
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s => s_out_mid(i),
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s => s_out_mid(i),
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valid_out => valid_mid(i),
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valid_out => valid_mid(i),
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b_req => fifo_reqs(i),
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b_req => fifo_reqs(i),
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a_out => a_out_mid(i),
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a_out => a_out_mid(i),
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n_out => n_out_mid(i),
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n_out => n_out_mid(i),
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stop => stops(i)
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stop => stops(i)
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);
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);
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end generate g1;
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end generate g1;
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process(clk, reset)
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process(clk, reset)
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begin
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begin
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if(clk = '1' and clk'event) then
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if(clk = '1' and clk'event) then
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if(reset = '1')then
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if(reset = '1')then
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state <= wait_start;
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state <= wait_start;
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count_feedback <= (others => '0');
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count_feedback <= (others => '0');
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reg_busy <= '0';
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reg_busy <= '0';
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for i in 0 to 7 loop
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for i in 0 to 7 loop
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b_reg(i) <= (others => '0');
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b_reg(i) <= (others => '0');
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fifo_reqs_reg (i) <= '0';
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fifo_reqs_reg (i) <= '0';
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count <= (others => '0');
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count <= (others => '0');
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reg_c_step <= '0';
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reg_c_step <= '0';
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end loop;
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end loop;
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else
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else
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state <= next_state;
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state <= next_state;
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reg_busy <= busy_pe;
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reg_busy <= busy_pe;
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count_feedback <= next_count_feedback;
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count_feedback <= next_count_feedback;
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for i in 0 to 7 loop
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for i in 0 to 7 loop
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b_reg(i) <= next_b_reg(i);
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b_reg(i) <= next_b_reg(i);
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fifo_reqs_reg (i) <= next_fifo_reqs_reg(i);
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fifo_reqs_reg (i) <= next_fifo_reqs_reg(i);
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count <= next_count;
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count <= next_count;
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reg_c_step <= c_step;
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reg_c_step <= c_step;
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end loop;
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end loop;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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--Proceso combinacional que controla las lecturas a la fifo
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--Proceso combinacional que controla las lecturas a la fifo
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process(fifo_reqs_reg, fifo_out, b, fifo_reqs, b_reg, state, empty)
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process(fifo_reqs_reg, fifo_out, b, fifo_reqs, b_reg, state, empty)
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begin
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begin
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for i in 0 to 7 loop
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for i in 0 to 7 loop
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next_b_reg(i) <= b_reg(i);
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next_b_reg(i) <= b_reg(i);
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next_fifo_reqs_reg(i) <= fifo_reqs(i);
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next_fifo_reqs_reg(i) <= fifo_reqs(i);
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end loop;
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end loop;
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if(state = wait_start) then
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if(state = wait_start) then
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next_b_reg(0) <= b;
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next_b_reg(0) <= b;
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next_fifo_reqs_reg(0) <= '0'; --anulamos la peticion de b
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next_fifo_reqs_reg(0) <= '0'; --anulamos la peticion de b
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for i in 1 to 7 loop
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for i in 1 to 7 loop
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next_b_reg(i) <= (others => '0');
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next_b_reg(i) <= (others => '0');
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next_fifo_reqs_reg(i) <= '0';
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next_fifo_reqs_reg(i) <= '0';
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end loop;
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end loop;
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else
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else
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for i in 0 to 7 loop
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for i in 0 to 7 loop
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if(fifo_reqs_reg(i) = '1' and empty = '0') then
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if(fifo_reqs_reg(i) = '1' and empty = '0') then
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next_b_reg(i) <= fifo_out;
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next_b_reg(i) <= fifo_out;
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end if;
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end if;
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end loop;
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end loop;
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end if;
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end if;
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end process;
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end process;
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--Proceso combinacional fsm principal
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--Proceso combinacional fsm principal
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process( valid_in, b, state, fifo_reqs, a_out_mid, n_out_mid, s_out_mid, valid_mid, a, s_prev, n, busy_pe, empty_feedback, fifo_out_feedback, count, reg_c_step, reset, reg_busy, count_feedback )
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process( valid_in, b, state, fifo_reqs, a_out_mid, n_out_mid, s_out_mid, valid_mid, a, s_prev, n, busy_pe, empty_feedback, fifo_out_feedback, count, reg_c_step, reset, reg_busy, count_feedback )
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begin
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begin
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--las peticiones a la fifo son las or de los modulos
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--las peticiones a la fifo son las or de los modulos
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rd_en <= fifo_reqs(0) or fifo_reqs(1) or fifo_reqs(2) or fifo_reqs(3) or fifo_reqs(4) or fifo_reqs(5) or fifo_reqs(6) or fifo_reqs(7);
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rd_en <= fifo_reqs(0) or fifo_reqs(1) or fifo_reqs(2) or fifo_reqs(3) or fifo_reqs(4) or fifo_reqs(5) or fifo_reqs(6) or fifo_reqs(7);
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next_state <= state;
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next_state <= state;
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wr_en <= '0';
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wr_en <= '0';
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fifo_in_feedback <= a_out_mid(7)&n_out_mid(7)&s_out_mid(7)&valid_mid(7);
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fifo_in_feedback <= a_out_mid(7)&n_out_mid(7)&s_out_mid(7)&valid_mid(7);
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read_fifo_feedback <= '0';
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read_fifo_feedback <= '0';
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wr_fifofeed <= '0';
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wr_fifofeed <= '0';
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--Controlamos el primer PE
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--Controlamos el primer PE
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a_in <= a;
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a_in <= a;
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s_in <= s_prev;
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s_in <= s_prev;
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n_in <= n;
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n_in <= n;
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f_valid <= valid_in;
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f_valid <= valid_in;
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reset_fifos <= reset;
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reset_fifos <= reset;
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--ponemos las salidas
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--ponemos las salidas
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s <= (others => '0');
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s <= (others => '0');
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valid_out <= '0';
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valid_out <= '0';
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--Incrementamos el contador solo cuando el primer PE termina su cuenta
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--Incrementamos el contador solo cuando el primer PE termina su cuenta
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next_count <= count;
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next_count <= count;
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next_count_feedback <= count_feedback;
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next_count_feedback <= count_feedback;
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--El contador solo se incrementa una vez por ciclo de la pipeline, así me evito que cada PE lo incremente
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--El contador solo se incrementa una vez por ciclo de la pipeline, así me evito que cada PE lo incremente
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if(reg_c_step = '1') then
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if(reg_c_step = '1') then
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next_count <= count + 8;
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next_count <= count + 8;
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end if;
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end if;
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--durante el ciclo de la pipeline que sea considerado el ultimo, sacamos los datos
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--durante el ciclo de la pipeline que sea considerado el ultimo, sacamos los datos
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if( count = x"20") then
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if( count = x"20") then
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s <= s_out_mid(0);
|
s <= s_out_mid(0);
|
valid_out <= valid_mid(0);
|
valid_out <= valid_mid(0);
|
end if;
|
end if;
|
|
|
for i in 0 to 7 loop
|
for i in 0 to 7 loop
|
stops(i) <= '0';
|
stops(i) <= '0';
|
end loop;
|
end loop;
|
|
|
case state is
|
case state is
|
--Esperamos a que tengamos un input y vamos cargando las b's
|
--Esperamos a que tengamos un input y vamos cargando las b's
|
when wait_start =>
|
when wait_start =>
|
reset_fifos <= '1';
|
--reset_fifos <= '1';
|
if(valid_in = '1') then
|
if(valid_in = '1') then
|
reset_fifos <= '0';
|
reset_fifos <= '0';
|
--next_b_reg(0) <= b;
|
--next_b_reg(0) <= b;
|
next_state <= process_data;
|
next_state <= process_data;
|
--wr_en <= '1';
|
--wr_en <= '1';
|
end if;
|
end if;
|
|
|
when process_data =>
|
when process_data =>
|
wr_fifofeed <= valid_mid(7);
|
wr_fifofeed <= valid_mid(7);
|
if(valid_in = '1') then
|
if(valid_in = '1') then
|
wr_en <= '1';
|
wr_en <= '1';
|
end if;
|
end if;
|
--Miramos si hay que volver a meter datos a la b
|
--Miramos si hay que volver a meter datos a la b
|
if(empty_feedback = '0' and reg_busy = '0') then
|
if(empty_feedback = '0' and reg_busy = '0') then
|
read_fifo_feedback <= '1';
|
read_fifo_feedback <= '1';
|
next_state <= dump_feed;
|
next_state <= dump_feed;
|
next_count_feedback <= x"0000";
|
next_count_feedback <= x"0000";
|
end if;
|
end if;
|
|
|
--Si ya hemos sobrepasado el limite paramos y volvemos a la espera
|
--Si ya hemos sobrepasado el limite paramos y volvemos a la espera
|
if( count > x"23") then
|
if( count > x"23") then
|
next_state <= wait_start;
|
next_state <= wait_start;
|
--y
|
--y
|
for i in 0 to 7 loop
|
for i in 0 to 7 loop
|
stops(i) <= '1';
|
stops(i) <= '1';
|
end loop;
|
end loop;
|
next_count <= (others => '0');
|
next_count <= (others => '0');
|
end if;
|
end if;
|
|
|
--Vacia la fifo de feedback
|
--Vacia la fifo de feedback
|
when dump_feed =>
|
when dump_feed =>
|
if(empty_feedback='0')
|
if(empty_feedback='0')
|
then
|
then
|
next_count_feedback <= count_feedback+1;
|
next_count_feedback <= count_feedback+1;
|
end if;
|
end if;
|
wr_fifofeed <= valid_mid(7);
|
wr_fifofeed <= valid_mid(7);
|
read_fifo_feedback <= '1';
|
read_fifo_feedback <= '1';
|
a_in <= fifo_out_feedback(48 downto 33);
|
a_in <= fifo_out_feedback(48 downto 33);
|
n_in <= fifo_out_feedback(32 downto 17);
|
n_in <= fifo_out_feedback(32 downto 17);
|
s_in <= fifo_out_feedback(16 downto 1);
|
s_in <= fifo_out_feedback(16 downto 1);
|
f_valid <= fifo_out_feedback(0);
|
f_valid <= fifo_out_feedback(0);
|
if(empty_feedback='1') then
|
if(empty_feedback='1') then
|
next_state <= process_data;
|
next_state <= process_data;
|
|
|
end if;
|
end if;
|
if(count_feedback = x"22") then
|
if(count_feedback = x"22") then
|
read_fifo_feedback <= '0';
|
read_fifo_feedback <= '0';
|
next_state <= process_data;
|
next_state <= process_data;
|
end if;
|
end if;
|
|
when rst_fifos =>
|
|
next_state <= wait_start;
|
|
reset_fifos <= '1';
|
end case;
|
end case;
|
|
|
end process;
|
end process;
|
end Behavioral;
|
end Behavioral;
|
|
|
|
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