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----------------------------------------------------------------------------------
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-- Company:
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-- Company:
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-- Engineer:
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-- Engineer:
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--
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--
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-- Create Date: 10:40:41 11/01/2009
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-- Create Date: 10:40:41 11/01/2009
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-- Design Name:
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-- Design Name:
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-- Module Name: module_with_fifo - Behavioral
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-- Module Name: module_with_fifo - Behavioral
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-- Project Name:
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-- Project Name:
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-- Target Devices:
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-- Target Devices:
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-- Tool versions:
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-- Tool versions:
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-- Description:
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-- Description:
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity montgomery_step is
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entity montgomery_step is
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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valid_in : in std_logic;
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valid_in : in std_logic;
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a : in std_logic_vector(15 downto 0);
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a : in std_logic_vector(15 downto 0);
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b : in std_logic_vector(15 downto 0);
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b : in std_logic_vector(15 downto 0);
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n : in std_logic_vector(15 downto 0);
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n : in std_logic_vector(15 downto 0);
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s_prev : in std_logic_vector(15 downto 0);
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s_prev : in std_logic_vector(15 downto 0);
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n_c : in std_logic_vector(15 downto 0);
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n_c : in std_logic_vector(15 downto 0);
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s : out std_logic_vector( 15 downto 0);
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s : out std_logic_vector( 15 downto 0);
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valid_out : out std_logic; -- es le valid out TODO : cambiar nombre
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valid_out : out std_logic; -- es le valid out TODO : cambiar nombre
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busy : out std_logic;
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busy : out std_logic;
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b_req : out std_logic;
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b_req : out std_logic;
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a_out : out std_logic_vector(15 downto 0);
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a_out : out std_logic_vector(15 downto 0);
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n_out : out std_logic_vector(15 downto 0); --seńal que indica que el modulo está ocupado y no puede procesar nuevas peticiones
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n_out : out std_logic_vector(15 downto 0); --seńal que indica que el modulo está ocupado y no puede procesar nuevas peticiones
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c_step : out std_logic; --genera un pulso cuando termina su computo para avisar al modulo superior
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c_step : out std_logic; --genera un pulso cuando termina su computo para avisar al modulo superior
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stop : in std_logic
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stop : in std_logic
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);
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);
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end montgomery_step;
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end montgomery_step;
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architecture Behavioral of montgomery_step is
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architecture Behavioral of montgomery_step is
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component pe_wrapper
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component pe_wrapper
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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ab_valid : in std_logic;
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ab_valid : in std_logic;
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valid_in : in std_logic;
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valid_in : in std_logic;
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a : in std_logic_vector(15 downto 0);
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a : in std_logic_vector(15 downto 0);
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b : in std_logic_vector(15 downto 0);
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b : in std_logic_vector(15 downto 0);
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n : in std_logic_vector(15 downto 0);
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n : in std_logic_vector(15 downto 0);
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s_prev : in std_logic_vector(15 downto 0);
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s_prev : in std_logic_vector(15 downto 0);
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n_c : in std_logic_vector(15 downto 0);
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n_c : in std_logic_vector(15 downto 0);
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s : out std_logic_vector( 15 downto 0);
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s : out std_logic_vector( 15 downto 0);
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data_ready : out std_logic;
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data_ready : out std_logic;
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fifo_req : out std_logic;
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fifo_req : out std_logic;
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m_val : out std_logic;
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m_val : out std_logic;
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reset_the_PE : in std_logic); -- estamos preparados para aceptar el siguiente dato
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reset_the_PE : in std_logic); -- estamos preparados para aceptar el siguiente dato
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end component;
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end component;
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--Inputs
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--Inputs
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signal ab_valid : std_logic;
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signal ab_valid : std_logic;
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signal valid_mont, fifo_read, m_val, valid_mont_out, reset_pe : std_logic;
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signal valid_mont, fifo_read, m_val, valid_mont_out, reset_pe : std_logic;
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--Outputs
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--Outputs
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--definimos los estados
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--definimos los estados
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type state_type is (wait_valid, wait_m, mont_proc, getting_results, prep_m, b_stable);
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type state_type is (wait_valid, wait_m, mont_proc, getting_results, prep_m, b_stable);
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signal state, next_state : state_type;
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signal state, next_state : state_type;
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signal counter, next_counter : std_logic_vector(7 downto 0); -- cuenta las palabras que han salido para ir cortando
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signal counter, next_counter : std_logic_vector(7 downto 0); -- cuenta las palabras que han salido para ir cortando
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--Seńales nuevas
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--Seńales nuevas
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signal mont_input_a, mont_input_n, mont_input_s : std_logic_vector(15 downto 0);
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signal mont_input_a, mont_input_n, mont_input_s : std_logic_vector(15 downto 0);
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signal reg_constant, next_reg_constant, next_reg_input, reg_input : std_logic_vector(47 downto 0);
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signal reg_constant, next_reg_constant, next_reg_input, reg_input : std_logic_vector(47 downto 0);
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signal reg_out, reg_out_1, reg_out_2, reg_out_3, reg_out_4 : std_logic_vector(31 downto 0);
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signal reg_out, reg_out_1, reg_out_2, reg_out_3, reg_out_4 : std_logic_vector(31 downto 0);
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signal next_reg_out : std_logic_vector(31 downto 0);
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signal next_reg_out : std_logic_vector(31 downto 0);
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--Cadena de registros hacia fuera
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--Cadena de registros hacia fuera
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signal reg_input_1, reg_input_2, reg_input_3, reg_input_4, reg_input_5 : std_logic_vector(47 downto 0);
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signal reg_input_1, reg_input_2, reg_input_3, reg_input_4, reg_input_5 : std_logic_vector(47 downto 0);
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begin
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begin
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mont : pe_wrapper port map (
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mont : pe_wrapper port map (
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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ab_valid => ab_valid,
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ab_valid => ab_valid,
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a => mont_input_a,
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a => mont_input_a,
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b => b,
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b => b,
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n => mont_input_n,
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n => mont_input_n,
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s_prev => mont_input_s,
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s_prev => mont_input_s,
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n_c => n_c,
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n_c => n_c,
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s => s,
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s => s,
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valid_in => valid_mont,
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valid_in => valid_mont,
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data_ready => valid_mont_out,
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data_ready => valid_mont_out,
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m_val => m_val,
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m_val => m_val,
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reset_the_PE => reset_pe
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reset_the_PE => reset_pe
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);
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);
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process(clk, reset)
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process(clk, reset)
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begin
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begin
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if(clk = '1' and clk'event) then
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if(clk = '1' and clk'event) then
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if(reset = '1')then
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if(reset = '1')then
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state <= wait_valid;
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state <= wait_valid;
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counter <= (others => '0');
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counter <= (others => '0');
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reg_constant <= (others => '0');
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reg_constant <= (others => '0');
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reg_input <= (others => '0');
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reg_input <= (others => '0');
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reg_input_1 <= (others => '0');
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reg_input_1 <= (others => '0');
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reg_input_2 <= (others => '0');
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reg_input_2 <= (others => '0');
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reg_input_3 <= (others => '0');
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reg_input_3 <= (others => '0');
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reg_input_4 <= (others => '0');
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reg_input_4 <= (others => '0');
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reg_out <= (others => '0');
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reg_out <= (others => '0');
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reg_out_1 <= (others => '0');
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reg_out_1 <= (others => '0');
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reg_out_2 <= (others => '0');
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reg_out_2 <= (others => '0');
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reg_out_3 <= (others => '0');
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reg_out_3 <= (others => '0');
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reg_out_4 <= (others => '0');
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reg_out_4 <= (others => '0');
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else
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else
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reg_input <= next_reg_input;
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reg_input <= next_reg_input;
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reg_input_1 <= reg_input;
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reg_input_1 <= reg_input;
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reg_input_2 <= reg_input_1;
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reg_input_2 <= reg_input_1;
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reg_input_3 <= reg_input_2;
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reg_input_3 <= reg_input_2;
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reg_input_4 <= reg_input_3;
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reg_input_4 <= reg_input_3;
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reg_input_5 <= reg_input_4;
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reg_input_5 <= reg_input_4;
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reg_out <= reg_input_4(47 downto 32) & reg_input_4(31 downto 16);
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reg_out <= reg_input_4(47 downto 32) & reg_input_4(31 downto 16);
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reg_out_1 <= reg_out;
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reg_out_1 <= reg_out;
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reg_out_2 <= reg_out_1;
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reg_out_2 <= reg_out_1;
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reg_out_3 <= reg_out_2;
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reg_out_3 <= reg_out_2;
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reg_out_4 <= reg_out_3;
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reg_out_4 <= reg_out_3;
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state <= next_state;
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state <= next_state;
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counter <= next_counter;
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counter <= next_counter;
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reg_constant <= next_reg_constant;
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reg_constant <= next_reg_constant;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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process(state, valid_in, m_val, a, n, s_prev, counter, valid_mont_out, stop, reg_constant, reg_input_5, reg_out_4)
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process(state, valid_in, m_val, a, n, s_prev, counter, valid_mont_out, stop, reg_constant, reg_input_5, reg_out_4)
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begin
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begin
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--reset_fifo <= '0';
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--reset_fifo <= '0';
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next_reg_input <= a&n&s_prev; --Propagación de la entrada TODO add variable
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next_reg_input <= a&n&s_prev; --Propagación de la entrada TODO add variable
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--next_reg_out <= a&n; --Vamos retrasando la entrada TODO add variable
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--next_reg_out <= a&n; --Vamos retrasando la entrada TODO add variable
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a_out <= reg_out_4(31 downto 16);
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a_out <= reg_out_4(31 downto 16);
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n_out <= reg_out_4(15 downto 0);
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n_out <= reg_out_4(15 downto 0);
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next_state <= state;
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next_state <= state;
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next_counter <= counter;
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next_counter <= counter;
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--write_fifos <= valid_in;
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--write_fifos <= valid_in;
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ab_valid <= '0';
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ab_valid <= '0';
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valid_mont <= '0';
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valid_mont <= '0';
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valid_out <= '0';
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valid_out <= '0';
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reset_pe <= '0';
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reset_pe <= '0';
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busy <= '1';
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busy <= '1';
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b_req <= '0';
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b_req <= '0';
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c_step <= '0';
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c_step <= '0';
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--Todo esto es nuevo
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--Todo esto es nuevo
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mont_input_a <= (others => '0');
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mont_input_a <= (others => '0');
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mont_input_n <= (others => '0');
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mont_input_n <= (others => '0');
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mont_input_s <= (others => '0');
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mont_input_s <= (others => '0');
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next_reg_constant <= reg_constant;
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next_reg_constant <= reg_constant;
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case state is
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case state is
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when wait_valid =>
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when wait_valid =>
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busy <= '0'; --esperamos la peticion
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busy <= '0'; --esperamos la peticion
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reset_pe <= '1';
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reset_pe <= '1';
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if(valid_in = '1') then
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if(valid_in = '1') then
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b_req <= '1'; --Solicitamos al modulo externo la b
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b_req <= '1'; --Solicitamos al modulo externo la b
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next_state <= b_stable;
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next_state <= b_stable;
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next_reg_constant <= a&n&s_prev; --TODO add variable
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next_reg_constant <= a&n&s_prev; --TODO add variable
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end if;
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end if;
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when b_stable =>
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when b_stable =>
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next_state <= prep_m;
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next_state <= prep_m;
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when prep_m =>
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when prep_m =>
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mont_input_a <= reg_constant(47 downto 32); --TODO add this to sensitivity
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mont_input_a <= reg_constant(47 downto 32); --TODO add this to sensitivity
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mont_input_n <= reg_constant(31 downto 16);
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mont_input_n <= reg_constant(31 downto 16);
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mont_input_s <= reg_constant(15 downto 0);
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mont_input_s <= reg_constant(15 downto 0);
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ab_valid <= '1';
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ab_valid <= '1';
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next_state <= wait_m;
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next_state <= wait_m;
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when wait_m =>
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when wait_m =>
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--Mantenemos las entradas para que nos calcule m correctamente
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--Mantenemos las entradas para que nos calcule m correctamente
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mont_input_a <= reg_constant(47 downto 32); --TODO add this to sensitivity
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mont_input_a <= reg_constant(47 downto 32); --TODO add this to sensitivity
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mont_input_n <= reg_constant(31 downto 16);
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mont_input_n <= reg_constant(31 downto 16);
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mont_input_s <= reg_constant(15 downto 0);
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mont_input_s <= reg_constant(15 downto 0);
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if (m_val = '1') then
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if (m_val = '1') then
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valid_mont <= '1';
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valid_mont <= '1';
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next_state <= mont_proc;
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next_state <= mont_proc;
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mont_input_a <= reg_input_5(47 downto 32);
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mont_input_a <= reg_input_5(47 downto 32);
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mont_input_n <= reg_input_5(31 downto 16);
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mont_input_n <= reg_input_5(31 downto 16);
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mont_input_s <= reg_input_5(15 downto 0);
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mont_input_s <= reg_input_5(15 downto 0);
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end if;
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end if;
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when mont_proc =>
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when mont_proc =>
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valid_mont <= '1';
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valid_mont <= '1';
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mont_input_a <= reg_input_5(47 downto 32);
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mont_input_a <= reg_input_5(47 downto 32);
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mont_input_n <= reg_input_5(31 downto 16);
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mont_input_n <= reg_input_5(31 downto 16);
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mont_input_s <= reg_input_5(15 downto 0);
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mont_input_s <= reg_input_5(15 downto 0);
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if(valid_mont_out = '1') then
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if(valid_mont_out = '1') then
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next_counter <= x"00";
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next_counter <= x"00";
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next_state <= getting_results;
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next_state <= getting_results;
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end if;
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end if;
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when getting_results =>
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when getting_results =>
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valid_out <= '1';
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valid_out <= '1';
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next_counter <= counter+1;
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next_counter <= counter+1;
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valid_mont <= '1';
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valid_mont <= '1';
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mont_input_a <= reg_input_5(47 downto 32);
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mont_input_a <= reg_input_5(47 downto 32);
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mont_input_n <= reg_input_5(31 downto 16);
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mont_input_n <= reg_input_5(31 downto 16);
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mont_input_s <= reg_input_5(15 downto 0);
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mont_input_s <= reg_input_5(15 downto 0);
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if(counter = (x"22")) then
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if(counter = (x"22")) then
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next_state <= wait_valid;
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next_state <= wait_valid;
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c_step <= '1';
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c_step <= '1';
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reset_pe <= '1';
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reset_pe <= '1';
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end if;
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end if;
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end case;
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end case;
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if(stop='1') then
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if(stop = '1') then
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next_state <= wait_valid;
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next_state <= wait_valid;
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--reset_fifo <= '1';
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--reset_fifo <= '1';
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reset_pe <= '1';
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reset_pe <= '1';
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end if;
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end if;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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