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----------------------------------------------------------------------------------
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-- Company:
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-- Company:
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-- Engineer:
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-- Engineer:
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--
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--
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-- Create Date: 19:08:19 10/29/2009
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-- Create Date: 19:08:19 10/29/2009
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-- Design Name:
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-- Design Name:
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-- Module Name: montgomery - Behavioral
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-- Module Name: montgomery - Behavioral
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-- Project Name:
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-- Project Name:
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-- Target Devices:
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-- Target Devices:
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-- Tool versions:
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-- Tool versions:
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-- Description:
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-- Description:
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity pe_wrapper is
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entity pe_wrapper is
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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ab_valid : in std_logic;
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ab_valid : in std_logic;
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valid_in : in std_logic;
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valid_in : in std_logic;
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a : in std_logic_vector(15 downto 0);
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a : in std_logic_vector(15 downto 0);
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b : in std_logic_vector(15 downto 0);
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b : in std_logic_vector(15 downto 0);
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n : in std_logic_vector(15 downto 0);
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n : in std_logic_vector(15 downto 0);
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s_prev : in std_logic_vector(15 downto 0);
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s_prev : in std_logic_vector(15 downto 0);
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n_c : in std_logic_vector(15 downto 0);
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n_c : in std_logic_vector(15 downto 0);
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s : out std_logic_vector( 15 downto 0);
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s : out std_logic_vector( 15 downto 0);
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data_ready : out std_logic;
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data_ready : out std_logic;
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fifo_req : out std_logic;
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fifo_req : out std_logic;
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m_val : out std_logic;
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m_val : out std_logic;
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reset_the_PE : in std_logic); -- estamos preparados para aceptar el siguiente dato
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reset_the_PE : in std_logic); -- estamos preparados para aceptar el siguiente dato
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end pe_wrapper;
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end pe_wrapper;
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architecture Behavioral of pe_wrapper is
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architecture Behavioral of pe_wrapper is
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component pe is
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component pe is
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port ( clk : in std_logic;
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port ( clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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a_j : in std_logic_vector(15 downto 0);
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a_j : in std_logic_vector(15 downto 0);
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b_i : in std_logic_vector(15 downto 0);
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b_i : in std_logic_vector(15 downto 0);
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s_prev : in std_logic_vector(15 downto 0); --entrada de la s anterior para la suma
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s_prev : in std_logic_vector(15 downto 0); --entrada de la s anterior para la suma
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m : in std_logic_vector(15 downto 0);
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m : in std_logic_vector(15 downto 0);
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n_j : in std_logic_vector(15 downto 0);
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n_j : in std_logic_vector(15 downto 0);
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s_next : out std_logic_vector(15 downto 0); --salida con la siguiente s
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s_next : out std_logic_vector(15 downto 0); --salida con la siguiente s
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aj_bi : out std_logic_vector(15 downto 0); --salida de multiplicador reutilizado para calcular a*b
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aj_bi : out std_logic_vector(15 downto 0); --salida de multiplicador reutilizado para calcular a*b
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ab_valid_in : in std_logic; --indica que los datos de entrada en el multiplicador son validos
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ab_valid_in : in std_logic; --indica que los datos de entrada en el multiplicador son validos
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valid_in : in std_logic; --todas las entradas son validas, y la m está calculada
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valid_in : in std_logic; --todas las entradas son validas, y la m está calculada
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ab_valid_out : out std_logic; --indica que la multiplicacion de un a y b validos se ha realizado con exito
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ab_valid_out : out std_logic; --indica que la multiplicacion de un a y b validos se ha realizado con exito
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valid_out : out std_logic;
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valid_out : out std_logic;
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fifo_req : out std_logic);
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fifo_req : out std_logic);
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end component;
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end component;
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component m_calc is
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component m_calc is
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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ab : in std_logic_vector (15 downto 0);
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ab : in std_logic_vector (15 downto 0);
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t : in std_logic_vector (15 downto 0);
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t : in std_logic_vector (15 downto 0);
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n_cons : in std_logic_vector (15 downto 0);
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n_cons : in std_logic_vector (15 downto 0);
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m : out std_logic_vector (15 downto 0);
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m : out std_logic_vector (15 downto 0);
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mult_valid : in std_logic;
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mult_valid : in std_logic;
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m_valid : out std_logic);
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m_valid : out std_logic);
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end component;
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end component;
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signal aj_bi, m, next_m, m_out : std_logic_vector(15 downto 0);
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signal aj_bi, m, next_m, m_out : std_logic_vector(15 downto 0);
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signal mult_valid, valid_m, valid_m_reg : std_logic; --lo registro para compararlos
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signal mult_valid, valid_m, valid_m_reg : std_logic; --lo registro para compararlos
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begin
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begin
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pe_0 : pe port map(
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pe_0 : pe port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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a_j => a,
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a_j => a,
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b_i => b,
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b_i => b,
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s_prev => s_prev,
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s_prev => s_prev,
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m => m,
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m => m,
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n_j => n,
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n_j => n,
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s_next => s,
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s_next => s,
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aj_bi => aj_bi,
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aj_bi => aj_bi,
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ab_valid_in => ab_valid,
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ab_valid_in => ab_valid,
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valid_in => valid_in,
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valid_in => valid_in,
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ab_valid_out => mult_valid,
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ab_valid_out => mult_valid,
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valid_out => data_ready,
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valid_out => data_ready,
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fifo_req => fifo_req);
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fifo_req => fifo_req);
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mcons_0 : m_calc port map(
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mcons_0 : m_calc port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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ab => aj_bi,
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ab => aj_bi,
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t => s_prev,
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t => s_prev,
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n_cons => n_c,
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n_cons => n_c,
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m => m_out,
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m => m_out,
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mult_valid => mult_valid,
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mult_valid => mult_valid,
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m_valid => valid_m);
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m_valid => valid_m);
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process(clk, reset)
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process(clk, reset)
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begin
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begin
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if(clk='1' and clk'event) then
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if(clk = '1' and clk'event) then
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if(reset='1')then
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if(reset = '1')then
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m <= (others=> '0' );
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m <= (others => '0' );
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valid_m_reg <= '0';
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valid_m_reg <= '0';
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else
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else
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m <= next_m;
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m <= next_m;
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valid_m_reg <= valid_m;
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valid_m_reg <= valid_m;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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process(m_out,valid_m, valid_m_reg, m)
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process(m_out, valid_m, valid_m_reg, m)
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begin
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begin
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m_val <= valid_m_reg;
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m_val <= valid_m_reg;
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if(valid_m = '1' and valid_m_reg ='0') then
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if(valid_m = '1' and valid_m_reg = '0') then
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next_m <= m_out;
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next_m <= m_out;
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else
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else
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next_m <= m;
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next_m <= m;
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end if;
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end if;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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