// ============================================================================
|
// ============================================================================
|
// __
|
// __
|
// \\__/ o\ (C) 2013 Robert Finch, Stratford
|
// \\__/ o\ (C) 2013 Robert Finch, Stratford
|
// \ __ / All rights reserved.
|
// \ __ / All rights reserved.
|
// \/_// robfinch<remove>@opencores.org
|
// \/_// robfinch<remove>@opencores.org
|
// ||
|
// ||
|
//
|
//
|
// This source file is free software: you can redistribute it and/or modify
|
// This source file is free software: you can redistribute it and/or modify
|
// it under the terms of the GNU Lesser General Public License as published
|
// it under the terms of the GNU Lesser General Public License as published
|
// by the Free Software Foundation, either version 3 of the License, or
|
// by the Free Software Foundation, either version 3 of the License, or
|
// (at your option) any later version.
|
// (at your option) any later version.
|
//
|
//
|
// This source file is distributed in the hope that it will be useful,
|
// This source file is distributed in the hope that it will be useful,
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
// GNU General Public License for more details.
|
// GNU General Public License for more details.
|
//
|
//
|
// You should have received a copy of the GNU General Public License
|
// You should have received a copy of the GNU General Public License
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
//
|
//
|
// ============================================================================
|
// ============================================================================
|
//
|
//
|
// Eight bit mode RTS/RTL states
|
// Eight bit mode RTS/RTL states
|
//
|
//
|
BYTE_RTS1:
|
BYTE_RTS1:
|
if (unCachedData) begin
|
if (unCachedData) begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
sel_o <= 4'hF;
|
sel_o <= 4'hF;
|
adr_o <= {radr,2'b00};
|
adr_o <= {radr,2'b00};
|
state <= BYTE_RTS2;
|
state <= BYTE_RTS2;
|
end
|
end
|
else if (dhit) begin
|
else if (dhit) begin
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr2LSB <= sp_inc[1:0];
|
radr2LSB <= sp_inc[1:0];
|
sp <= sp_inc;
|
sp <= sp_inc;
|
pc[7:0] <= rdat8;
|
pc[7:0] <= rdat8;
|
state <= BYTE_RTS3;
|
state <= BYTE_RTS3;
|
end
|
end
|
else
|
else
|
dmiss <= `TRUE;
|
dmiss <= `TRUE;
|
BYTE_RTS2:
|
BYTE_RTS2:
|
if (ack_i) begin
|
if (ack_i) begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 4'h0;
|
sel_o <= 4'h0;
|
adr_o <= 34'h0;
|
adr_o <= 34'h0;
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr2LSB <= sp_inc[1:0];
|
radr2LSB <= sp_inc[1:0];
|
sp <= sp_inc;
|
sp <= sp_inc;
|
pc[7:0] <= dati;
|
pc[7:0] <= dati;
|
state <= BYTE_RTS3;
|
state <= BYTE_RTS3;
|
end
|
end
|
|
else if (err_i) begin
|
|
lock_o <= 1'b0;
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
we_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
adr_o <= 34'h0;
|
|
dat_o <= 32'h0;
|
|
state <= BUS_ERROR;
|
|
end
|
BYTE_RTS3:
|
BYTE_RTS3:
|
if (unCachedData) begin
|
if (unCachedData) begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
sel_o <= 4'hF;
|
sel_o <= 4'hF;
|
adr_o <= {radr,2'b00};
|
adr_o <= {radr,2'b00};
|
state <= BYTE_RTS4;
|
state <= BYTE_RTS4;
|
end
|
end
|
else if (dhit) begin
|
else if (dhit) begin
|
if (ir[7:0]==`RTL) begin
|
if (ir[7:0]==`RTL) begin
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr2LSB <= sp_inc[1:0];
|
radr2LSB <= sp_inc[1:0];
|
sp <= sp_inc;
|
sp <= sp_inc;
|
end
|
end
|
pc[15:8] <= rdat8;
|
pc[15:8] <= rdat8;
|
state <= BYTE_RTS5;
|
state <= BYTE_RTS5;
|
end
|
end
|
else
|
else
|
dmiss <= `TRUE;
|
dmiss <= `TRUE;
|
BYTE_RTS4:
|
BYTE_RTS4:
|
if (ack_i) begin
|
if (ack_i) begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 4'h0;
|
sel_o <= 4'h0;
|
adr_o <= 34'h0;
|
adr_o <= 34'h0;
|
pc[15:8] <= dati;
|
pc[15:8] <= dati;
|
if (ir[7:0]==`RTL) begin
|
if (ir[7:0]==`RTL) begin
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr2LSB <= sp_inc[1:0];
|
radr2LSB <= sp_inc[1:0];
|
sp <= sp_inc;
|
sp <= sp_inc;
|
end
|
end
|
state <= BYTE_RTS5;
|
state <= BYTE_RTS5;
|
end
|
end
|
|
else if (err_i) begin
|
|
lock_o <= 1'b0;
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
we_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
adr_o <= 34'h0;
|
|
dat_o <= 32'h0;
|
|
state <= BUS_ERROR;
|
|
end
|
BYTE_RTS5:
|
BYTE_RTS5:
|
if (ir[7:0]!=`RTL) begin
|
if (ir[7:0]!=`RTL) begin
|
pc <= pc + 32'd1;
|
pc <= pc + 32'd1;
|
state <= IFETCH;
|
state <= IFETCH;
|
end
|
end
|
else begin
|
else begin
|
if (unCachedData) begin
|
if (unCachedData) begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
sel_o <= 4'hF;
|
sel_o <= 4'hF;
|
adr_o <= {radr,2'b00};
|
adr_o <= {radr,2'b00};
|
state <= BYTE_RTS6;
|
state <= BYTE_RTS6;
|
end
|
end
|
else if (dhit) begin
|
else if (dhit) begin
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr2LSB <= sp_inc[1:0];
|
radr2LSB <= sp_inc[1:0];
|
sp <= sp_inc;
|
sp <= sp_inc;
|
pc[23:16] <= rdat8;
|
pc[23:16] <= rdat8;
|
state <= BYTE_RTS7;
|
state <= BYTE_RTS7;
|
end
|
end
|
else
|
else
|
dmiss <= `TRUE;
|
dmiss <= `TRUE;
|
end
|
end
|
BYTE_RTS6:
|
BYTE_RTS6:
|
if (ack_i) begin
|
if (ack_i) begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 4'h0;
|
sel_o <= 4'h0;
|
adr_o <= 34'h0;
|
adr_o <= 34'h0;
|
pc[23:16] <= dati;
|
pc[23:16] <= dati;
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr2LSB <= sp_inc[1:0];
|
radr2LSB <= sp_inc[1:0];
|
sp <= sp_inc;
|
sp <= sp_inc;
|
state <= BYTE_RTS7;
|
state <= BYTE_RTS7;
|
end
|
end
|
|
else if (err_i) begin
|
|
lock_o <= 1'b0;
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
we_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
adr_o <= 34'h0;
|
|
dat_o <= 32'h0;
|
|
state <= BUS_ERROR;
|
|
end
|
BYTE_RTS7:
|
BYTE_RTS7:
|
if (unCachedData) begin
|
if (unCachedData) begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
sel_o <= 4'hF;
|
sel_o <= 4'hF;
|
adr_o <= {radr,2'b00};
|
adr_o <= {radr,2'b00};
|
state <= BYTE_RTS8;
|
state <= BYTE_RTS8;
|
end
|
end
|
else if (dhit) begin
|
else if (dhit) begin
|
pc[31:24] <= rdat8;
|
pc[31:24] <= rdat8;
|
state <= BYTE_RTS9;
|
state <= BYTE_RTS9;
|
end
|
end
|
else
|
else
|
dmiss <= `TRUE;
|
dmiss <= `TRUE;
|
BYTE_RTS8:
|
BYTE_RTS8:
|
if (ack_i) begin
|
if (ack_i) begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 4'h0;
|
sel_o <= 4'h0;
|
adr_o <= 34'h0;
|
adr_o <= 34'h0;
|
pc[31:24] <= dati;
|
pc[31:24] <= dati;
|
state <= BYTE_RTS9;
|
state <= BYTE_RTS9;
|
end
|
end
|
|
else if (err_i) begin
|
|
lock_o <= 1'b0;
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
we_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
adr_o <= 34'h0;
|
|
dat_o <= 32'h0;
|
|
state <= BUS_ERROR;
|
|
end
|
BYTE_RTS9:
|
BYTE_RTS9:
|
begin
|
begin
|
pc <= pc + 32'd1;
|
pc <= pc + 32'd1;
|
state <= IFETCH;
|
state <= IFETCH;
|
end
|
end
|
|
|
No newline at end of file
|
No newline at end of file
|
|
|
No newline at end of file
|
No newline at end of file
|
