// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2013 Robert Finch, Stratford
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// \\__/ o\ (C) 2013 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// \/_// robfinch<remove>@opencores.org
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// ||
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// ||
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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task decode_tsk;
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task decode_tsk;
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begin
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begin
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first_ifetch <= `TRUE;
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first_ifetch <= `TRUE;
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Rt <= 4'h0; // Default
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Rt <= 4'h0; // Default
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state <= IFETCH;
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state <= IFETCH;
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pc <= pc + pc_inc;
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pc <= pc + pc_inc;
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pc_inc2 <= pc_inc;
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a <= rfoa;
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a <= rfoa;
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res <= alu_out;
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res <= alu_out;
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ttrig <= tf;
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ttrig <= tf;
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oisp <= isp; // for bus retry
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oisp <= isp; // for bus retry
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// This case statement should include all opcodes or the opcode
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// This case statement should include all opcodes or the opcode
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// will end up being treated as an undefined operation.
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// will end up being treated as an undefined operation.
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case(ir9)
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case(ir9)
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`STP: clk_en <= 1'b0;
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`STP: clk_en <= 1'b0;
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`NOP: ;
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`NOP: ;
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// casex(ir[63:0])
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// casex(ir[63:0])
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// {`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp8;
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// {`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp8;
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// {8'hxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp7;
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// {8'hxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp7;
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// {16'hxxxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp6;
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// {16'hxxxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp6;
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// {24'hxxxxxx,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp5;
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// {24'hxxxxxx,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp5;
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// {32'hxxxxxxxx,`NOP,`NOP,`NOP,`NOP}: pc <= pcp4;
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// {32'hxxxxxxxx,`NOP,`NOP,`NOP,`NOP}: pc <= pcp4;
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// {40'hxxxxxxxxxx,`NOP,`NOP,`NOP}: pc <= pcp3;
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// {40'hxxxxxxxxxx,`NOP,`NOP,`NOP}: pc <= pcp3;
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// {48'hxxxxxxxxxxxx,`NOP,`NOP}: pc <= pcp2;
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// {48'hxxxxxxxxxxxx,`NOP,`NOP}: pc <= pcp2;
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// {56'hxxxxxxxxxxxxxx,`NOP}: pc <= pcp1;
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// {56'hxxxxxxxxxxxxxx,`NOP}: pc <= pcp1;
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// endcase
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// endcase
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`CLC: cf <= 1'b0;
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`CLC: cf <= 1'b0;
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`SEC: cf <= 1'b1;
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`SEC: cf <= 1'b1;
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`CLV: vf <= 1'b0;
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`CLV: vf <= 1'b0;
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`CLI: im <= 1'b0;
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`CLI: im <= 1'b0;
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`CLD: df <= 1'b0;
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`CLD: df <= 1'b0;
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`SED: df <= 1'b1;
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`SED: df <= 1'b1;
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`SEI: im <= 1'b1;
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`SEI: im <= 1'b1;
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`WAI: wai <= 1'b1;
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`WAI: wai <= 1'b1;
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`TON: tf <= 1'b1;
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`TON: tf <= 1'b1;
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`TOFF: tf <= 1'b0;
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`TOFF: tf <= 1'b0;
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`HOFF: hist_capture <= 1'b0;
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`HOFF: hist_capture <= 1'b0;
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`EMM: begin em <= 1'b1;
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// Switching to 65c02 mode zeros out the upper part of the index registers.
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// Switching to 65c816 mode does not zero out the upper part of the index registers,
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// this is unlike switching from '02 to '816 mode. Also, the register size select
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// bits are not affected.
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`XCE: begin
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em <= 1'b1;
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m816 <= ~cf;
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cf <= ~m816;
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if (cf) begin
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x[31:8] <= 24'd0;
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y[31:8] <= 24'd0;
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end
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`ifdef SUPPORT_EM8
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`ifdef SUPPORT_EM8
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state <= BYTE_IFETCH;
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next_state(BYTE_IFETCH);
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`endif
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`endif
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end
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end
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`DEX: Rt <= 4'd2;
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`DEX: Rt <= 4'd2;
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// DEX/BNE accelerator
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// DEX/BNE accelerator
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// if (ir[15:8]==`BNE) begin
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// if (ir[15:8]==`BNE) begin
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// if (x!=32'd1) begin
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// if (x!=32'd1) begin
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// if (ir[23:16]==8'h01)
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// if (ir[23:16]==8'h01)
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// pc <= pc + {{16{ir[39]}},ir[39:24]} + 32'd1;
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// pc <= pc + {{16{ir[39]}},ir[39:24]} + 32'd1;
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// else
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// else
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// pc <= pc + {{24{ir[23]}},ir[23:16]} + 32'd1;
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// pc <= pc + {{24{ir[23]}},ir[23:16]} + 32'd1;
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// end
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// end
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// else begin
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// else begin
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// if (ir[23:16]==8'h01)
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// if (ir[23:16]==8'h01)
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// pc <= pcp5;
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// pc <= pcp5;
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// else
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// else
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// pc <= pcp3;
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// pc <= pcp3;
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// end
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// end
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// end
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// end
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`INX: Rt <= 4'd2;
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`INX: Rt <= 4'd2;
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`DEY: Rt <= 4'd3;
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`DEY: Rt <= 4'd3;
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`INY: Rt <= 4'd3;
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`INY: Rt <= 4'd3;
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`DEA: Rt <= 4'd1;
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`DEA: Rt <= 4'd1;
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`INA: Rt <= 4'd1;
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`INA: Rt <= 4'd1;
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`TSX: Rt <= 4'd2;
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`TSX: Rt <= 4'd2;
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`TSA: Rt <= 4'd1;
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`TSA: Rt <= 4'd1;
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`TXS: ;
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`TXS: ;
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`TXA: Rt <= 4'd1;
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`TXA: Rt <= 4'd1;
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`TXY: Rt <= 4'd3;
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`TXY: Rt <= 4'd3;
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`TAX: Rt <= 4'd2;
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`TAX: Rt <= 4'd2;
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`TAY: Rt <= 4'd3;
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`TAY: Rt <= 4'd3;
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`TAS: ;
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`TAS: ;
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`TYA: Rt <= 4'd1;
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`TYA: Rt <= 4'd1;
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`TYX: Rt <= 4'd2;
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`TYX: Rt <= 4'd2;
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`TRS: ;
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`TRS: ;
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`TSR: begin
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`TSR: begin
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Rt <= ir[15:12];
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Rt <= ir[15:12];
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case(ir[11:8])
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case(ir[11:8])
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4'h0: ;
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4'h0: ;
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4'h2: ;
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4'h2: ;
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4'h3: ;
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4'h3: ;
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4'h4: ;
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4'h4: ;
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4'h5: lfsr <= {lfsr[30:0],lfsr_fb};
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4'h5: lfsr <= {lfsr[30:0],lfsr_fb};
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4'd7: ;
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4'd7: ;
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4'h8: ;
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4'h8: ;
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4'h9: ;
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4'h9: ;
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`ifdef DEBUG
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`ifdef DEBUG
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4'hA: history_ndx <= history_ndx + 6'd1;
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4'hA: history_ndx <= history_ndx + 6'd1;
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`endif
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`endif
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4'hE: ;
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4'hE: ;
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4'hF: ;
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4'hF: ;
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default: ;
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default: ;
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endcase
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endcase
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end
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end
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`ASL_ACC: Rt <= 4'd1;
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`ASL_ACC: Rt <= 4'd1;
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`ROL_ACC: Rt <= 4'd1;
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`ROL_ACC: Rt <= 4'd1;
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`LSR_ACC: Rt <= 4'd1;
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`LSR_ACC: Rt <= 4'd1;
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`ROR_ACC: Rt <= 4'd1;
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`ROR_ACC: Rt <= 4'd1;
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`RR:
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`RR:
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begin
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begin
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Rt <= ir[19:16];
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Rt <= ir[19:16];
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case(ir[23:20])
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case(ir[23:20])
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`ADD_RR: b <= rfob;
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`ADD_RR: b <= rfob;
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`SUB_RR: b <= rfob;
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`SUB_RR: b <= rfob;
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`AND_RR: b <= rfob; // for bit flags
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`AND_RR: b <= rfob; // for bit flags
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`OR_RR: b <= rfob;
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`OR_RR: b <= rfob;
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`EOR_RR: b <= rfob;
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`EOR_RR: b <= rfob;
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`MUL_RR: begin b <= rfob; state <= MULDIV1; end
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`MUL_RR: begin b <= rfob; state <= MULDIV1; end
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`MULS_RR: begin b <= rfob; state <= MULDIV1; end
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`MULS_RR: begin b <= rfob; state <= MULDIV1; end
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`ifdef SUPPORT_DIVMOD
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`ifdef SUPPORT_DIVMOD
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`DIV_RR: begin b <= rfob; state <= MULDIV1; end
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`DIV_RR: begin b <= rfob; state <= MULDIV1; end
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`DIVS_RR: begin b <= rfob; state <= MULDIV1; end
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`DIVS_RR: begin b <= rfob; state <= MULDIV1; end
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`MOD_RR: begin b <= rfob; state <= MULDIV1; end
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`MOD_RR: begin b <= rfob; state <= MULDIV1; end
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`MODS_RR: begin b <= rfob; state <= MULDIV1; end
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`MODS_RR: begin b <= rfob; state <= MULDIV1; end
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`endif
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`endif
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`ifdef SUPPORT_SHIFT
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`ifdef SUPPORT_SHIFT
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`ASL_RRR: begin b <= rfob; state <= CALC; end
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`ASL_RRR: begin b <= rfob; state <= CALC; end
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`LSR_RRR: begin b <= rfob; state <= CALC; end
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`LSR_RRR: begin b <= rfob; state <= CALC; end
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`endif
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`endif
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default:
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default:
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begin
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begin
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Rt <= 4'h0;
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Rt <= 4'h0;
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pg2 <= `FALSE;
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pg2 <= `FALSE;
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ir <= {8{`BRK}};
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ir <= {8{`BRK}};
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hwi <= `TRUE;
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hwi <= `TRUE;
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vect <= {vbr[31:9],9'd495,2'b00};
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vect <= {vbr[31:9],9'd495,2'b00};
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pc <= pc; // override the pc increment
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pc <= pc; // override the pc increment
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state <= DECODE;
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state <= DECODE;
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end
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end
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endcase
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endcase
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end
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end
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`LD_RR: Rt <= ir[15:12];
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`LD_RR: Rt <= ir[15:12];
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`ASL_RR: Rt <= ir[15:12];
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`ASL_RR: Rt <= ir[15:12];
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`ROL_RR: Rt <= ir[15:12];
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`ROL_RR: Rt <= ir[15:12];
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`LSR_RR: Rt <= ir[15:12];
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`LSR_RR: Rt <= ir[15:12];
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`ROR_RR: Rt <= ir[15:12];
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`ROR_RR: Rt <= ir[15:12];
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`DEC_RR: Rt <= ir[15:12];
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`DEC_RR: Rt <= ir[15:12];
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`INC_RR: Rt <= ir[15:12];
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`INC_RR: Rt <= ir[15:12];
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/*
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Can't P&R this
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`ADD_R: begin Rt <= ir[11: 8]; b <= rfob; end
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`SUB_R: begin Rt <= ir[11: 8]; b <= rfob; end
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`OR_R: begin Rt <= ir[11: 8]; b <= rfob; end
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`AND_R: begin Rt <= ir[11: 8]; b <= rfob; end
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`EOR_R: begin Rt <= ir[11: 8]; b <= rfob; end
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*/
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`ADD_IMM4: begin Rt <= ir[11: 8]; b <= {{28{ir[15]}},ir[15:12]}; end
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`SUB_IMM4: begin Rt <= ir[11: 8]; b <= {{28{ir[15]}},ir[15:12]}; end
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`OR_IMM4: begin Rt <= ir[11: 8]; b <= {{28{ir[15]}},ir[15:12]}; end
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`AND_IMM4: begin Rt <= ir[11: 8]; b <= {{28{ir[15]}},ir[15:12]}; end
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`EOR_IMM4: begin Rt <= ir[11: 8]; b <= {{28{ir[15]}},ir[15:12]}; end
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`ADD_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
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`ADD_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
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`SUB_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
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`SUB_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
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`MUL_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
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`MUL_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
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`ifdef SUPPORT_DIVMOD
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`ifdef SUPPORT_DIVMOD
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`DIV_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
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`DIV_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
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`MOD_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
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`MOD_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
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`endif
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`endif
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`OR_IMM8: begin Rt <= ir[15:12]; end
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`OR_IMM8: begin Rt <= ir[15:12]; end
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`AND_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
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`AND_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
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`EOR_IMM8: begin Rt <= ir[15:12]; end
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`EOR_IMM8: begin Rt <= ir[15:12]; end
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`CMP_IMM8: ;
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`CMP_IMM8: ;
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`ifdef SUPPORT_SHIFT
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`ifdef SUPPORT_SHIFT
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`ASL_IMM8: begin Rt <= ir[15:12]; b <= ir[20:16]; state <= CALC; end
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`ASL_IMM8: begin Rt <= ir[15:12]; b <= ir[20:16]; state <= CALC; end
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`LSR_IMM8: begin Rt <= ir[15:12]; b <= ir[20:16]; state <= CALC; end
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`LSR_IMM8: begin Rt <= ir[15:12]; b <= ir[20:16]; state <= CALC; end
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`endif
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`endif
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`ADD_IMM16: begin Rt <= ir[15:12]; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
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`ADD_IMM16: begin Rt <= ir[15:12]; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
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`SUB_IMM16: begin Rt <= ir[15:12]; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
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`SUB_IMM16: begin Rt <= ir[15:12]; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
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`MUL_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
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`MUL_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
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`ifdef SUPPORT_DIVMOD
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`ifdef SUPPORT_DIVMOD
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`DIV_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
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`DIV_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
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`MOD_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
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`MOD_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
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`endif
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`endif
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`OR_IMM16: begin Rt <= ir[15:12]; end
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`OR_IMM16: begin Rt <= ir[15:12]; end
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`AND_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; end
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`AND_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; end
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`EOR_IMM16: begin Rt <= ir[15:12]; end
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`EOR_IMM16: begin Rt <= ir[15:12]; end
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`ADD_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; end
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`ADD_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; end
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`SUB_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; end
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`SUB_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; end
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`MUL_IMM16: begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
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`MUL_IMM16: begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
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`ifdef SUPPORT_DIVMOD
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`ifdef SUPPORT_DIVMOD
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`DIV_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
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`DIV_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
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`MOD_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
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`MOD_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
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`endif
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`endif
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`OR_IMM32: begin Rt <= ir[15:12]; end
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`OR_IMM32: begin Rt <= ir[15:12]; end
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`AND_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; end
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`AND_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; end
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`EOR_IMM32: begin Rt <= ir[15:12]; end
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`EOR_IMM32: begin Rt <= ir[15:12]; end
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`LDA_IMM32: Rt <= 4'd1;
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`LDA_IMM32: Rt <= 4'd1;
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`LDX_IMM32: Rt <= 4'd2;
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`LDX_IMM32: Rt <= 4'd2;
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`LDY_IMM32: Rt <= 4'd3;
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`LDY_IMM32: Rt <= 4'd3;
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`LDA_IMM16: Rt <= 4'd1;
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`LDA_IMM16: Rt <= 4'd1;
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`LDX_IMM16: Rt <= 4'd2;
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`LDX_IMM16: Rt <= 4'd2;
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`LDA_IMM8: Rt <= 4'd1;
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`LDA_IMM8: Rt <= 4'd1;
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`LDX_IMM8: Rt <= 4'd2;
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`LDX_IMM8: Rt <= 4'd2;
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`SUB_SP8: ;
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`SUB_SP8: ;
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`SUB_SP16: ;
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`SUB_SP16: ;
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`SUB_SP32: ;
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`SUB_SP32: ;
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`CPX_IMM32: ;
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`CPX_IMM32: ;
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`CPY_IMM32: ;
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`CPY_IMM32: ;
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`LDX_ZPX:
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`LDX_ZPX:
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begin
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begin
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Rt <= 4'd2;
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Rt <= 4'd2;
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radr <= zpx32xy_address;
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radr <= zpx32xy_address;
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load_what <= `WORD_311;
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load_what <= `WORD_311;
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state <= LOAD_MAC1;
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state <= LOAD_MAC1;
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end
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end
|
`LDY_ZPX:
|
`LDY_ZPX:
|
begin
|
begin
|
Rt <= 4'd3;
|
Rt <= 4'd3;
|
radr <= zpx32xy_address;
|
radr <= zpx32xy_address;
|
load_what <= `WORD_311;
|
load_what <= `WORD_311;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`ORB_ZPX:
|
`ORB_ZPX:
|
begin
|
begin
|
Rt <= ir[19:16];
|
Rt <= ir[19:16];
|
radr <= zpx32_address[31:2];
|
radr <= zpx32_address[31:2];
|
radr2LSB <= zpx32_address[1:0];
|
radr2LSB <= zpx32_address[1:0];
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`LDX_ABS:
|
`LDX_ABS:
|
begin
|
begin
|
Rt <= 4'd2;
|
Rt <= 4'd2;
|
radr <= ir[39:8];
|
radr <= ir[39:8];
|
load_what <= `WORD_311;
|
load_what <= `WORD_311;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`LDY_ABS:
|
`LDY_ABS:
|
begin
|
begin
|
Rt <= 4'd3;
|
Rt <= 4'd3;
|
radr <= ir[39:8];
|
radr <= ir[39:8];
|
load_what <= `WORD_311;
|
load_what <= `WORD_311;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`ORB_ABS:
|
`ORB_ABS:
|
begin
|
begin
|
Rt <= ir[15:12];
|
Rt <= ir[15:12];
|
radr <= ir[47:18];
|
radr <= ir[47:18];
|
radr2LSB <= ir[17:16];
|
radr2LSB <= ir[17:16];
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`LDX_ABSY:
|
`LDX_ABSY:
|
begin
|
begin
|
Rt <= 4'd2;
|
Rt <= 4'd2;
|
radr <= absx32xy_address;
|
radr <= absx32xy_address;
|
load_what <= `WORD_311;
|
load_what <= `WORD_311;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`LDY_ABSX:
|
`LDY_ABSX:
|
begin
|
begin
|
Rt <= 4'd3;
|
Rt <= 4'd3;
|
radr <= absx32xy_address;
|
radr <= absx32xy_address;
|
load_what <= `WORD_311;
|
load_what <= `WORD_311;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`ORB_ABSX:
|
`ORB_ABSX:
|
begin
|
begin
|
Rt <= ir[19:16];
|
Rt <= ir[19:16];
|
radr <= absx32_address[31:2];
|
radr <= absx32_address[31:2];
|
radr2LSB <= absx32_address[1:0];
|
radr2LSB <= absx32_address[1:0];
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`ST_ZPX:
|
`ST_ZPX:
|
begin
|
begin
|
wadr <= zpx32_address;
|
wadr <= zpx32_address;
|
store_what <= `STW_RFA;
|
store_what <= `STW_RFA;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STB_ZPX:
|
`STB_ZPX:
|
begin
|
begin
|
wadr <= zpx32_address[31:2];
|
wadr <= zpx32_address[31:2];
|
wadr2LSB <= zpx32_address[1:0];
|
wadr2LSB <= zpx32_address[1:0];
|
store_what <= `STW_RFA8;
|
store_what <= `STW_RFA8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`ST_DSP:
|
`ST_DSP:
|
begin
|
begin
|
wadr <= {{24{ir[23]}},ir[23:16]} + isp;
|
wadr <= {24'b0,ir[23:16]} + isp;
|
store_what <= `STW_RFA;
|
store_what <= `STW_RFA;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`ST_ABS:
|
`ST_ABS:
|
begin
|
begin
|
wadr <= ir[47:16];
|
wadr <= ir[47:16];
|
store_what <= `STW_RFA;
|
store_what <= `STW_RFA;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STB_ABS:
|
`STB_ABS:
|
begin
|
begin
|
wadr <= ir[47:18];
|
wadr <= ir[47:18];
|
wadr2LSB <= ir[17:16];
|
wadr2LSB <= ir[17:16];
|
store_what <= `STW_RFA8;
|
store_what <= `STW_RFA8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`ST_ABSX:
|
`ST_ABSX:
|
begin
|
begin
|
wadr <= absx32_address;
|
wadr <= absx32_address;
|
store_what <= `STW_RFA;
|
store_what <= `STW_RFA;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STB_ABSX:
|
`STB_ABSX:
|
begin
|
begin
|
wadr <= absx32_address[31:2];
|
wadr <= absx32_address[31:2];
|
wadr2LSB <= absx32_address[1:0];
|
wadr2LSB <= absx32_address[1:0];
|
store_what <= `STW_RFA8;
|
store_what <= `STW_RFA8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STX_ZPX:
|
`STX_ZPX:
|
begin
|
begin
|
wadr <= zpx32xy_address;
|
wadr <= zpx32xy_address;
|
store_what <= `STW_X;
|
store_what <= `STW_X;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STX_ABS:
|
`STX_ABS:
|
begin
|
begin
|
wadr <= ir[39:8];
|
wadr <= ir[39:8];
|
store_what <= `STW_X;
|
store_what <= `STW_X;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STY_ZPX:
|
`STY_ZPX:
|
begin
|
begin
|
wadr <= zpx32xy_address;
|
wadr <= zpx32xy_address;
|
store_what <= `STW_Y;
|
store_what <= `STW_Y;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STY_ABS:
|
`STY_ABS:
|
begin
|
begin
|
wadr <= ir[39:8];
|
wadr <= ir[39:8];
|
store_what <= `STW_Y;
|
store_what <= `STW_Y;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`ADD_ZPX,`SUB_ZPX,`AND_ZPX,`TRB_ZPX:
|
`ADD_ZPX,`SUB_ZPX,`AND_ZPX,`TRB_ZPX:
|
begin
|
begin
|
Rt <= ir[19:16];
|
Rt <= ir[19:16];
|
radr <= zpx32_address;
|
radr <= zpx32_address;
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`LEA_ZPX:
|
`LEA_ZPX:
|
begin
|
begin
|
Rt <= ir[19:16];
|
Rt <= ir[19:16];
|
res <= zpx32_address;
|
res <= zpx32_address;
|
state <= IFETCH;
|
state <= IFETCH;
|
end
|
end
|
// Trim a clock cycle off of loads by testing for Ra = 0.
|
// Trim a clock cycle off of loads by testing for Ra = 0.
|
`OR_ZPX,`EOR_ZPX,`TSB_ZPX:
|
`OR_ZPX,`EOR_ZPX,`TSB_ZPX:
|
begin
|
begin
|
Rt <= ir[19:16];
|
Rt <= ir[19:16];
|
radr <= zpx32_address;
|
radr <= zpx32_address;
|
load_what <= (Ra==4'd0) ? `WORD_311: `WORD_310;
|
load_what <= (Ra==4'd0) ? `WORD_311: `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
|
`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
|
begin
|
begin
|
radr <= zpx32xy_address;
|
radr <= zpx32xy_address;
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`BMS_ZPX,`BMC_ZPX,`BMF_ZPX,`BMT_ZPX:
|
`BMS_ZPX,`BMC_ZPX,`BMF_ZPX,`BMT_ZPX:
|
begin
|
begin
|
radr <= zpx32xy_address + acc[31:5];
|
radr <= zpx32xy_address + acc[31:5];
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`LEA_DSP:
|
`LEA_DSP:
|
begin
|
begin
|
Rt <= ir[15:12];
|
Rt <= ir[15:12];
|
res <= {{24{ir[23]}},ir[23:16]} + isp;
|
res <= {24'b0,ir[23:16]} + isp;
|
state <= IFETCH;
|
state <= IFETCH;
|
end
|
end
|
`ADD_DSP,`SUB_DSP,`OR_DSP,`AND_DSP,`EOR_DSP:
|
`ADD_DSP,`SUB_DSP,`OR_DSP,`AND_DSP,`EOR_DSP:
|
begin
|
begin
|
Rt <= ir[15:12];
|
Rt <= ir[15:12];
|
radr <= {{24{ir[23]}},ir[23:16]} + isp;
|
radr <= {24'b0,ir[23:16]} + isp;
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX,`LEA_IX:
|
`ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX,`LEA_IX:
|
begin
|
begin
|
if (ir[7:0]!=`ST_IX) // for ST_IX, Rt=0
|
if (ir[7:0]!=`ST_IX) // for ST_IX, Rt=0
|
Rt <= ir[19:16];
|
Rt <= ir[19:16];
|
radr <= zpx32_address;
|
radr <= zpx32_address;
|
load_what <= `IA_310;
|
load_what <= `IA_310;
|
store_what <= `STW_A;
|
store_what <= `STW_A;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`LEA_RIND:
|
`LEA_RIND:
|
begin
|
begin
|
Rt <= ir[19:16];
|
Rt <= ir[19:16];
|
res <= rfob;
|
res <= rfob;
|
state <= IFETCH;
|
state <= IFETCH;
|
end
|
end
|
`ADD_RIND,`SUB_RIND,`OR_RIND,`AND_RIND,`EOR_RIND:
|
`ADD_RIND,`SUB_RIND,`OR_RIND,`AND_RIND,`EOR_RIND:
|
begin
|
begin
|
radr <= rfob;
|
radr <= rfob;
|
Rt <= ir[19:16];
|
Rt <= ir[19:16];
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`ST_RIND:
|
`ST_RIND:
|
begin
|
begin
|
wadr <= rfob;
|
wadr <= rfob;
|
store_what <= `STW_RFA;
|
store_what <= `STW_RFA;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`ADD_IY,`SUB_IY,`OR_IY,`AND_IY,`EOR_IY,`ST_IY,`LEA_IY:
|
`ADD_IY,`SUB_IY,`OR_IY,`AND_IY,`EOR_IY,`ST_IY,`LEA_IY:
|
begin
|
begin
|
if (ir[7:0]!=`ST_IY) // for ST_IY, Rt=0
|
if (ir[7:0]!=`ST_IY) // for ST_IY, Rt=0
|
Rt <= ir[19:16];
|
Rt <= ir[19:16];
|
isIY <= 1'b1;
|
isIY <= 1'b1;
|
radr <= ir[31:20];
|
radr <= ir[31:20];
|
load_what <= `IA_310;
|
load_what <= `IA_310;
|
store_what <= `STW_A;
|
store_what <= `STW_A;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`LEA_ABS:
|
`LEA_ABS:
|
begin
|
begin
|
res <= ir[47:16];
|
res <= ir[47:16];
|
Rt <= ir[15:12];
|
Rt <= ir[15:12];
|
state <= IFETCH;
|
state <= IFETCH;
|
end
|
end
|
`OR_ABS,`EOR_ABS,`TSB_ABS:
|
`OR_ABS,`EOR_ABS,`TSB_ABS:
|
begin
|
begin
|
radr <= ir[47:16];
|
radr <= ir[47:16];
|
Rt <= ir[15:12];
|
Rt <= ir[15:12];
|
load_what <= (Ra==4'd0) ? `WORD_311 : `WORD_310;
|
load_what <= (Ra==4'd0) ? `WORD_311 : `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`ADD_ABS,`SUB_ABS,`AND_ABS,`TRB_ABS:
|
`ADD_ABS,`SUB_ABS,`AND_ABS,`TRB_ABS:
|
begin
|
begin
|
radr <= ir[47:16];
|
radr <= ir[47:16];
|
Rt <= ir[15:12];
|
Rt <= ir[15:12];
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS:
|
`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS:
|
begin
|
begin
|
radr <= ir[39:8];
|
radr <= ir[39:8];
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
|
`SPL_ABS:
|
|
begin
|
|
Rt <= 4'h0;
|
|
radr <= ir[39:8];
|
|
load_what <= `WORD_310;
|
|
state <= LOAD_MAC1;
|
|
end
|
`BMS_ABS,`BMC_ABS,`BMF_ABS,`BMT_ABS:
|
`BMS_ABS,`BMC_ABS,`BMF_ABS,`BMT_ABS:
|
begin
|
begin
|
radr <= ir[39:8] + acc[31:5];
|
radr <= ir[39:8] + acc[31:5];
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`LEA_ABSX:
|
`LEA_ABSX:
|
begin
|
begin
|
res <= absx32_address;
|
res <= absx32_address;
|
Rt <= ir[19:16];
|
Rt <= ir[19:16];
|
state <= IFETCH;
|
state <= IFETCH;
|
end
|
end
|
`ADD_ABSX,`SUB_ABSX,`AND_ABSX:
|
`ADD_ABSX,`SUB_ABSX,`AND_ABSX:
|
begin
|
begin
|
radr <= absx32_address;
|
radr <= absx32_address;
|
Rt <= ir[19:16];
|
Rt <= ir[19:16];
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`OR_ABSX,`EOR_ABSX:
|
`OR_ABSX,`EOR_ABSX:
|
begin
|
begin
|
radr <= absx32_address;
|
radr <= absx32_address;
|
Rt <= ir[19:16];
|
Rt <= ir[19:16];
|
load_what <= (Ra==4'd0) ? `WORD_311 : `WORD_310;
|
load_what <= (Ra==4'd0) ? `WORD_311 : `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX:
|
`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX:
|
begin
|
begin
|
radr <= absx32xy_address;
|
radr <= absx32xy_address;
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`BMS_ABSX,`BMC_ABSX,`BMF_ABSX,`BMT_ABSX:
|
`BMS_ABSX,`BMC_ABSX,`BMF_ABSX,`BMT_ABSX:
|
begin
|
begin
|
radr <= absx32xy_address + acc[31:5];
|
radr <= absx32xy_address + acc[31:5];
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
|
`SPL_ABSX:
|
|
begin
|
|
Rt <= 4'h0;
|
|
radr <= absx32xy_address;
|
|
load_what <= `WORD_310;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
|
`CPX_ZPX:
|
`CPX_ZPX:
|
begin
|
begin
|
radr <= zpx32xy_address;
|
radr <= zpx32xy_address;
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`CPY_ZPX:
|
`CPY_ZPX:
|
begin
|
begin
|
radr <= zpx32xy_address;
|
radr <= zpx32xy_address;
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`CPX_ABS:
|
`CPX_ABS:
|
begin
|
begin
|
radr <= ir[39:8];
|
radr <= ir[39:8];
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`CPY_ABS:
|
`CPY_ABS:
|
begin
|
begin
|
radr <= ir[39:8];
|
radr <= ir[39:8];
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`BRK:
|
`BRK:
|
begin
|
begin
|
bf <= !hwi;
|
bf <= !hwi;
|
km <= `TRUE;
|
km <= `TRUE;
|
`ifdef DEBUG
|
`ifdef DEBUG
|
hist_capture <= `FALSE;
|
hist_capture <= `FALSE;
|
`endif
|
`endif
|
radr <= isp_dec;
|
radr <= isp_dec;
|
wadr <= isp_dec;
|
wadr <= isp_dec;
|
isp <= isp_dec;
|
isp <= isp_dec;
|
store_what <= `STW_PCHWI;
|
store_what <= `STW_PCHWI;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`INT0,`INT1:
|
`INT0,`INT1:
|
begin
|
begin
|
pg2 <= `FALSE;
|
pg2 <= `FALSE;
|
ir <= {8{`BRK}};
|
ir <= {8{`BRK}};
|
vect <= {vbr[31:9],ir[15:7],2'b00};
|
vect <= {vbr[31:9],ir[0],ir[15:8],2'b00};
|
state <= DECODE;
|
state <= DECODE;
|
end
|
end
|
`JMP:
|
`JMP:
|
begin
|
begin
|
pc[15:0] <= ir[23:8];
|
pc[15:0] <= ir[23:8];
|
state <= IFETCH;
|
state <= IFETCH;
|
end
|
end
|
`JML:
|
`JML:
|
begin
|
begin
|
pc <= ir[39:8];
|
pc <= ir[39:8];
|
state <= IFETCH;
|
state <= IFETCH;
|
end
|
end
|
`JMP_IND:
|
`JMP_IND:
|
begin
|
begin
|
radr <= ir[39:8];
|
radr <= ir[39:8];
|
load_what <= `PC_310;
|
load_what <= `PC_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`JMP_INDX:
|
`JMP_INDX:
|
begin
|
begin
|
radr <= ir[39:8] + x;
|
radr <= ir[39:8] + x;
|
load_what <= `PC_310;
|
load_what <= `PC_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`JMP_RIND:
|
`JMP_RIND:
|
begin
|
begin
|
pc <= rfoa;
|
pc <= rfoa;
|
res <= pc + 32'd2;
|
res <= pc + 32'd2;
|
Rt <= ir[15:12];
|
Rt <= ir[15:12];
|
state <= IFETCH;
|
state <= IFETCH;
|
end
|
end
|
`JSR:
|
`JSR:
|
begin
|
begin
|
radr <= isp_dec;
|
radr <= isp_dec;
|
wadr <= isp_dec;
|
wadr <= isp_dec;
|
isp <= isp_dec;
|
isp <= isp_dec;
|
store_what <= `STW_DEF;
|
store_what <= `STW_DEF;
|
wdat <= pc+{31'd1,suppress_pcinc[0]};
|
wdat <= pc+{31'd1,suppress_pcinc[0]};
|
pc <= {pc[31:16],ir[23:8]};
|
pc <= {pc[31:16],ir[23:8]};
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`JSR_RIND:
|
`JSR_RIND:
|
begin
|
begin
|
radr <= isp_dec;
|
radr <= isp_dec;
|
wadr <= isp_dec;
|
wadr <= isp_dec;
|
wdat <= pc + 32'd2;
|
wdat <= pc + 32'd2;
|
isp <= isp_dec;
|
isp <= isp_dec;
|
store_what <= `STW_DEF;
|
store_what <= `STW_DEF;
|
pc <= rfoa;
|
pc <= rfoa;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`JSL,`JSR_INDX,`JSR_IND:
|
`JSL,`JSR_INDX,`JSR_IND:
|
begin
|
begin
|
radr <= isp_dec;
|
radr <= isp_dec;
|
wadr <= isp_dec;
|
wadr <= isp_dec;
|
isp <= isp_dec;
|
isp <= isp_dec;
|
store_what <= `STW_DEF;
|
store_what <= `STW_DEF;
|
wdat <= suppress_pcinc[0] ? pc + 32'd5 : pc + 32'd2;
|
wdat <= suppress_pcinc[0] ? pc + 32'd5 : pc + 32'd2;
|
pc <= ir[39:8]; // This pc assignment will be overridden later by JSR_INDX
|
pc <= ir[39:8]; // This pc assignment will be overridden later by JSR_INDX
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`BSR:
|
`BSR:
|
begin
|
begin
|
radr <= isp_dec;
|
radr <= isp_dec;
|
wadr <= isp_dec;
|
wadr <= isp_dec;
|
isp <= isp_dec;
|
isp <= isp_dec;
|
store_what <= `STW_DEF;
|
store_what <= `STW_DEF;
|
wdat <= pc+{31'd1,suppress_pcinc[0]};
|
wdat <= pc+{31'd1,suppress_pcinc[0]};
|
pc <= pc + {{16{ir[23]}},ir[23:8]};
|
pc <= pc + {{16{ir[23]}},ir[23:8]};
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`RTS,`RTL:
|
`RTS,`RTL:
|
begin
|
begin
|
radr <= isp;
|
radr <= isp;
|
isp <= isp_inc;
|
isp <= isp_inc;
|
load_what <= `PC_310;
|
load_what <= `PC_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`RTI: begin
|
`RTI: begin
|
hist_capture <= `TRUE;
|
hist_capture <= `TRUE;
|
radr <= isp;
|
radr <= isp;
|
isp <= isp_inc;
|
isp <= isp_inc;
|
load_what <= `SR_310;
|
load_what <= `SR_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA,
|
`BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA,
|
`BGT,`BGE,`BLT,`BLE,`BHI,`BLS:
|
`BGT,`BGE,`BLT,`BLE,`BHI,`BLS:
|
begin
|
begin
|
if (ir[15:8]==8'h00) begin
|
if (ir[15:8]==8'h00) begin
|
pg2 <= `FALSE;
|
pg2 <= `FALSE;
|
ir <= {8{`BRK}};
|
ir <= {8{`BRK}};
|
pc <= pc; // override the pc increment
|
pc <= pc; // override the pc increment
|
vect <= {vbr[31:9],`SLP_VECTNO,2'b00};
|
vect <= {vbr[31:9],`SLP_VECTNO,2'b00};
|
state <= DECODE;
|
state <= DECODE;
|
end
|
end
|
else if (ir[15:8]==8'h1) begin
|
else if (ir[15:8]==8'h1) begin
|
if (takb)
|
if (takb)
|
pc <= pc + {{16{ir[31]}},ir[31:16]};
|
pc <= pc + {{16{ir[31]}},ir[31:16]};
|
else
|
else
|
pc <= pcp4;
|
pc <= pcp4;
|
end
|
end
|
else begin
|
else begin
|
if (takb)
|
if (takb)
|
pc <= pc + {{24{ir[15]}},ir[15:8]};
|
pc <= pc + {{24{ir[15]}},ir[15:8]};
|
else
|
else
|
pc <= pcp2;
|
pc <= pcp2;
|
end
|
end
|
end
|
end
|
`BRL:
|
`BRL:
|
begin
|
begin
|
if (ir[23:8]==16'h0000) begin
|
if (ir[23:8]==16'h0000) begin
|
pg2 <= `FALSE;
|
pg2 <= `FALSE;
|
ir <= {8{`BRK}};
|
ir <= {8{`BRK}};
|
vect <= {vbr[31:9],`SLP_VECTNO,2'b00};
|
vect <= {vbr[31:9],`SLP_VECTNO,2'b00};
|
pc <= pc; // override the pc increment
|
pc <= pc; // override the pc increment
|
state <= DECODE;
|
state <= DECODE;
|
end
|
end
|
else begin
|
else begin
|
pc <= pc + {{16{ir[23]}},ir[23:8]};
|
pc <= pc + {{16{ir[23]}},ir[23:8]};
|
state <= IFETCH;
|
state <= IFETCH;
|
end
|
end
|
end
|
end
|
`ifdef SUPPORT_EXEC
|
`ifdef SUPPORT_EXEC
|
`EXEC,`ATNI:
|
`EXEC,`ATNI:
|
begin
|
begin
|
exbuf[31:0] <= rfoa;
|
exbuf[31:0] <= rfoa;
|
exbuf[63:32] <= rfob;
|
exbuf[63:32] <= rfob;
|
end
|
end
|
`endif
|
`endif
|
`PHP:
|
`PHP:
|
begin
|
begin
|
radr <= isp_dec;
|
radr <= isp_dec;
|
wadr <= isp_dec;
|
wadr <= isp_dec;
|
store_what <= `STW_SR;
|
store_what <= `STW_SR;
|
isp <= isp_dec;
|
isp <= isp_dec;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`PHA:
|
`PHA:
|
begin
|
begin
|
radr <= isp_dec;
|
radr <= isp_dec;
|
wadr <= isp_dec;
|
wadr <= isp_dec;
|
store_what <= `STW_ACC;
|
store_what <= `STW_ACC;
|
isp <= isp_dec;
|
isp <= isp_dec;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`PHX:
|
`PHX:
|
begin
|
begin
|
radr <= isp_dec;
|
radr <= isp_dec;
|
wadr <= isp_dec;
|
wadr <= isp_dec;
|
store_what <= `STW_X;
|
store_what <= `STW_X;
|
isp <= isp_dec;
|
isp <= isp_dec;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`PHY:
|
`PHY:
|
begin
|
begin
|
radr <= isp_dec;
|
radr <= isp_dec;
|
wadr <= isp_dec;
|
wadr <= isp_dec;
|
store_what <= `STW_Y;
|
store_what <= `STW_Y;
|
isp <= isp_dec;
|
isp <= isp_dec;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`PUSH:
|
`PUSH:
|
begin
|
begin
|
if (ir[15:12]==4'h0) begin
|
if (ir[15:12]==4'h0) begin
|
radr <= isp_dec;
|
radr <= isp_dec;
|
wadr <= isp_dec;
|
wadr <= isp_dec;
|
isp <= isp_dec;
|
isp <= isp_dec;
|
end
|
end
|
else begin
|
else begin
|
radr <= rfob-32'd1;
|
radr <= rfob-32'd1;
|
wadr <= rfob-32'd1;
|
wadr <= rfob-32'd1;
|
wrrf <= 1'b1;
|
wrrf <= 1'b1;
|
Rt <= ir[15:12];
|
Rt <= ir[15:12];
|
res <= rfob-32'd1;
|
res <= rfob-32'd1;
|
end
|
end
|
store_what <= `STW_A;
|
store_what <= `STW_A;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`PUSHA:
|
`PUSHA:
|
begin
|
begin
|
radr <= isp_dec;
|
radr <= isp_dec;
|
wadr <= isp_dec;
|
wadr <= isp_dec;
|
ir[11:8] <= 4'd1;
|
ir[11:8] <= 4'd1;
|
store_what <= `STW_RFA;
|
store_what <= `STW_RFA;
|
state <= STORE1;
|
state <= STORE1;
|
isp <= isp_dec;
|
isp <= isp_dec;
|
end
|
end
|
`PLP:
|
`PLP:
|
begin
|
begin
|
radr <= isp;
|
radr <= isp;
|
isp <= isp_inc;
|
isp <= isp_inc;
|
load_what <= `SR_310;
|
load_what <= `SR_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`PLA:
|
`PLA:
|
begin
|
begin
|
Rt <= 4'd1;
|
Rt <= 4'd1;
|
radr <= isp;
|
radr <= isp;
|
isp <= isp_inc;
|
isp <= isp_inc;
|
load_what <= `WORD_311;
|
load_what <= `WORD_311;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`PLX:
|
`PLX:
|
begin
|
begin
|
Rt <= 4'd2;
|
Rt <= 4'd2;
|
radr <= isp;
|
radr <= isp;
|
isp <= isp_inc;
|
isp <= isp_inc;
|
load_what <= `WORD_311;
|
load_what <= `WORD_311;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`PLY:
|
`PLY:
|
begin
|
begin
|
Rt <= 4'd3;
|
Rt <= 4'd3;
|
radr <= isp;
|
radr <= isp;
|
isp <= isp_inc;
|
isp <= isp_inc;
|
load_what <= `WORD_311;
|
load_what <= `WORD_311;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`POP:
|
`POP:
|
begin
|
begin
|
if (ir[11:8]!=4'h0) begin
|
if (ir[11:8]!=4'h0) begin
|
Rt <= ir[11:8];
|
Rt <= ir[11:8];
|
res <= rfoa+32'd1;
|
res <= rfoa+32'd1;
|
wrrf <= 1'b1;
|
wrrf <= 1'b1;
|
radr <= rfoa;
|
radr <= rfoa;
|
end
|
end
|
else begin
|
else begin
|
radr <= isp;
|
radr <= isp;
|
isp <= isp_inc;
|
isp <= isp_inc;
|
end
|
end
|
load_what <= `WORD_311;
|
load_what <= `WORD_311;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`POPA:
|
`POPA:
|
begin
|
begin
|
Rt <= 4'd15;
|
Rt <= 4'd15;
|
radr <= isp;
|
radr <= isp;
|
isp <= isp_inc;
|
isp <= isp_inc;
|
load_what <= `WORD_311;
|
load_what <= `WORD_311;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`ifdef SUPPORT_STRING
|
`ifdef SUPPORT_STRING
|
`MVN:
|
`MVN:
|
begin
|
begin
|
Rt <= 4'd3;
|
Rt <= 4'd3;
|
radr <= x;
|
radr <= x;
|
res <= x + 32'd1;
|
res <= x_inc;
|
load_what <= `WORD_312;
|
load_what <= `WORD_312;
|
|
pc <= pc;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`MVP:
|
`MVP:
|
begin
|
begin
|
Rt <= 4'd3;
|
Rt <= 4'd3;
|
radr <= x;
|
radr <= x;
|
res <= x - 32'd1;
|
res <= x_dec;
|
load_what <= `WORD_312;
|
load_what <= `WORD_312;
|
|
pc <= pc;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`STS:
|
`STS:
|
begin
|
begin
|
Rt <= 4'd3;
|
Rt <= 4'd3;
|
radr <= y;
|
radr <= y;
|
wadr <= y;
|
wadr <= y;
|
store_what <= `STW_X;
|
store_what <= `STW_X;
|
acc <= acc - 32'd1;
|
acc <= acc_dec;
|
|
pc <= pc;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`CMPS:
|
`CMPS:
|
begin
|
begin
|
Rt <= 4'd3;
|
Rt <= 4'd3;
|
radr <= x;
|
radr <= x;
|
res <= x + 32'd1;
|
res <= x_inc;
|
|
pc <= pc;
|
load_what <= `WORD_313;
|
load_what <= `WORD_313;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`endif
|
`endif
|
`PG2: begin
|
`PG2: begin
|
pg2 <= `TRUE;
|
pg2 <= `TRUE;
|
ir <= ir[63:8];
|
ir <= ir[63:8];
|
state <= DECODE;
|
state <= DECODE;
|
end
|
end
|
default: // unimplemented opcode
|
default: // unimplemented opcode
|
begin
|
begin
|
res <= 32'd0;
|
res <= 32'd0;
|
pg2 <= `FALSE;
|
pg2 <= `FALSE;
|
ir <= {8{`BRK}};
|
ir <= {8{`BRK}};
|
hwi <= `TRUE;
|
hwi <= `TRUE;
|
vect <= {vbr[31:9],9'd495,2'b00};
|
vect <= {vbr[31:9],9'd495,2'b00};
|
pc <= pc; // override the pc increment
|
pc <= pc; // override the pc increment
|
state <= DECODE;
|
state <= DECODE;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
