// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2013 Robert Finch, Stratford
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// \\__/ o\ (C) 2013 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// \/_// robfinch<remove>@opencores.org
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// ||
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// ||
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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`include "rtf65002_defines.v"
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`include "rtf65002_defines.v"
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module rtf65002_alu(clk, state, resin, pg2, ir, acc, x, y, isp, rfoa, rfob, a, b, b8, Rt,
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module rtf65002_alu(clk, state, resin, pg2, ir, acc, x, y, isp, rfoa, rfob, a, b, b8, Rt,
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icacheOn, dcacheOn, write_allocate, prod, tick, lfsr, abs8, vbr, nmoi,
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icacheOn, dcacheOn, write_allocate, prod, tick, lfsr, abs8, vbr, nmoi,
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derr_address, history_buf, spage, sp, df, cf,
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derr_address, history_buf, spage, sp, df, cf,
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res);
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res);
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input clk;
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input clk;
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input [5:0] state;
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input [5:0] state;
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input [32:0] resin;
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input [32:0] resin;
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input pg2;
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input pg2;
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input [63:0] ir;
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input [63:0] ir;
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input [31:0] acc;
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input [31:0] acc;
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input [31:0] x;
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input [31:0] x;
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input [31:0] y;
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input [31:0] y;
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input [31:0] isp;
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input [31:0] isp;
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input [31:0] rfoa;
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input [31:0] rfoa;
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input [31:0] rfob;
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input [31:0] rfob;
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input [31:0] a;
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input [31:0] a;
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input [31:0] b;
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input [31:0] b;
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input [7:0] b8;
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input [7:0] b8;
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input [3:0] Rt;
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input [3:0] Rt;
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input icacheOn;
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input icacheOn;
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input dcacheOn;
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input dcacheOn;
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input write_allocate;
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input write_allocate;
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input [63:0] prod;
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input [63:0] prod;
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input [31:0] tick;
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input [31:0] tick;
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input [31:0] lfsr;
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input [31:0] lfsr;
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input [31:0] abs8;
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input [31:0] abs8;
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input [31:0] vbr;
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input [31:0] vbr;
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input nmoi;
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input nmoi;
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input [31:0] derr_address;
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input [31:0] derr_address;
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input [31:0] history_buf;
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input [31:0] history_buf;
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input [31:0] spage;
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input [31:0] spage;
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input [7:0] sp;
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input [7:0] sp;
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input df;
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input df;
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input cf;
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input cf;
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output reg [32:0] res;
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output reg [32:0] res;
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`ifdef SUPPORT_SHIFT
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`ifdef SUPPORT_SHIFT
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wire [31:0] shlo = a << b[4:0];
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wire [31:0] shlo = a << b[4:0];
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wire [31:0] shro = a >> b[4:0];
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wire [31:0] shro = a >> b[4:0];
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`else
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`else
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wire [31:0] shlo = 32'd0;
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wire [31:0] shlo = 32'd0;
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wire [31:0] shro = 32'd0;
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wire [31:0] shro = 32'd0;
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`endif
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`endif
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always @*
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always @*
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case({pg2,ir[7:0]})
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case({pg2,ir[7:0]})
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`DEX: res <= x - 32'd1;
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`DEX: res <= x - 32'd1;
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`INX: res <= x + 32'd1;
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`INX: res <= x + 32'd1;
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`DEY,`MVP: res <= y - 32'd1;
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`DEY,`MVP: res <= y - 32'd1;
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`INY: res <= y + 32'd1;
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`INY: res <= y + 32'd1;
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`STS,`MVN,`CMPS: res <= y + 32'd1;
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`STS,`MVN,`CMPS: res <= y + 32'd1;
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`DEA: res <= acc - 32'd1;
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`DEA: res <= acc - 32'd1;
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`INA: res <= acc + 32'd1;
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`INA: res <= acc + 32'd1;
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`TSX,`TSA: res <= isp;
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`TSX,`TSA: res <= isp;
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`TXS,`TXA,`TXY: res <= x;
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`TXS,`TXA,`TXY: res <= x;
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`TAX,`TAY,`TAS: res <= acc;
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`TAX,`TAY,`TAS: res <= acc;
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`TYA,`TYX: res <= y;
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`TYA,`TYX: res <= y;
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`TRS: res <= rfoa;
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`TRS: res <= rfoa;
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`TSR: begin
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`TSR: begin
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case(ir[11:8])
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case(ir[11:8])
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4'h0:
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4'h0:
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begin
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begin
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`ifdef SUPPORT_ICACHE
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`ifdef SUPPORT_ICACHE
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res[0] <= icacheOn;
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res[0] <= icacheOn;
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`endif
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`endif
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`ifdef SUPPORT_DCACHE
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`ifdef SUPPORT_DCACHE
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res[1] <= dcacheOn;
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res[1] <= dcacheOn;
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res[2] <= write_allocate;
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res[2] <= write_allocate;
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`endif
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`endif
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res[32:3] <= 30'd0;
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res[32:3] <= 30'd0;
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end
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end
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4'h2: res <= prod[31:0];
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4'h2: res <= prod[31:0];
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4'h3: res <= prod[63:32];
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4'h3: res <= prod[63:32];
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4'h4: res <= tick;
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4'h4: res <= tick;
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4'h5: res <= lfsr;
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4'h5: res <= lfsr;
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4'd7: res <= abs8;
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4'd7: res <= abs8;
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4'h8: res <= {vbr[31:1],nmoi};
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4'h8: res <= {vbr[31:1],nmoi};
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4'h9: res <= derr_address;
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4'h9: res <= derr_address;
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`ifdef DEBUG
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4'hA: res <= history_buf;
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4'hA: res <= history_buf;
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`endif
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4'hE: res <= {spage[31:8],sp};
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4'hE: res <= {spage[31:8],sp};
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4'hF: res <= isp;
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4'hF: res <= isp;
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default: res <= 33'd0;
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default: res <= 33'd0;
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endcase
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endcase
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end
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end
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`ASL_ACC: res <= {acc,1'b0};
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`ASL_ACC: res <= {acc,1'b0};
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`ROL_ACC: res <= {acc,cf};
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`ROL_ACC: res <= {acc,cf};
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`LSR_ACC: res <= {acc[0],1'b0,acc[31:1]};
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`LSR_ACC: res <= {acc[0],1'b0,acc[31:1]};
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`ROR_ACC: res <= {acc[0],cf,acc[31:1]};
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`ROR_ACC: res <= {acc[0],cf,acc[31:1]};
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`RR:
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`RR:
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begin
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begin
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case(ir[23:20])
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case(ir[23:20])
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`ADD_RR: res <= rfoa + rfob + {31'b0,df&cf};
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`ADD_RR: res <= rfoa + rfob + {31'b0,df&cf};
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`SUB_RR: res <= rfoa - rfob - {31'b0,df&~cf&|ir[19:16]};
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`SUB_RR: res <= rfoa - rfob - {31'b0,df&~cf&|ir[19:16]};
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`AND_RR: res <= rfoa & rfob;
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`AND_RR: res <= rfoa & rfob;
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`OR_RR: res <= rfoa | rfob;
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`OR_RR: res <= rfoa | rfob;
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`EOR_RR: res <= rfoa ^ rfob;
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`EOR_RR: res <= rfoa ^ rfob;
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`ifdef SUPPORT_SHIFT
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`ifdef SUPPORT_SHIFT
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`ASL_RRR: res <= shlo;
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`ASL_RRR: res <= shlo;
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`LSR_RRR: res <= shro;
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`LSR_RRR: res <= shro;
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`endif
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`endif
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default: res <= 33'd0;
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default: res <= 33'd0;
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endcase
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endcase
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end
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end
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`LD_RR: res <= rfoa;
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`LD_RR: res <= rfoa;
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`ASL_RR: res <= {rfoa,1'b0};
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`ASL_RR: res <= {rfoa,1'b0};
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`ROL_RR: res <= {rfoa,cf};
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`ROL_RR: res <= {rfoa,cf};
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`LSR_RR: res <= {rfoa[0],1'b0,rfoa[31:1]};
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`LSR_RR: res <= {rfoa[0],1'b0,rfoa[31:1]};
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`ROR_RR: res <= {rfoa[0],cf,rfoa[31:1]};
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`ROR_RR: res <= {rfoa[0],cf,rfoa[31:1]};
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`DEC_RR: res <= rfoa - 32'd1;
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`DEC_RR: res <= rfoa - 32'd1;
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`INC_RR: res <= rfoa + 32'd1;
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`INC_RR: res <= rfoa + 32'd1;
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`ADD_IMM8: res <= rfoa + {{24{ir[23]}},ir[23:16]} + {31'b0,df&cf};
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`ADD_IMM8: res <= rfoa + {{24{ir[23]}},ir[23:16]} + {31'b0,df&cf};
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`SUB_IMM8: res <= rfoa - {{24{ir[23]}},ir[23:16]} - {31'b0,df&~cf&|ir[15:12]};
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`SUB_IMM8: res <= rfoa - {{24{ir[23]}},ir[23:16]} - {31'b0,df&~cf&|ir[15:12]};
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`MUL_IMM8: res <= 33'd0;
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`MUL_IMM8: res <= 33'd0;
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`ifdef SUPPORT_DIVMOD
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`ifdef SUPPORT_DIVMOD
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`DIV_IMM8: res <= 33'd0;
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`DIV_IMM8: res <= 33'd0;
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`MOD_IMM8: res <= 33'd0;
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`MOD_IMM8: res <= 33'd0;
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`endif
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`endif
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`OR_IMM8: res <= rfoa | {{24{ir[23]}},ir[23:16]};
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`OR_IMM8: res <= rfoa | {{24{ir[23]}},ir[23:16]};
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`AND_IMM8: res <= rfoa & {{24{ir[23]}},ir[23:16]};
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`AND_IMM8: res <= rfoa & {{24{ir[23]}},ir[23:16]};
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`EOR_IMM8: res <= rfoa ^ {{24{ir[23]}},ir[23:16]};
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`EOR_IMM8: res <= rfoa ^ {{24{ir[23]}},ir[23:16]};
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`CMP_IMM8: res <= acc - {{24{ir[15]}},ir[15:8]};
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`CMP_IMM8: res <= acc - {{24{ir[15]}},ir[15:8]};
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`ADD_IMM16: res <= rfoa + {{16{ir[31]}},ir[31:16]} + {31'b0,df&cf};
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`ADD_IMM16: res <= rfoa + {{16{ir[31]}},ir[31:16]} + {31'b0,df&cf};
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`SUB_IMM16: res <= rfoa - {{16{ir[31]}},ir[31:16]} - {31'b0,df&~cf&|ir[15:12]};
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`SUB_IMM16: res <= rfoa - {{16{ir[31]}},ir[31:16]} - {31'b0,df&~cf&|ir[15:12]};
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`MUL_IMM16: res <= 33'd0;
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`MUL_IMM16: res <= 33'd0;
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`ifdef SUPPORT_DIVMOD
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`ifdef SUPPORT_DIVMOD
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`DIV_IMM16: res <= 33'd0;
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`DIV_IMM16: res <= 33'd0;
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`MOD_IMM16: res <= 33'd0;
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`MOD_IMM16: res <= 33'd0;
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`endif
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`endif
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`OR_IMM16: res <= rfoa | {{16{ir[31]}},ir[31:16]};
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`OR_IMM16: res <= rfoa | {{16{ir[31]}},ir[31:16]};
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`AND_IMM16:
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`AND_IMM16:
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begin
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begin
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res <= rfoa & {{16{ir[31]}},ir[31:16]};
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res <= rfoa & {{16{ir[31]}},ir[31:16]};
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$display("%h & %h", rfoa, {{16{ir[31]}},ir[31:16]});
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$display("%h & %h", rfoa, {{16{ir[31]}},ir[31:16]});
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end
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end
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`EOR_IMM16: res <= rfoa ^ {{16{ir[31]}},ir[31:16]};
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`EOR_IMM16: res <= rfoa ^ {{16{ir[31]}},ir[31:16]};
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`ADD_IMM32: res <= rfoa + ir[47:16] + {31'b0,df&cf};
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`ADD_IMM32: res <= rfoa + ir[47:16] + {31'b0,df&cf};
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`SUB_IMM32: res <= rfoa - ir[47:16] - {31'b0,df&~cf&|ir[15:12]};
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`SUB_IMM32: res <= rfoa - ir[47:16] - {31'b0,df&~cf&|ir[15:12]};
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`MUL_IMM16: res <= 33'd0;
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`MUL_IMM16: res <= 33'd0;
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`ifdef SUPPORT_DIVMOD
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`ifdef SUPPORT_DIVMOD
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`DIV_IMM32: res <= 33'd0;
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`DIV_IMM32: res <= 33'd0;
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`MOD_IMM32: res <= 33'd0;
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`MOD_IMM32: res <= 33'd0;
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`endif
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`endif
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`OR_IMM32: res <= rfoa | ir[47:16];
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`OR_IMM32: res <= rfoa | ir[47:16];
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`AND_IMM32: res <= rfoa & ir[47:16];
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`AND_IMM32: res <= rfoa & ir[47:16];
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`EOR_IMM32: res <= rfoa ^ ir[47:16];
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`EOR_IMM32: res <= rfoa ^ ir[47:16];
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`LDX_IMM32,`LDY_IMM32,`LDA_IMM32: res <= ir[39:8];
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`LDX_IMM32,`LDY_IMM32,`LDA_IMM32: res <= ir[39:8];
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`LDX_IMM16,`LDA_IMM16: res <= {{16{ir[23]}},ir[23:8]};
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`LDX_IMM16,`LDA_IMM16: res <= {{16{ir[23]}},ir[23:8]};
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`LDX_IMM8,`LDA_IMM8: res <= {{24{ir[15]}},ir[15:8]};
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`LDX_IMM8,`LDA_IMM8: res <= {{24{ir[15]}},ir[15:8]};
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`SUB_SP8: res <= isp - {{24{ir[15]}},ir[15:8]};
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`SUB_SP8: res <= isp - {{24{ir[15]}},ir[15:8]};
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`SUB_SP16: res <= isp - {{16{ir[23]}},ir[23:8]};
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`SUB_SP16: res <= isp - {{16{ir[23]}},ir[23:8]};
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`SUB_SP32: res <= isp - ir[39:8];
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`SUB_SP32: res <= isp - ir[39:8];
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`CPX_IMM32: res <= x - ir[39:8];
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`CPX_IMM32: res <= x - ir[39:8];
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`CPY_IMM32: res <= y - ir[39:8];
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`CPY_IMM32: res <= y - ir[39:8];
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// The following results are available for CALC only after the DECODE/LOAD_MAC
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// The following results are available for CALC only after the DECODE/LOAD_MAC
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// stage as the 'a' and 'b' side registers need to be loaded.
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// stage as the 'a' and 'b' side registers need to be loaded.
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`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND: res <= a + b + {31'b0,df&cf};
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`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND: res <= a + b + {31'b0,df&cf};
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`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND: res <= a - b - {31'b0,df&~cf&|Rt}; // Also CMP
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`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND: res <= a - b - {31'b0,df&~cf&|Rt}; // Also CMP
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`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND: res <= a & b; // Also BIT
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`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND: res <= a & b; // Also BIT
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`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND: res <= a | b; // Also LD
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`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND: res <= a | b; // Also LD
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`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND: res <= a ^ b;
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`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND: res <= a ^ b;
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`LDX_ZPY,`LDX_ABS,`LDX_ABSY: res <= b;
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`LDX_ZPY,`LDX_ABS,`LDX_ABSY: res <= b;
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`LDY_ZPX,`LDY_ABS,`LDY_ABSX: res <= b;
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`LDY_ZPX,`LDY_ABS,`LDY_ABSX: res <= b;
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`CPX_ZPX,`CPX_ABS: res <= x - b;
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`CPX_ZPX,`CPX_ABS: res <= x - b;
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`CPY_ZPX,`CPY_ABS: res <= y - b;
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`CPY_ZPX,`CPY_ABS: res <= y - b;
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`ifdef SUPPORT_SHIFT
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`ifdef SUPPORT_SHIFT
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`ASL_IMM8: res <= shlo;
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`ASL_IMM8: res <= shlo;
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`LSR_IMM8: res <= shro;
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`LSR_IMM8: res <= shro;
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`endif
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`endif
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`ASL_ZPX,`ASL_ABS,`ASL_ABSX: res <= {b,1'b0};
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`ASL_ZPX,`ASL_ABS,`ASL_ABSX: res <= {b,1'b0};
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`ROL_ZPX,`ROL_ABS,`ROL_ABSX: res <= {b,cf};
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`ROL_ZPX,`ROL_ABS,`ROL_ABSX: res <= {b,cf};
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`LSR_ZPX,`LSR_ABS,`LSR_ABSX: res <= {b[0],1'b0,b[31:1]};
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`LSR_ZPX,`LSR_ABS,`LSR_ABSX: res <= {b[0],1'b0,b[31:1]};
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`ROR_ZPX,`ROR_ABS,`ROR_ABSX: res <= {b[0],cf,b[31:1]};
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`ROR_ZPX,`ROR_ABS,`ROR_ABSX: res <= {b[0],cf,b[31:1]};
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`INC_ZPX,`INC_ABS,`INC_ABSX: res <= b + 32'd1;
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`INC_ZPX,`INC_ABS,`INC_ABSX: res <= b + 32'd1;
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`DEC_ZPX,`DEC_ABS,`DEC_ABSX: res <= b - 32'd1;
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`DEC_ZPX,`DEC_ABS,`DEC_ABSX: res <= b - 32'd1;
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`ORB_ZPX,`ORB_ABS,`ORB_ABSX: res <= a | {24'h0,b8};
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`ORB_ZPX,`ORB_ABS,`ORB_ABSX: res <= a | {24'h0,b8};
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`BMS_ZPX,`BMS_ABS,`BMS_ABSX: res <= b | (32'b1 << acc[4:0]);
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`BMS_ZPX,`BMS_ABS,`BMS_ABSX: res <= b | (32'b1 << acc[4:0]);
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`BMC_ZPX,`BMC_ABS,`BMC_ABSX: res <= b & (~(32'b1 << acc[4:0]));
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`BMC_ZPX,`BMC_ABS,`BMC_ABSX: res <= b & (~(32'b1 << acc[4:0]));
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`BMF_ZPX,`BMF_ABS,`BMF_ABSX: res <= b ^ (32'b1 << acc[4:0]);
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`BMF_ZPX,`BMF_ABS,`BMF_ABSX: res <= b ^ (32'b1 << acc[4:0]);
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`BMT_ZPX,`BMT_ABS,`BMT_ABSX: res <= b & (32'b1 << acc[4:0]);
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`BMT_ZPX,`BMT_ABS,`BMT_ABSX: res <= b & (32'b1 << acc[4:0]);
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default: res <= 33'd0;
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default: res <= 33'd0;
|
endcase
|
endcase
|
endmodule
|
endmodule
|
|
|
