// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2013 Robert Finch, Stratford
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// \\__/ o\ (C) 2013 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// \/_// robfinch<remove>@opencores.org
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// ||
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// ||
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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module rtf65002_itagmem2way(whichrd, whichwr, wclk, wr, adr, rclk, pc, hit0, hit1);
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module rtf65002_itagmem2way(whichrd, whichwr, wclk, wr, adr, rclk, pc, hit0, hit1);
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output reg [1:0] whichrd;
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output reg [1:0] whichrd;
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input whichwr;
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input whichwr;
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input wclk;
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input wclk;
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input wr;
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input wr;
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input [33:0] adr;
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input [33:0] adr;
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input rclk;
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input rclk;
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input [31:0] pc;
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input [31:0] pc;
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output reg hit0;
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output reg hit0;
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output reg hit1;
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output reg hit1;
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wire [31:0] pcp8 = pc + 32'd8;
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wire [31:0] pcp8 = pc + 32'd8;
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wire [31:0] tag0a,tag0b;
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wire [31:0] tag0a,tag0b;
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wire [31:0] tag1a,tag1b;
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wire [31:0] tag1a,tag1b;
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reg [31:0] rpc;
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reg [31:0] rpc;
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reg [31:0] rpcp8;
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reg [31:0] rpcp8;
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wire hit0a,hit1a;
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wire hit0a,hit1a;
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wire hit0b,hit1b;
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wire hit0b,hit1b;
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always @(posedge rclk)
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always @(posedge rclk)
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rpc <= pc;
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rpc <= pc;
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always @(posedge rclk)
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always @(posedge rclk)
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rpcp8 <= pcp8;
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rpcp8 <= pcp8;
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syncRam512x32_1rw1r ram0 (
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syncRam512x32_1rw1r ram0 (
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.wrst(1'b0),
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.wrst(1'b0),
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.wclk(wclk),
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.wclk(wclk),
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.wce(adr[3:2]==2'b11 && !whichwr),
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.wce(!whichwr),
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.we(wr),
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.we(wr),
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.wadr(adr[12:4]),
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.wadr(adr[12:4]),
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.i(adr[31:0]),
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.i(adr[31:0]),
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.wo(),
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.wo(),
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.rrst(1'b0),
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.rrst(1'b0),
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.rclk(rclk),
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.rclk(rclk),
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.rce(1'b1),
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.rce(1'b1),
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.radr(pc[12:4]),
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.radr(pc[12:4]),
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.o(tag0a)
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.o(tag0a)
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);
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);
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syncRam512x32_1rw1r ram1 (
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syncRam512x32_1rw1r ram1 (
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.wrst(1'b0),
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.wrst(1'b0),
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.wclk(wclk),
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.wclk(wclk),
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.wce(adr[3:2]==2'b11 && !whichwr),
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.wce(!whichwr),
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.we(wr),
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.we(wr),
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.wadr(adr[12:4]),
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.wadr(adr[12:4]),
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.i(adr[31:0]),
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.i(adr[31:0]),
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.wo(),
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.wo(),
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.rrst(1'b0),
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.rrst(1'b0),
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.rclk(rclk),
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.rclk(rclk),
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.rce(1'b1),
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.rce(1'b1),
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.radr(pcp8[12:4]),
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.radr(pcp8[12:4]),
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.o(tag1a)
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.o(tag1a)
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);
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);
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syncRam512x32_1rw1r ram2 (
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syncRam512x32_1rw1r ram2 (
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.wrst(1'b0),
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.wrst(1'b0),
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.wclk(wclk),
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.wclk(wclk),
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.wce(adr[3:2]==2'b11 && whichwr),
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.wce(whichwr),
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.we(wr),
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.we(wr),
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.wadr(adr[12:4]),
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.wadr(adr[12:4]),
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.i(adr[31:0]),
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.i(adr[31:0]),
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.wo(),
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.wo(),
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.rrst(1'b0),
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.rrst(1'b0),
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.rclk(rclk),
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.rclk(rclk),
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.rce(1'b1),
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.rce(1'b1),
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.radr(pc[12:4]),
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.radr(pc[12:4]),
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.o(tag0b)
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.o(tag0b)
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);
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);
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syncRam512x32_1rw1r ram3 (
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syncRam512x32_1rw1r ram3 (
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.wrst(1'b0),
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.wrst(1'b0),
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.wclk(wclk),
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.wclk(wclk),
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.wce(adr[3:2]==2'b11 && whichwr),
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.wce(whichwr),
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.we(wr),
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.we(wr),
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.wadr(adr[12:4]),
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.wadr(adr[12:4]),
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.i(adr[31:0]),
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.i(adr[31:0]),
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.wo(),
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.wo(),
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.rrst(1'b0),
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.rrst(1'b0),
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.rclk(rclk),
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.rclk(rclk),
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.rce(1'b1),
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.rce(1'b1),
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.radr(pcp8[12:4]),
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.radr(pcp8[12:4]),
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.o(tag1b)
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.o(tag1b)
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);
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);
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assign hit0a = tag0a[31:13]==rpc[31:13] && tag0a[0];
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assign hit0a = tag0a[31:13]==rpc[31:13] && tag0a[0];
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assign hit1a = tag1a[31:13]==rpcp8[31:13] && tag1a[0];
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assign hit1a = tag1a[31:13]==rpcp8[31:13] && tag1a[0];
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assign hit0b = tag0b[31:13]==rpc[31:13] && tag0b[0];
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assign hit0b = tag0b[31:13]==rpc[31:13] && tag0b[0];
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assign hit1b = tag1b[31:13]==rpcp8[31:13] && tag1b[0];
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assign hit1b = tag1b[31:13]==rpcp8[31:13] && tag1b[0];
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always @(hit0a or hit1a or hit0b or hit1b or whichwr)
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always @(hit0a or hit1a or hit0b or hit1b or whichwr)
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if (hit0a & hit1a) begin
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if (hit0a & hit1a) begin
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hit0 <= 1'b1;
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hit0 <= 1'b1;
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hit1 <= 1'b1;
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hit1 <= 1'b1;
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whichrd <= 2'b00;
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whichrd <= 2'b00;
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end
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end
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else if (hit0b & hit1b) begin
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else if (hit0b & hit1b) begin
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hit0 <= 1'b1;
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hit0 <= 1'b1;
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hit1 <= 1'b1;
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hit1 <= 1'b1;
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whichrd <= 2'b01;
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whichrd <= 2'b01;
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end
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end
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else if (hit0a & hit1b) begin
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else if (hit0a & hit1b) begin
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hit0 <= 1'b1;
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hit0 <= 1'b1;
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hit1 <= 1'b1;
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hit1 <= 1'b1;
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whichrd <= 2'b10;
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whichrd <= 2'b10;
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end
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end
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else if (hit0b & hit1a) begin
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else if (hit0b & hit1a) begin
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hit0 <= 1'b1;
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hit0 <= 1'b1;
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hit1 <= 1'b1;
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hit1 <= 1'b1;
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whichrd <= 2'b11;
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whichrd <= 2'b11;
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end
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end
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else begin
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else begin
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whichrd <= 2'b00;
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whichrd <= 2'b00;
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if (whichwr) begin
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if (whichwr) begin
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hit0 <= hit0b;
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hit0 <= hit0b;
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hit1 <= hit1b;
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hit1 <= hit1b;
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end
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end
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else begin
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else begin
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hit0 <= hit0a;
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hit0 <= hit0a;
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hit1 <= hit1a;
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hit1 <= hit1a;
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end
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end
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end
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end
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endmodule
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endmodule
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