// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2013 Robert Finch, Stratford
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// \\__/ o\ (C) 2013 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// \/_// robfinch<remove>@opencores.org
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// ||
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// ||
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// Memory store states
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// Memory store states
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// The store states work for either eight bit or 32 bit mode
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// The store states work for either eight bit or 32 bit mode
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// ============================================================================
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// ============================================================================
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//
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//
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// Stores always write through to memory, then optionally update the cache if
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// Stores always write through to memory, then optionally update the cache if
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// there was a write hit.
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// there was a write hit.
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STORE1:
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STORE1:
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begin
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begin
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cyc_o <= 1'b1;
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cyc_o <= 1'b1;
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stb_o <= 1'b1;
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stb_o <= 1'b1;
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we_o <= 1'b1;
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we_o <= 1'b1;
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if (em || isStb)
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if (em || isStb) begin
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case(wadr2LSB)
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case(wadr2LSB)
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2'd0: sel_o <= 4'b0001;
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2'd0: sel_o <= 4'b0001;
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2'd1: sel_o <= 4'b0010;
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2'd1: sel_o <= 4'b0010;
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2'd2: sel_o <= 4'b0100;
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2'd2: sel_o <= 4'b0100;
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2'd3: sel_o <= 4'b1000;
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2'd3: sel_o <= 4'b1000;
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endcase
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endcase
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end
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else
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else
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sel_o <= 4'hf;
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sel_o <= 4'hf;
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adr_o <= {wadr,2'b00};
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adr_o <= {wadr,2'b00};
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dat_o <= wdat;
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dat_o <= wdat;
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radr <= wadr; // Do a cache read to test the hit
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radr <= wadr; // Do a cache read to test the hit
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state <= STORE2;
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state <= STORE2;
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end
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end
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// Terminal state for stores. Update the data cache if there was a cache hit.
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// Terminal state for stores. Update the data cache if there was a cache hit.
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// Clear any previously set lock status
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// Clear any previously set lock status
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STORE2:
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STORE2:
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if (ack_i) begin
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if (ack_i) begin
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if (isMove)
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if (isMove)
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state <= MVN3;
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state <= MVN3;
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else
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else
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state <= IFETCH;
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state <= IFETCH;
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lock_o <= 1'b0;
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lock_o <= 1'b0;
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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we_o <= 1'b0;
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we_o <= 1'b0;
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sel_o <= 4'h0;
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sel_o <= 4'h0;
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adr_o <= 34'h0;
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adr_o <= 34'h0;
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dat_o <= 32'h0;
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dat_o <= 32'h0;
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if (dhit) begin
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if (dhit) begin
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wrsel <= sel_o;
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wrsel <= sel_o;
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wr <= 1'b1;
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wr <= 1'b1;
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end
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end
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else if (write_allocate) begin
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else if (write_allocate) begin
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dmiss <= `TRUE;
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dmiss <= `TRUE;
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state <= WAIT_DHIT;
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state <= WAIT_DHIT;
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if (isMove)
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if (isMove)
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retstate <= MVN3;
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retstate <= MVN3;
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else
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else
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retstate <= IFETCH;
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retstate <= IFETCH;
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end
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end
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end
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end
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else if (err_i) begin
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else if (err_i) begin
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lock_o <= 1'b0;
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lock_o <= 1'b0;
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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we_o <= 1'b0;
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we_o <= 1'b0;
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sel_o <= 4'h0;
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sel_o <= 4'h0;
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dat_o <= 32'h0;
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dat_o <= 32'h0;
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state <= BUS_ERROR;
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state <= BUS_ERROR;
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end
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end
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