// ============================================================================
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// ============================================================================
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// CONTROL_LOGIC
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// CONTROL_LOGIC
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// - assorted control logic
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// - assorted control logic
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//
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//
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//
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//
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// (C) 2009,2010 Robert Finch
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// (C) 2009,2010,2013 Robert Finch
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// robfinch[remove]@opencores.org
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// robfinch[remove]@finitron.ca
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//
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// Verilog
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// Verilog
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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wire [15:0] sp_dec = sp - 16'd1;
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wire [15:0] sp_dec = sp - 16'd1;
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wire [15:0] sp_inc = sp + 16'd1;
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wire [15:0] sp_inc = sp + 16'd1;
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wire [15:0] ip_inc = ip + 16'd1;
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wire [15:0] ip_inc = ip + 16'd1;
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wire [15:0] ip_dec = ip - 16'd1;
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wire [15:0] ip_dec = ip - 16'd1;
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wire [15:0] cx_dec = cx - 16'd1;
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wire [15:0] cx_dec = cx - 16'd1;
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wire [15:0] si_dec = si - 16'd1;
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wire [15:0] si_dec = si - 16'd1;
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wire [15:0] di_dec = di - 16'd1;
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wire [15:0] di_dec = di - 16'd1;
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wire [15:0] si_inc = si + 16'd1;
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wire [15:0] si_inc = si + 16'd1;
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wire [15:0] di_inc = di + 16'd1;
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wire [15:0] di_inc = di + 16'd1;
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wire [15:0] sp_dec2 = sp - 16'd2;
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wire [15:0] sp_dec2 = sp - 16'd2;
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wire [15:0] sp_inc2 = sp + 16'd2;
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wire [15:0] sp_inc2 = sp + 16'd2;
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wire [15:0] ip_inc2 = ip + 16'd2;
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wire [15:0] ip_inc2 = ip + 16'd2;
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wire [15:0] ip_dec2 = ip - 16'd2;
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wire [15:0] ip_dec2 = ip - 16'd2;
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wire [19:0] ea_inc = ea + 20'd1;
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wire [19:0] ea_inc = ea + 20'd1;
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wire [19:0] ea_inc2 = ea + 20'd2;
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wire [19:0] ea_inc2 = ea + 20'd2;
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wire [19:0] adr_o_inc = adr_o + 20'd1;
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wire [19:0] adr_o_inc = adr_o + 20'd1;
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wire [4:0] modrm = {mod,rm};
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wire [4:0] modrm = {mod,rm};
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wire [15:0] offsdisp = offset + disp16;
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wire [15:0] offsdisp = offset + disp16;
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wire checkForInts = (prefix1==8'h00) && (prefix2==8'h00);
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wire checkForInts = (prefix1==8'h00) && (prefix2==8'h00);
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wire doCmp = ir==8'h38 || ir==8'h39 || ir==8'h3A || ir==8'h3B || ir==8'h3C || ir==8'h3D;
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wire doCmp = ir==8'h38 || ir==8'h39 || ir==8'h3A || ir==8'h3B || ir==8'h3C || ir==8'h3D;
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// Detect when to fetch the mod-r/m byte
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// Detect when to fetch the mod-r/m byte
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//
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//
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wire fetch_modrm =
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wire fetch_modrm =
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ir==8'h00 || ir==8'h01 || ir==8'h02 || ir==8'h03 || // ADD
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ir==8'h00 || ir==8'h01 || ir==8'h02 || ir==8'h03 || // ADD
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ir==8'h08 || ir==8'h09 || ir==8'h0A || ir==8'h0B || // OR
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ir==8'h08 || ir==8'h09 || ir==8'h0A || ir==8'h0B || // OR
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ir==8'h10 || ir==8'h11 || ir==8'h12 || ir==8'h13 || // ADC
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ir==8'h10 || ir==8'h11 || ir==8'h12 || ir==8'h13 || // ADC
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ir==8'h18 || ir==8'h19 || ir==8'h1A || ir==8'h1B || // SBB
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ir==8'h18 || ir==8'h19 || ir==8'h1A || ir==8'h1B || // SBB
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ir==8'h20 || ir==8'h21 || ir==8'h22 || ir==8'h23 || // AND
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ir==8'h20 || ir==8'h21 || ir==8'h22 || ir==8'h23 || // AND
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ir==8'h28 || ir==8'h29 || ir==8'h2A || ir==8'h2B || // SUB
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ir==8'h28 || ir==8'h29 || ir==8'h2A || ir==8'h2B || // SUB
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ir==8'h30 || ir==8'h31 || ir==8'h32 || ir==8'h33 || // XOR
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ir==8'h30 || ir==8'h31 || ir==8'h32 || ir==8'h33 || // XOR
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ir==8'h38 || ir==8'h39 || ir==8'h3A || ir==8'h3B || // CMP
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ir==8'h38 || ir==8'h39 || ir==8'h3A || ir==8'h3B || // CMP
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ir==8'h3C || ir==8'h3D || // CMP
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ir==8'h3C || ir==8'h3D || // CMP
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ir==8'h62 || // BOUND
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ir==8'h62 || // BOUND
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ir==8'h63 || // ARPL
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ir==8'h63 || // ARPL
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ir==8'h69 || ir==8'h6B || // IMUL
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ir==8'h69 || ir==8'h6B || // IMUL
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ir[7:4]==4'h8 ||
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ir[7:4]==4'h8 ||
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(ir[7]==1'b0 && ir[6]==1'b0 && ir[2]==1'b0) || // arithmetic
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(ir[7]==1'b0 && ir[6]==1'b0 && ir[2]==1'b0) || // arithmetic
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(ir==8'h0F && ir2[7:4]==4'hA && ir2[2:1]==2'b10) ||
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(ir==8'h0F && ir2[7:4]==4'hA && ir2[2:1]==2'b10) ||
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ir==8'hC4 || ir==8'hC5 || // LES / LDS
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ir==8'hC4 || ir==8'hC5 || // LES / LDS
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ir==8'hC6 || ir==8'hC7 || // MOV I
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ir==8'hC6 || ir==8'hC7 || // MOV I
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ir==8'hC0 || ir==8'hC1 || // shift / rotate
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ir==8'hC0 || ir==8'hC1 || // shift / rotate
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ir==8'hD0 || ir==8'hD1 || ir==8'hD2 || ir==8'hD3 || // shift / rotate
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ir==8'hD0 || ir==8'hD1 || ir==8'hD2 || ir==8'hD3 || // shift / rotate
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ir==8'hF6 || ir==8'hF7 || // NOT / NEG / TEST / MUL / IMUL / DIV / IDIV
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ir==8'hF6 || ir==8'hF7 || // NOT / NEG / TEST / MUL / IMUL / DIV / IDIV
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ir==8'hFE || ir==8'hFF // INC / DEC / CALL
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ir==8'hFE || ir==8'hFF // INC / DEC / CALL
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;
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;
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// Detect when to fetch the mod-r/m byte during a two byte opcode
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// Detect when to fetch the mod-r/m byte during a two byte opcode
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//
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//
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wire fetch_modrm2 =
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wire fetch_modrm2 =
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ir2==8'h00 || // LLDT / LTR / STR / VERR / VERW
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ir2==8'h00 || // LLDT / LTR / STR / VERR / VERW
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ir2==8'h01 || // INVLPG / LGDT / LIDT / LMSW / SGDT /
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ir2==8'h01 || // INVLPG / LGDT / LIDT / LMSW / SGDT /
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ir2==8'h02 || // LAR
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ir2==8'h02 || // LAR
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ir2==8'h03 || // LSL
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ir2==8'h03 || // LSL
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ir2[7:4]==4'h9 ||
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ir2[7:4]==4'h9 ||
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ir2==8'hA4 || ir2==8'hAC || ir2==8'hA5 || ir2==8'hAD || // SHRD / SHLD
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ir2==8'hA4 || ir2==8'hAC || ir2==8'hA5 || ir2==8'hAD || // SHRD / SHLD
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ir2==8'hAF || // IMUL
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ir2==8'hAF || // IMUL
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ir2==8'hB0 || ir2==8'hB1 || // CMPXCHG
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ir2==8'hB0 || ir2==8'hB1 || // CMPXCHG
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ir2==8'hB2 || ir2==8'hB4 || ir2==8'hB5 || // LSS / LFS / LGS
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ir2==8'hB2 || ir2==8'hB4 || ir2==8'hB5 || // LSS / LFS / LGS
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ir2==8'hB6 || ir2==8'hB7 || ir2==8'hFE || ir2==8'hFF ||
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ir2==8'hB6 || ir2==8'hB7 || ir2==8'hFE || ir2==8'hFF ||
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ir2==8'hA3 || ir2==8'hBA || ir2==8'hBB || ir2==8'hBC || ir2==8'hBD ||
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ir2==8'hA3 || ir2==8'hBA || ir2==8'hBB || ir2==8'hBC || ir2==8'hBD ||
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ir2==8'hC0 || ir2==8'hC1 // XADD
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ir2==8'hC0 || ir2==8'hC1 // XADD
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;
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;
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wire fetch_data =
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wire fetch_data =
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ir==8'h8A || ir==8'h8B || // memory to register
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ir==8'h8A || ir==8'h8B || // memory to register
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ir==8'hA0 || ir==8'hA1 || // memory to accumulator
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ir==8'hA0 || ir==8'hA1 || // memory to accumulator
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ir==8'h8E || // memory to segmenr register
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ir==8'h8E || // memory to segmenr register
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(ir==8'h0f && (ir2==8'hB6 || ir2==8'hB7 || ir2==8'hBE || ir2==8'hBf)) || // memory to register - needs more resolving.
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(ir==8'h0f && (ir2==8'hB6 || ir2==8'hB7 || ir2==8'hBE || ir2==8'hBf)) || // memory to register - needs more resolving.
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ir==`POP_AX ||
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ir==`POP_AX ||
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ir==`POP_DX ||
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ir==`POP_DX ||
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ir==`POP_CX ||
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ir==`POP_CX ||
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ir==`POP_BX ||
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ir==`POP_BX ||
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ir==`POP_SP ||
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ir==`POP_SP ||
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ir==`POP_BP ||
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ir==`POP_BP ||
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ir==`POP_SI ||
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ir==`POP_SI ||
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ir==`POP_DI ||
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ir==`POP_DI ||
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ir==8'h86 || ir==8'h87 || // exchange register with memory
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ir==8'h86 || ir==8'h87 || // exchange register with memory
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ir==`LDS ||
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ir==`LDS ||
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ir==`LES ||
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ir==`LES ||
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(ir==`EXTOP && (ir2==`LFS || ir2==`LGS || ir2==`LSS)) ||
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(ir==`EXTOP && (ir2==`LFS || ir2==`LGS || ir2==`LSS)) ||
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ir==`POPF ||
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ir==`POPF ||
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fetch_modrm;
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fetch_modrm;
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wire store_data =
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wire store_data =
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(ir==8'h0F && ir2==8'h00 && rrr==3'd0 && mod!=2'b11) || // SLDT
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(ir==8'h0F && ir2==8'h00 && rrr==3'd0 && mod!=2'b11) || // SLDT
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(ir==8'h0F && ir2==8'h00 && rrr==3'd1 && mod!=2'b11) || // STR
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(ir==8'h0F && ir2==8'h00 && rrr==3'd1 && mod!=2'b11) || // STR
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(ir==8'h0F && ir2==8'h01 && rrr==3'd0 && mod!=2'b11) || // SGDT
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(ir==8'h0F && ir2==8'h01 && rrr==3'd0 && mod!=2'b11) || // SGDT
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(ir==8'h0F && ir2==8'h01 && rrr==3'd1 && mod!=2'b11) || // SIDT
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(ir==8'h0F && ir2==8'h01 && rrr==3'd1 && mod!=2'b11) || // SIDT
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(ir==8'h0F && ir2==8'h01 && rrr==3'd4 && mod!=2'b11) || // SMSW
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(ir==8'h0F && ir2==8'h01 && rrr==3'd4 && mod!=2'b11) || // SMSW
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(ir==8'h00 && mod!=2'b11) || // ADD b
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(ir==8'h00 && mod!=2'b11) || // ADD b
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(ir==8'h01 && mod!=2'b11) || // ADD w
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(ir==8'h01 && mod!=2'b11) || // ADD w
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(ir==8'h08 && mod!=2'b11) || // OR b
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(ir==8'h08 && mod!=2'b11) || // OR b
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(ir==8'h09 && mod!=2'b11) || // OR w
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(ir==8'h09 && mod!=2'b11) || // OR w
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(ir==8'h10 && mod!=2'b11) || // ADC b
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(ir==8'h10 && mod!=2'b11) || // ADC b
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(ir==8'h11 && mod!=2'b11) || // ADC w
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(ir==8'h11 && mod!=2'b11) || // ADC w
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(ir==8'h18 && mod!=2'b11) || // SBB b
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(ir==8'h18 && mod!=2'b11) || // SBB b
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(ir==8'h19 && mod!=2'b11) || // SBB w
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(ir==8'h19 && mod!=2'b11) || // SBB w
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(ir==8'h20 && mod!=2'b11) || // AND b
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(ir==8'h20 && mod!=2'b11) || // AND b
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(ir==8'h21 && mod!=2'b11) || // AND w
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(ir==8'h21 && mod!=2'b11) || // AND w
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(ir==8'h28 && mod!=2'b11) || // SUB b
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(ir==8'h28 && mod!=2'b11) || // SUB b
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(ir==8'h29 && mod!=2'b11) || // SUB w
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(ir==8'h29 && mod!=2'b11) || // SUB w
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(ir==8'h30 && mod!=2'b11) || // XOR b
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(ir==8'h30 && mod!=2'b11) || // XOR b
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(ir==8'h31 && mod!=2'b11) || // XOR w
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(ir==8'h31 && mod!=2'b11) || // XOR w
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(ir==8'h63 && mod!=2'b11) || // ARPL
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(ir==8'h63 && mod!=2'b11) || // ARPL
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(ir==8'hD0 && mod!=2'b11) || // byte shifts #1
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(ir==8'hD0 && mod!=2'b11) || // byte shifts #1
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(ir==8'hD1 && mod!=2'b11) || // word shifts #1
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(ir==8'hD1 && mod!=2'b11) || // word shifts #1
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(ir==8'hD2 && mod!=2'b11) || // byte shifts CL
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(ir==8'hD2 && mod!=2'b11) || // byte shifts CL
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(ir==8'hD3 && mod!=2'b11) || // word shifts CL
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(ir==8'hD3 && mod!=2'b11) || // word shifts CL
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(ir==8'hC0 && mod!=2'b11) || // byte shifts #n8
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(ir==8'hC0 && mod!=2'b11) || // byte shifts #n8
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(ir==8'hC1 && mod!=2'b11) || // word shifts #n8
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(ir==8'hC1 && mod!=2'b11) || // word shifts #n8
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(hasFetchedModrm && (d==1'b0) && (mod!=2'b11)) ||
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(hasFetchedModrm && (d==1'b0) && (mod!=2'b11)) ||
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ir==8'hA2 || // MOV mem8,AL
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ir==8'hA2 || // MOV mem8,AL
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ir==8'hA3 || // MOV mem16,AL
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ir==8'hA3 || // MOV mem16,AL
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((ir==8'h86 || ir==8'h87) && (mod!=2'b11)) || // XCHG
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((ir==8'h86 || ir==8'h87) && (mod!=2'b11)) || // XCHG
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((ir==8'h88 || ir==8'h89) && (mod!=2'b11)) || // MOV
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((ir==8'h88 || ir==8'h89) && (mod!=2'b11)) || // MOV
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((ir==8'h6B || ir==8'h69) && (mod!=2'b11)) || // IMUL
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((ir==8'h6B || ir==8'h69) && (mod!=2'b11)) || // IMUL
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((ir==8'hC6 || ir==8'hC7) && rrr==3'd0 && (mod!=2'b11)) || // MOV mem,imm
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((ir==8'hC6 || ir==8'hC7) && rrr==3'd0 && (mod!=2'b11)) || // MOV mem,imm
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( ir==8'h8C && rrr[2]==1'b0 && (mod!=2'b11)) || // MOV mem16,seg_reg
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( ir==8'h8C && rrr[2]==1'b0 && (mod!=2'b11)) || // MOV mem16,seg_reg
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((ir==8'hF6 || ir==8'hF7) && rrr==3'd2 && (mod!=2'b11)) || // NOT
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((ir==8'hF6 || ir==8'hF7) && rrr==3'd2 && (mod!=2'b11)) || // NOT
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((ir==8'hF6 || ir==8'hF7) && rrr==3'd3 && (mod!=2'b11)) || // NEG
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((ir==8'hF6 || ir==8'hF7) && rrr==3'd3 && (mod!=2'b11)) || // NEG
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((ir==8'hF6 || ir==8'hF7) && rrr==3'd4 && (mod!=2'b11)) || // MUL
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((ir==8'hF6 || ir==8'hF7) && rrr==3'd4 && (mod!=2'b11)) || // MUL
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((ir==8'hF6 || ir==8'hF7) && rrr==3'd5 && (mod!=2'b11)) || // IMUL
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((ir==8'hF6 || ir==8'hF7) && rrr==3'd5 && (mod!=2'b11)) || // IMUL
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((ir==8'hF6 || ir==8'hF7) && rrr==3'd6 && (mod!=2'b11)) || // DIV
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((ir==8'hF6 || ir==8'hF7) && rrr==3'd6 && (mod!=2'b11)) || // DIV
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((ir==8'hF6 || ir==8'hF7) && rrr==3'd7 && (mod!=2'b11)) || // IDIV
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((ir==8'hF6 || ir==8'hF7) && rrr==3'd7 && (mod!=2'b11)) || // IDIV
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((ir==8'hFE || ir==8'hFF) && rrr==3'd0 && (mod!=2'b11)) || // INC
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((ir==8'hFE || ir==8'hFF) && rrr==3'd0 && (mod!=2'b11)) || // INC
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((ir==8'hFE || ir==8'hFF) && rrr==3'd1 && (mod!=2'b11)) || // DEC
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((ir==8'hFE || ir==8'hFF) && rrr==3'd1 && (mod!=2'b11)) || // DEC
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((ir==8'h80 || ir==8'h81 || ir==8'h83) && (rrr!=3'b111) && (mod!=2'b11)) // compare excluded
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((ir==8'h80 || ir==8'h81 || ir==8'h83) && (rrr!=3'b111) && (mod!=2'b11)) // compare excluded
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;
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;
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wire bus_locked = prefix1==`LOCK || prefix2==`LOCK ||
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wire bus_locked = prefix1==`LOCK || prefix2==`LOCK ||
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((ir==8'h86||ir==8'h87) && mod!=2'b11)
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((ir==8'h86||ir==8'h87) && mod!=2'b11)
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;
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;
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wire is_prefix =
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wire is_prefix =
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ir==`REPZ ||
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ir==`REPZ ||
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ir==`REPNZ ||
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ir==`REPNZ ||
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ir==`LOCK ||
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ir==`LOCK ||
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ir==`CS ||
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ir==`CS ||
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ir==`DS ||
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ir==`DS ||
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ir==`ES ||
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ir==`ES ||
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ir==`SS
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ir==`SS
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;
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;
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wire tgt_reg8 =
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wire tgt_reg8 =
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ir==8'h10 ||
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ir==8'h10 ||
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ir==8'h12
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ir==8'h12
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;
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;
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/*
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/*
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if (ir==8'h80 && mod==2'b11) tgt <= RM8; src <= IMM8;
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if (ir==8'h80 && mod==2'b11) tgt <= RM8; src <= IMM8;
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if (ir==8'h81 && mod==2'b11) tgt <= RM16; src <= IMM16;
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if (ir==8'h81 && mod==2'b11) tgt <= RM16; src <= IMM16;
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if (ir==8'h83 && mod==2'b11) tgt <= RM16; src <= IMM8;
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if (ir==8'h83 && mod==2'b11) tgt <= RM16; src <= IMM8;
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if (ir==8'h80 && mod!=2'b11) tgt <= MEM8; src <= IMM8;
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if (ir==8'h80 && mod!=2'b11) tgt <= MEM8; src <= IMM8;
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if (ir==8'h81 && mod!=2'b11) tgt <= MEM16; src <= IMM16;
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if (ir==8'h81 && mod!=2'b11) tgt <= MEM16; src <= IMM16;
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if (ir==8'h83 && mod!=2'b11) tgt <= MEM16; src <= IMM8;
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if (ir==8'h83 && mod!=2'b11) tgt <= MEM16; src <= IMM8;
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case(rrr)
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case(rrr)
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3'b000: op <= `ADD;
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3'b000: op <= `ADD;
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3'b010: op <= `ADC;
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3'b010: op <= `ADC;
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3'b100: op <= `AND;
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3'b100: op <= `AND;
|
3'b111: op <= `CMP;
|
3'b111: op <= `CMP;
|
endcase
|
endcase
|
*/
|
*/
|
|
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
wire lea = ir==`LEA;
|
wire lea = ir==`LEA;
|
|
|
wire hasPrefix = prefix1!=8'h00;
|
wire hasPrefix = prefix1!=8'h00;
|
wire hasDoublePrefix = hasPrefix && prefix2!=8'h00;
|
wire hasDoublePrefix = hasPrefix && prefix2!=8'h00;
|
wire repz = prefix1==`REPZ || prefix2==`REPZ;
|
wire repz = prefix1==`REPZ || prefix2==`REPZ;
|
wire repnz = prefix1==`REPNZ || prefix2==`REPNZ;
|
wire repnz = prefix1==`REPNZ || prefix2==`REPNZ;
|
|
|
|
// ZF is tested only for SCAS, CMPS
|
wire repdone =
|
wire repdone =
|
((repz | repnz) & cxz) ||
|
((repz | repnz) & cxz) ||
|
(repz & !zf) ||
|
(repz && !zf && (ir==`SCASB||ir==`SCASW||ir==`CMPSB||ir==`CMPSW)) ||
|
(repnz & zf)
|
(repnz && zf && (ir==`SCASB||ir==`SCASW||ir==`CMPSB||ir==`CMPSW))
|
;
|
;
|
|
|
|
|
