// ============================================================================
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// ============================================================================
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// DECODE
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// DECODE
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// - decode / dispatch instruction
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// - decode / dispatch instruction
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//
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//
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//
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//
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// (C) 2009-2012 Robert Finch
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// (C) 2009-2012 Robert Finch
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// Stratford
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// Stratford
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// robfinch[remove]@opencores.org
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// robfinch[remove]@opencores.org
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//
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// Verilog
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// Verilog
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//
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//
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// Decode / dispatch instruction
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// Decode / dispatch instruction
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// ============================================================================
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// ============================================================================
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//
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//
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DECODE:
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DECODE:
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casex(ir)
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casex(ir)
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`MORE1: state <= XI_FETCH;
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`MORE1: state <= XI_FETCH;
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`MORE2: state <= XI_FETCH;
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`MORE2: state <= XI_FETCH;
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`EXTOP: state <= XI_FETCH;
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`EXTOP: state <= XI_FETCH;
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`DEC_REG,`INC_REG:
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`DEC_REG,`INC_REG:
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begin
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begin
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w <= 1'b1;
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w <= 1'b1;
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rrr <= ir[2:0];
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rrr <= ir[2:0];
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state <= EXECUTE;
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state <= REGFETCHA;
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end
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end
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`LEA: state <= EXECUTE;
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`LEA: state <= EXECUTE;
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Immediate Loads
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// Immediate Loads
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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`MOV_I2AL,`MOV_I2DL,`MOV_I2CL,`MOV_I2BL,`MOV_I2AH,`MOV_I2DH,`MOV_I2CH,`MOV_I2BH:
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`MOV_I2AL,`MOV_I2DL,`MOV_I2CL,`MOV_I2BL,`MOV_I2AH,`MOV_I2DH,`MOV_I2CH,`MOV_I2BH:
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begin
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begin
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`INITIATE_CODE_READ
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`INITIATE_CODE_READ
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state <= MOV_I2BYTREG;
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state <= MOV_I2BYTREG;
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end
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end
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`MOV_I2AX,`MOV_I2DX,`MOV_I2CX,`MOV_I2BX,`MOV_I2SP,`MOV_I2BP,`MOV_I2SI,`MOV_I2DI:
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`MOV_I2AX,`MOV_I2DX,`MOV_I2CX,`MOV_I2BX,`MOV_I2SP,`MOV_I2BP,`MOV_I2SI,`MOV_I2DI:
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begin
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begin
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w <= 1'b1;
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w <= 1'b1;
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rrr <= ir[2:0];
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rrr <= ir[2:0];
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if (ip==16'hFFFF) begin
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if (ip==16'hFFFF) begin
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int_num <= 8'h0d;
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int_num <= 8'h0d;
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state <= INT2;
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state <= INT2;
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end
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end
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else
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else
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state <= FETCH_IMM16;
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state <= FETCH_IMM16;
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end
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end
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`XLAT:
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`XLAT:
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if (!cyc_o) begin
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if (!cyc_o) begin
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cyc_type <= `CT_RDMEM;
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cyc_type <= `CT_RDMEM;
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cyc_o <= 1'b1;
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cyc_o <= 1'b1;
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stb_o <= 1'b1;
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stb_o <= 1'b1;
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adr_o <= {seg_reg,`SEG_SHIFT} + bx + al;
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adr_o <= {seg_reg,`SEG_SHIFT} + bx + al;
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end
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end
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else if (ack_i) begin
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else if (ack_i) begin
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cyc_type <= `CT_PASSIVE;
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cyc_type <= `CT_PASSIVE;
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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res <= dat_i;
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res <= dat_i;
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wrregs <= 1'b1;
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wrregs <= 1'b1;
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w <= 1'b0;
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w <= 1'b0;
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rrr <= 3'd0;
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rrr <= 3'd0;
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state <= IFETCH;
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state <= IFETCH;
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end
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end
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Arithmetic Operations
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// Arithmetic Operations
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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`AAA,`AAS:
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`AAA,`AAS:
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begin
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begin
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state <= IFETCH;
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state <= IFETCH;
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wrregs <= 1'b1;
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wrregs <= 1'b1;
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w <= 1'b1;
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w <= 1'b1;
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rrr <= 3'd0;
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rrr <= 3'd0;
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res <= alu_o;
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res <= alu_o;
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af <= (al[3:0]>4'h9 || af);
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af <= (al[3:0]>4'h9 || af);
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cf <= (al[3:0]>4'h9 || af);
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cf <= (al[3:0]>4'h9 || af);
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end
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end
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`ADD_ALI8,`ADC_ALI8,`SUB_ALI8,`SBB_ALI8,`AND_ALI8,`OR_ALI8,`XOR_ALI8,`CMP_ALI8:
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`ADD_ALI8,`ADC_ALI8,`SUB_ALI8,`SBB_ALI8,`AND_ALI8,`OR_ALI8,`XOR_ALI8,`CMP_ALI8:
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begin
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begin
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w <= 1'b0;
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w <= 1'b0;
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a <= {{8{al[7]}},al};
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a <= {{8{al[7]}},al};
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rrr <= 3'd0;
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rrr <= 3'd0;
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state <= FETCH_IMM8;
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state <= FETCH_IMM8;
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end
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end
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`ADD_AXI16,`ADC_AXI16,`SUB_AXI16,`SBB_AXI16,`AND_AXI16,`OR_AXI16,`XOR_AXI16,`CMP_AXI16:
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`ADD_AXI16,`ADC_AXI16,`SUB_AXI16,`SBB_AXI16,`AND_AXI16,`OR_AXI16,`XOR_AXI16,`CMP_AXI16:
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begin
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begin
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w <= 1'b1;
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w <= 1'b1;
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a <= ax;
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a <= ax;
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rrr <= 3'd0;
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rrr <= 3'd0;
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if (ip==16'hFFFF) begin
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if (ip==16'hFFFF) begin
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int_num <= 8'h0d;
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int_num <= 8'h0d;
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state <= INT2;
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state <= INT2;
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end
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end
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else
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else
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state <= FETCH_IMM16;
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state <= FETCH_IMM16;
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end
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end
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`ALU_I2R8:
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`ALU_I2R8:
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begin
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begin
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state <= FETCH_IMM8;
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state <= FETCH_IMM8;
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a <= rrro;
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a <= rrro;
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end
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end
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`ALU_I2R16:
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`ALU_I2R16:
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begin
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begin
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state <= FETCH_IMM16;
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state <= FETCH_IMM16;
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a <= rrro;
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a <= rrro;
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end
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end
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`XCHG_AXR:
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`XCHG_AXR:
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begin
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begin
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state <= IFETCH;
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state <= IFETCH;
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wrregs <= 1'b1;
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wrregs <= 1'b1;
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w <= 1'b1;
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w <= 1'b1;
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rrr <= ir[2:0];
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rrr <= ir[2:0];
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res <= ax;
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res <= ax;
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case(ir[2:0])
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case(ir[2:0])
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3'd0: ax <= ax;
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3'd0: ax <= ax;
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3'd1: ax <= cx;
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3'd1: ax <= cx;
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3'd2: ax <= dx;
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3'd2: ax <= dx;
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3'd3: ax <= bx;
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3'd3: ax <= bx;
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3'd4: ax <= sp;
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3'd4: ax <= sp;
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3'd5: ax <= bp;
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3'd5: ax <= bp;
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3'd6: ax <= si;
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3'd6: ax <= si;
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3'd7: ax <= di;
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3'd7: ax <= di;
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endcase
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endcase
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end
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end
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`CBW: begin ax[15:8] <= {8{ax[7]}}; state <= IFETCH; end
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`CBW: begin ax[15:8] <= {8{ax[7]}}; state <= IFETCH; end
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`CWD:
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`CWD:
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begin
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begin
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state <= IFETCH;
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state <= IFETCH;
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wrregs <= 1'b1;
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wrregs <= 1'b1;
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w <= 1'b1;
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w <= 1'b1;
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rrr <= 3'd2;
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rrr <= 3'd2;
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res <= {16{ax[15]}};
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res <= {16{ax[15]}};
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end
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end
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// String Operations
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// String Operations
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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`LODSB: state <= LODS;
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`LODSB: state <= LODS;
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`LODSW: state <= LODS;
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`LODSW: state <= LODS;
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`STOSB: state <= STOS;
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`STOSB: state <= STOS;
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`STOSW: state <= STOS;
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`STOSW: state <= STOS;
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`MOVSB: state <= MOVS;
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`MOVSB: state <= MOVS;
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`MOVSW: state <= MOVS;
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`MOVSW: state <= MOVS;
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`CMPSB: state <= CMPSB;
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`CMPSB: state <= CMPSB;
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`CMPSW: state <= CMPSW;
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`CMPSW: state <= CMPSW;
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`SCASB: state <= SCASB;
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`SCASB: state <= SCASB;
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`SCASW: state <= SCASW;
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`SCASW: state <= SCASW;
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Stack Operations
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// Stack Operations
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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`PUSH_REG: begin sp <= sp_dec; state <= PUSH; end
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`PUSH_REG: begin sp <= sp_dec; state <= PUSH; end
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`PUSH_DS: begin sp <= sp_dec; state <= PUSH; end
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`PUSH_DS: begin sp <= sp_dec; state <= PUSH; end
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`PUSH_ES: begin sp <= sp_dec; state <= PUSH; end
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`PUSH_ES: begin sp <= sp_dec; state <= PUSH; end
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`PUSH_SS: begin sp <= sp_dec; state <= PUSH; end
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`PUSH_SS: begin sp <= sp_dec; state <= PUSH; end
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`PUSH_CS: begin sp <= sp_dec; state <= PUSH; end
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`PUSH_CS: begin sp <= sp_dec; state <= PUSH; end
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`PUSHF: begin sp <= sp_dec; state <= PUSH; end
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`PUSHF: begin sp <= sp_dec; state <= PUSH; end
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`POP_REG: state <= POP;
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`POP_REG: state <= POP;
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`POP_DS: state <= POP;
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`POP_DS: state <= POP;
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`POP_ES: state <= POP;
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`POP_ES: state <= POP;
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`POP_SS: state <= POP;
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`POP_SS: state <= POP;
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`POPF: state <= POP;
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`POPF: state <= POP;
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Flow controls
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// Flow controls
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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`NOP: state <= IFETCH;
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`NOP: state <= IFETCH;
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`HLT: if (pe_nmi | (irq_i & ie)) state <= IFETCH;
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`HLT: if (pe_nmi | (irq_i & ie)) state <= IFETCH;
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`WAI: if (!busy_i) state <= IFETCH;
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`WAI: if (!busy_i) state <= IFETCH;
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`LOOP: begin cx <= cx_dec; state <= BRANCH1; end
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`LOOP: begin cx <= cx_dec; state <= BRANCH1; end
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`LOOPZ: begin cx <= cx_dec; state <= BRANCH1; end
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`LOOPZ: begin cx <= cx_dec; state <= BRANCH1; end
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`LOOPNZ: begin cx <= cx_dec; state <= BRANCH1; end
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`LOOPNZ: begin cx <= cx_dec; state <= BRANCH1; end
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`Jcc: state <= BRANCH1;
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`Jcc: state <= BRANCH1;
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`JCXZ: state <= BRANCH1;
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`JCXZ: state <= BRANCH1;
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`JMPS: state <= BRANCH1;
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`JMPS: state <= BRANCH1;
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`JMPF: state <= FETCH_OFFSET;
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`JMPF: state <= FETCH_OFFSET;
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`CALL: begin sp <= sp_dec; state <= FETCH_DISP16; end
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`CALL: begin sp <= sp_dec; state <= FETCH_DISP16; end
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`CALLF: begin sp <= sp_dec; state <= FETCH_OFFSET; end
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`CALLF: begin sp <= sp_dec; state <= FETCH_OFFSET; end
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`RET: state <= RETPOP; // data16 is zero
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`RET: state <= RETPOP; // data16 is zero
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`RETPOP: state <= FETCH_STK_ADJ1;
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`RETPOP: state <= FETCH_STK_ADJ1;
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`RETF: state <= RETFPOP; // data16 is zero
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`RETF: state <= RETFPOP; // data16 is zero
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`RETFPOP: state <= FETCH_STK_ADJ1;
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`RETFPOP: state <= FETCH_STK_ADJ1;
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`IRET: state <= IRET1;
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`IRET: state <= IRET1;
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`INT: state <= INT;
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`INT: state <= INT;
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`INT3: begin int_num <= 8'd3; state <= INT2; end
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`INT3: begin int_num <= 8'd3; state <= INT2; end
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`INTO:
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`INTO:
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if (vf) begin
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if (vf) begin
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int_num <= 8'd4;
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int_num <= 8'd4;
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state <= INT2;
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state <= INT2;
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end
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end
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else
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else
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state <= IFETCH;
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state <= IFETCH;
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Flag register operations
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// Flag register operations
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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`STI: begin ie <= 1'b1; state <= IFETCH; end
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`STI: begin ie <= 1'b1; state <= IFETCH; end
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`CLI: begin ie <= 1'b0; state <= IFETCH; end
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`CLI: begin ie <= 1'b0; state <= IFETCH; end
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`STD: begin df <= 1'b1; state <= IFETCH; end
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`STD: begin df <= 1'b1; state <= IFETCH; end
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`CLD: begin df <= 1'b0; state <= IFETCH; end
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`CLD: begin df <= 1'b0; state <= IFETCH; end
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`STC: begin cf <= 1'b1; state <= IFETCH; end
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`STC: begin cf <= 1'b1; state <= IFETCH; end
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`CLC: begin cf <= 1'b0; state <= IFETCH; end
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`CLC: begin cf <= 1'b0; state <= IFETCH; end
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`CMC: begin cf <= !cf; state <= IFETCH; end
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`CMC: begin cf <= !cf; state <= IFETCH; end
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`LAHF:
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`LAHF:
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begin
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begin
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ax[15] <= sf;
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ax[15] <= sf;
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ax[14] <= zf;
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ax[14] <= zf;
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ax[12] <= af;
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ax[12] <= af;
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ax[10] <= pf;
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ax[10] <= pf;
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ax[8] <= cf;
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ax[8] <= cf;
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state <= IFETCH;
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state <= IFETCH;
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end
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end
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`SAHF:
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`SAHF:
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begin
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begin
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sf <= ah[7];
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sf <= ah[7];
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zf <= ah[6];
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zf <= ah[6];
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af <= ah[4];
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af <= ah[4];
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pf <= ah[2];
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pf <= ah[2];
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cf <= ah[0];
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cf <= ah[0];
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state <= IFETCH;
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state <= IFETCH;
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end
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end
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|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
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// IO instructions
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// IO instructions
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// - fetch port number, then vector
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// - fetch port number, then vector
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//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
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`INB: state <= INB;
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`INB: state <= INB;
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`INW: state <= INW;
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`INW: state <= INW;
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`OUTB: state <= OUTB;
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`OUTB: state <= OUTB;
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`OUTW: state <= OUTW;
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`OUTW: state <= OUTW;
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`INB_DX: begin ea <= {`SEG_SHIFT,dx}; state <= INB1; end
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`INB_DX: begin ea <= {`SEG_SHIFT,dx}; state <= INB1; end
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`INW_DX: begin ea <= {`SEG_SHIFT,dx}; state <= INW1; end
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`INW_DX: begin ea <= {`SEG_SHIFT,dx}; state <= INW1; end
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`OUTB_DX: begin ea <= {`SEG_SHIFT,dx}; state <= OUTB1; end
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`OUTB_DX: begin ea <= {`SEG_SHIFT,dx}; state <= OUTB1; end
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`OUTW_DX: begin ea <= {`SEG_SHIFT,dx}; state <= OUTW1; end
|
`OUTW_DX: begin ea <= {`SEG_SHIFT,dx}; state <= OUTW1; end
|
`INSB: state <= INSB;
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`INSB: state <= INSB;
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`OUTSB: state <= OUTSB;
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`OUTSB: state <= OUTSB;
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`OUTSW: state <= OUTSW;
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`OUTSW: state <= OUTSW;
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Control Prefix
|
// Control Prefix
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
`LOCK: begin lock_insn <= ir; state <= IFETCH; end
|
`LOCK: begin lock_insn <= ir; state <= IFETCH; end
|
`REPZ,`REPNZ,`CS,`DS,`ES,`SS: state <= IFETCH;
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`REPZ,`REPNZ,`CS,`DS,`ES,`SS: state <= IFETCH;
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// disp16 instructions
|
// disp16 instructions
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
`MOV_M2AL,`MOV_M2AX,`MOV_AL2M,`MOV_AX2M,`CALL,`JMP:
|
`MOV_M2AL,`MOV_M2AX,`MOV_AL2M,`MOV_AX2M,`CALL,`JMP:
|
begin
|
begin
|
`INITIATE_CODE_READ
|
`INITIATE_CODE_READ
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state <= FETCH_DISP16_ACK;
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state <= FETCH_DISP16_ACK;
|
end
|
end
|
|
|
default:
|
default:
|
begin
|
begin
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// MOD/RM instructions
|
// MOD/RM instructions
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
$display("Fetching mod/rm");
|
$display("Fetching mod/rm");
|
if (ir==`MOV_R2S || ir==`MOV_S2R)
|
if (ir==`MOV_R2S || ir==`MOV_S2R)
|
w <= 1'b1;
|
w <= 1'b1;
|
if (ir==`LDS || ir==`LES)
|
if (ir==`LDS || ir==`LES)
|
w <= 1'b1;
|
w <= 1'b1;
|
if (fetch_modrm) begin
|
if (fetch_modrm) begin
|
`INITIATE_CODE_READ
|
`INITIATE_CODE_READ
|
state <= EACALC;
|
state <= EACALC;
|
end
|
end
|
else
|
else
|
state <= IFETCH;
|
state <= IFETCH;
|
end
|
end
|
endcase
|
endcase
|
|
|
