// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2006-2022 Robert Finch, Waterloo
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// \\__/ o\ (C) 2006-2023 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// rfTextController.sv
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// rfTextController.sv
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// text controller
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// text controller
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//
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//
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// BSD 3-Clause License
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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// 1. Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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// list of conditions and the following disclaimer.
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//
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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// this software without specific prior written permission.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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//
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//
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// Text Controller
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// Text Controller
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//
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//
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// FEATURES
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// FEATURES
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//
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//
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// This core requires an external timing generator to provide horizontal
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// This core requires an external timing generator to provide horizontal
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// and vertical sync signals, but otherwise can be used as a display
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// and vertical sync signals, but otherwise can be used as a display
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// controller on it's own. However, this core may also be embedded within
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// controller on it's own. However, this core may also be embedded within
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// another core such as a VGA controller.
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// another core such as a VGA controller.
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//
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//
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// Window positions are referenced to the rising edge of the vertical and
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// Window positions are referenced to the rising edge of the vertical and
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// horizontal sync pulses.
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// horizontal sync pulses.
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//
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//
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// The core includes an embedded dual port RAM to hold the screen
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// The core includes an embedded dual port RAM to hold the screen
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// characters.
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// characters.
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//
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//
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// The controller expects a 128kB memory region to be reserved.
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// The controller expects a 256kB memory region to be reserved.
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//
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//
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// Memory Map:
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// Memory Map:
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// 00000-0FFFF display ram
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// 00000-3FFFF display ram
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// 10000-1FEFF character bitmap ram
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// 40000-7FFFF character bitmap ram
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// 1FF00-1FFFF controller registers
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// 80000-800FF controller registers
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//
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//
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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// Registers
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// Registers
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//
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//
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// 00h
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// 00h
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// 7 - 0 cccccccc number of columns (horizontal displayed number of characters)
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// 7 - 0 cccccccc number of columns (horizontal displayed number of characters)
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// 15- 8 rrrrrrrr number of rows (vertical displayed number of characters)
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// 15- 8 rrrrrrrr number of rows (vertical displayed number of characters)
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// 19-16 dddd character output delay
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// 19-16 dddd character output delay
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// 43-32 nnnn nnnnnnnn window left (horizontal sync position - reference for left edge of displayed)
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// 43-32 nnnn nnnnnnnn window left (horizontal sync position - reference for left edge of displayed)
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// 59-48 nnnn nnnnnnnn window top (vertical sync position - reference for the top edge of displayed)
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// 59-48 nnnn nnnnnnnn window top (vertical sync position - reference for the top edge of displayed)
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// 08h
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// 08h
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// 5- 0 nnnnnn char height in pixels, maximum scan line
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// 5- 0 nnnnnn char height in pixels, maximum scan line
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// 11- 8 wwww pixel size - width
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// 11- 8 wwww pixel size - width
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// 15-12 hhhh pixel size - height
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// 15-12 hhhh pixel size - height
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// 21-16 nnnnnn char width in pixels
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// 21-16 nnnnnn char width in pixels
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// 24 r reset state bit
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// 24 r reset state bit
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// 32 e controller enable
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// 32 e controller enable
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// 40 m multi-color mode
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// 40 m multi-color mode
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// 41 a anti-alias mode
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// 48-52 nnnnn yscroll
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// 48-52 nnnnn yscroll
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// 56-60 nnnnn xscroll
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// 56-60 nnnnn xscroll
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// 10h
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// 10h
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// 30- 0 cccccccc cccccccc color code for transparent background RGB 4,9,9,9 (only RGB 7,7,7 used)
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// 30- 0 cccccccc cccccccc color code for transparent background RGB 4,9,9,9 (only RGB 7,7,7 used)
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// 63-32 cccc...cccc border color ZRGB 4,9,9,9
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// 63-32 cccc...cccc border color ZRGB 4,9,9,9
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// 18h
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// 18h
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// 30- 0 cccccccc cccccccc tile color code 1
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// 30- 0 cccccccc cccccccc tile color code 1
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// 62-32 cccccccc cccccccc tile color code 2
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// 62-32 cccccccc cccccccc tile color code 2
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// 20h
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// 20h
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// 4- 0 eeeee cursor end
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// 4- 0 eeeee cursor end
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// 7- 5 bbb blink control
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// 7- 5 bbb blink control
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// BP: 00=no blink
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// BP: 00=no blink
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// BP: 01=no display
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// BP: 01=no display
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// BP: 10=1/16 field rate blink
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// BP: 10=1/16 field rate blink
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// BP: 11=1/32 field rate blink
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// BP: 11=1/32 field rate blink
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// 12- 8 sssss cursor start
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// 12- 8 sssss cursor start
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// 15-13 ttt cursor image type (none, box, underline, sidebar, checker, solid
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// 15-13 ttt cursor image type (none, box, underline, sidebar, checker, solid
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// 47-32 aaaaaaaa aaaaaaaa cursor position
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// 47-32 aaaaaaaa aaaaaaaa cursor position
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// 28h
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// 28h
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// 15- 0 aaaaaaaa aaaaaaaa start address (index into display memory)
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// 15- 0 aaaaaaaa aaaaaaaa start address (index into display memory)
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// 30h
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// 30h
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// 15- 0 aaaaaaaa aaaaaaaa font address in char bitmap memory
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// 15- 0 aaaaaaaa aaaaaaaa font address in char bitmap memory
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// 31-24 dddddd font ascent
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// 31-24 dddddd font ascent
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// 63-32 nnnnnnnn nnnnnnnn font ram lock "LOCK" or "UNLK"
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// 63-32 nnnnnnnn nnnnnnnn font ram lock "LOCK" or "UNLK"
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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//
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//
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// 1209 LUTs / 1003 FFs / 48 BRAMs / 1 DSP
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// ============================================================================
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// ============================================================================
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//`define USE_CLOCK_GATE
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//`define USE_CLOCK_GATE
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//`define SUPPORT_AAM 1
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`define TC_RAM_ADDR 32'hEC000001
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`define TC_CBM_ADDR 32'hEC040001
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`define TC_REG_ADDR 32'hEC080001
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module rfTextController(
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module rfTextController(
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rst_i, clk_i, cs_i,
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rst_i, clk_i, cs_config_i, cs_io_i,
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cti_i, cyc_i, stb_i, ack_o, wr_i, sel_i, adr_i, dat_i, dat_o,
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cti_i, cyc_i, stb_i, ack_o, wr_i, sel_i, adr_i, dat_i, dat_o,
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dot_clk_i, hsync_i, vsync_i, blank_i, border_i, zrgb_i, zrgb_o, xonoff_i
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dot_clk_i, hsync_i, vsync_i, blank_i, border_i, zrgb_i, zrgb_o, xonoff_i
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);
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);
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parameter num = 4'd1;
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parameter num = 4'd1;
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parameter COLS = 8'd64;
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parameter COLS = 8'd64;
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parameter ROWS = 8'd32;
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parameter ROWS = 8'd32;
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parameter BUSWID = 64;
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parameter BUSWID = 32;
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parameter TEXT_CELL_COUNT = 8192;
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parameter CFG_BUS = 8'd0;
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parameter CFG_DEVICE = 5'd1;
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parameter CFG_FUNC = 3'd0;
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parameter CFG_VENDOR_ID = 16'h0;
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parameter CFG_DEVICE_ID = 16'h0;
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parameter CFG_SUBSYSTEM_VENDOR_ID = 16'h0;
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parameter CFG_SUBSYSTEM_ID = 16'h0;
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parameter CFG_ROM_ADDR = 32'hFFFFFFF0;
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// Syscon
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// Syscon
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input rst_i; // reset
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input rst_i; // reset
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input clk_i; // clock
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input clk_i; // clock
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input cs_config_i;
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input cs_io_i;
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// Slave signals
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// Slave signals
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input cs_i; // circuit select
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input [2:0] cti_i;
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input [2:0] cti_i;
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input cyc_i; // valid bus cycle
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input cyc_i; // valid bus cycle
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input stb_i; // data strobe
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input stb_i; // data strobe
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output ack_o; // data acknowledge
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output ack_o; // data acknowledge
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input wr_i; // write
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input wr_i; // write
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input [BUSWID/8-1:0] sel_i; // byte lane select
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input [BUSWID/8-1:0] sel_i; // byte lane select
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input [16:0] adr_i; // address
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input [31:0] adr_i; // address
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input [BUSWID-1:0] dat_i; // data input
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input [BUSWID-1:0] dat_i; // data input
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output reg [BUSWID-1:0] dat_o; // data output
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output reg [BUSWID-1:0] dat_o; // data output
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// Video signals
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// Video signals
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input dot_clk_i; // video dot clock
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input dot_clk_i; // video dot clock
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input hsync_i; // end of scan line
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input hsync_i; // end of scan line
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input vsync_i; // end of frame
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input vsync_i; // end of frame
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input blank_i; // blanking signal
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input blank_i; // blanking signal
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input border_i; // border area
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input border_i; // border area
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input [39:0] zrgb_i; // input pixel stream
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input [39:0] zrgb_i; // input pixel stream
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output reg [39:0] zrgb_o; // output pixel stream
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output reg [39:0] zrgb_o; // output pixel stream
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input xonoff_i;
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input xonoff_i;
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integer n2,n3;
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reg controller_enable;
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reg controller_enable;
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reg [39:0] bkColor40, bkColor40d, bkColor40d2; // background color
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reg [39:0] bkColor40, bkColor40d, bkColor40d2, bkColor40d3; // background color
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reg [39:0] fgColor40, fgColor40d, fgColor40d2; // foreground color
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reg [39:0] fgColor40, fgColor40d, fgColor40d2, fgColor40d3; // foreground color
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wire [1:0] pix; // pixel value from character generator 1=on,0=off
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wire [1:0] pix; // pixel value from character generator 1=on,0=off
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reg por;
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reg por;
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wire vclk;
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wire vclk;
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assign txt_clk_o = vclk;
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assign txt_we_o = por;
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assign txt_sel_o = 8'hFF;
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assign cbm_clk_o = vclk;
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assign cbm_we_o = 1'b0;
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assign cbm_sel_o = 8'hFF;
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reg [63:0] rego;
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reg [63:0] rego;
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reg [5:0] yscroll;
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reg [5:0] yscroll;
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reg [5:0] xscroll;
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reg [5:0] xscroll;
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reg [11:0] windowTop;
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reg [11:0] windowTop;
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reg [11:0] windowLeft;
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reg [11:0] windowLeft;
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reg [ 7:0] numCols;
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reg [ 7:0] numCols;
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reg [ 7:0] numRows;
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reg [ 7:0] numRows;
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reg [ 7:0] charOutDelay;
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reg [ 7:0] charOutDelay;
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reg [ 1:0] mode;
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reg [ 1:0] mode;
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reg [ 5:0] maxRowScan;
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reg [ 5:0] maxRowScan;
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reg [ 5:0] maxScanpix;
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reg [ 5:0] maxScanpix;
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reg [1:0] tileWidth; // width of tile in bytes (0=1,1=2,2=4,3=8)
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reg [1:0] tileWidth; // width of tile in bytes (0=1,1=2,2=4,3=8)
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reg [ 5:0] cursorStart, cursorEnd;
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reg [ 5:0] cursorStart, cursorEnd;
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reg [15:0] cursorPos;
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reg [15:0] cursorPos;
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reg [2:0] cursorType;
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reg [2:0] cursorType;
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reg [15:0] startAddress;
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reg [15:0] startAddress;
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reg [15:0] fontAddress;
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reg [15:0] fontAddress;
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reg font_locked;
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reg font_locked;
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reg [5:0] fontAscent;
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reg [5:0] fontAscent;
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reg [ 2:0] rBlink;
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reg [ 2:0] rBlink;
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reg [31:0] bdrColor; // Border color
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reg [31:0] bdrColor; // Border color
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reg [ 3:0] pixelWidth; // horizontal pixel width in clock cycles
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reg [ 3:0] pixelWidth; // horizontal pixel width in clock cycles
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reg [ 3:0] pixelHeight; // vertical pixel height in scan lines
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reg [ 3:0] pixelHeight; // vertical pixel height in scan lines
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reg mcm; // multi-color mode
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reg mcm; // multi-color mode
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reg aam; // anti-alias mode
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wire [11:0] hctr; // horizontal reference counter (counts clocks since hSync)
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wire [11:0] hctr; // horizontal reference counter (counts clocks since hSync)
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wire [11:0] scanline; // scan line
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wire [11:0] scanline; // scan line
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reg [ 7:0] row; // vertical reference counter (counts rows since vSync)
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reg [ 7:0] row; // vertical reference counter (counts rows since vSync)
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reg [ 7:0] col; // horizontal column
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reg [ 7:0] col; // horizontal column
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reg [ 5:0] rowscan; // scan line within row
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reg [ 5:0] rowscan; // scan line within row
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reg [ 5:0] colscan; // pixel column number within cell
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reg [ 5:0] colscan; // pixel column number within cell
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wire nxt_row; // when to increment the row counter
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wire nxt_row; // when to increment the row counter
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wire nxt_col; // when to increment the column counter
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wire nxt_col; // when to increment the column counter
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reg [ 5:0] bcnt; // blink timing counter
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reg [ 5:0] bcnt; // blink timing counter
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wire blink;
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wire blink;
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reg iblank;
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reg iblank;
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reg [5:0] maxScanlinePlusOne;
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reg [5:0] maxScanlinePlusOne;
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wire nhp; // next horizontal pixel
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wire nhp; // next horizontal pixel
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wire ld_shft = nxt_col & nhp;
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wire ld_shft = nxt_col & nhp;
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// display and timing signals
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// display and timing signals
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reg [15:0] txtAddr; // index into memory
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reg [15:0] txtAddr; // index into memory
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reg [15:0] penAddr;
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reg [15:0] penAddr;
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wire [63:0] screen_ram_out; // character code
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wire [63:0] screen_ram_out; // character code
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wire [20:0] txtBkColor; // background color code
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wire [20:0] txtBkColor; // background color code
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wire [20:0] txtFgColor; // foreground color code
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wire [20:0] txtFgColor; // foreground color code
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wire [5:0] txtZorder;
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wire [5:0] txtZorder;
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reg [30:0] txtTcCode; // transparent color code
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reg [30:0] txtTcCode; // transparent color code
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reg [30:0] tileColor1;
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reg [30:0] tileColor1;
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reg [30:0] tileColor2;
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reg [30:0] tileColor2;
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reg bgt, bgtd, bgtd2;
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reg bgt, bgtd, bgtd2;
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wire [63:0] tdat_o;
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wire [63:0] tdat_o;
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wire [63:0] chdat_o;
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wire [63:0] chdat_o;
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reg [63:0] cfg_dat [0:31];
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reg [63:0] cfg_out;
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function [63:0] fnRbo;
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input n;
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input [63:0] i;
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fnRbo = n ? {i[7:0],i[15:8],i[23:16],i[31:24],i[39:32],i[47:40],i[55:48],i[63:56]} : i;
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endfunction
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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// bus interfacing
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// bus interfacing
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// Address Decoding
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// Address Decoding
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// I/O range Dx
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// I/O range Dx
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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// Register the inputs
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// Register the inputs
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reg cs_config;
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reg cs_rom, cs_reg, cs_text, cs_any;
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reg cs_rom, cs_reg, cs_text, cs_any;
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reg [16:0] radr_i;
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reg cs_rom1, cs_reg1, cs_text1;
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reg cs_tc;
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reg [17:0] radr_i;
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reg [63:0] rdat_i;
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reg [63:0] rdat_i;
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reg rwr_i;
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reg rwr_i;
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reg [7:0] rsel_i;
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reg [7:0] rsel_i;
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reg [7:0] wrs_i;
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reg [7:0] wrs_i;
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reg [31:0] tc_ram_addr;
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reg [31:0] tc_cbm_addr;
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reg [31:0] tc_reg_addr;
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always_ff @(posedge clk_i)
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always_ff @(posedge clk_i)
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cs_rom <= cs_i && cyc_i && stb_i && (adr_i[16:8] >= 9'h100 && adr_i[16:8] < 9'h1FF);
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cs_any <= cyc_i & stb_i & cs_io_i;
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always_ff @(posedge clk_i)
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always_ff @(posedge clk_i)
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cs_reg <= cs_i && cyc_i && stb_i && (adr_i[16:8] == 9'h1FF);
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cs_config <= cyc_i & stb_i & cs_config_i && adr_i[27:20]==CFG_BUS && adr_i[19:15]==CFG_DEVICE && adr_i[14:12]==CFG_FUNC;
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always_ff @(posedge clk_i)
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always_ff @(posedge clk_i)
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cs_text <= cs_i && cyc_i && stb_i && (adr_i[16:8] < 9'h100);
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cs_rom1 <= adr_i[31:18] == tc_cbm_addr[31:18];
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always_ff @(posedge clk_i)
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always_ff @(posedge clk_i)
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cs_any <= cs_i && cyc_i && stb_i;
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cs_reg1 <= adr_i[31: 8] == tc_reg_addr[31: 8];
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always_ff @(posedge clk_i)
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cs_text1 <= adr_i[31:18] == tc_ram_addr[31:18];
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always_comb
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cs_rom <= cs_rom1 && cs_any;
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always_comb
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cs_reg <= cs_reg1 && cs_any;
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always_comb
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cs_text <= cs_text1 && cs_any;
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always_ff @(posedge clk_i)
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always_ff @(posedge clk_i)
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wrs_i <= BUSWID==64 ? {8{wr_i}} & sel_i :
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wrs_i <= (BUSWID==64) ? {8{wr_i}} & sel_i :
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adr_i[2] ? {{4{wr_i}} & sel_i,4'h0} : {4'h0,{4{wr_i}} & sel_i};
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adr_i[2] ? {{4{wr_i}} & sel_i,4'h0} : {4'h0,{4{wr_i}} & sel_i};
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always_ff @(posedge clk_i)
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always_ff @(posedge clk_i)
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rwr_i <= wr_i;
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rwr_i <= wr_i;
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always_ff @(posedge clk_i)
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always_ff @(posedge clk_i)
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rsel_i <= BUSWID==64 ? sel_i : adr_i[2] ? {sel_i,4'h0} : {4'h0,sel_i};
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rsel_i <= (BUSWID==64) ? sel_i : adr_i[2] ? {sel_i,4'h0} : {4'h0,sel_i};
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always_ff @(posedge clk_i)
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always_ff @(posedge clk_i)
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radr_i <= adr_i;
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radr_i <= adr_i;
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always_ff @(posedge clk_i)
|
always_ff @(posedge clk_i)
|
rdat_i <= BUSWID==64 ? dat_i : {2{dat_i}};
|
rdat_i <= (BUSWID==64) ? dat_i : (BUSWID==32) ? {2{dat_i}} : {4{dat_i}};
|
|
|
// Register outputs
|
// Register outputs
|
always @(posedge clk_i)
|
always_ff @(posedge clk_i)
|
if (BUSWID==64)
|
if (BUSWID==64)
|
casez({cs_rom,cs_reg,cs_text})
|
casez({cs_config,cs_rom,cs_reg,cs_text})
|
3'b1??: dat_o <= chdat_o;
|
4'b1???: dat_o <= cfg_out;
|
3'b01?: dat_o <= rego;
|
4'b01??: dat_o <= chdat_o;
|
3'b001: dat_o <= tdat_o;
|
4'b001?: dat_o <= rego;
|
|
4'b0001: dat_o <= tdat_o;
|
default: dat_o <= 'h0;
|
default: dat_o <= 'h0;
|
endcase
|
endcase
|
else if (BUSWID==32)
|
else if (BUSWID==32)
|
casez({cs_rom,cs_reg,cs_text})
|
casez({cs_config,cs_rom,cs_reg,cs_text})
|
3'b1??: dat_o <= radr_i[2] ? chdat_o[63:32] : chdat_o[31:0];
|
4'b1???: dat_o <= radr_i[2] ? cfg_out[63:32] : cfg_out[31:0];
|
3'b01?: dat_o <= radr_i[2] ? rego[63:32] : rego[31:0];
|
4'b01??: dat_o <= radr_i[2] ? chdat_o[63:32] : chdat_o[31:0];
|
3'b001: dat_o <= radr_i[2] ? tdat_o[63:32] : tdat_o[31:0];
|
4'b001?: dat_o <= radr_i[2] ? rego[63:32] : rego[31:0];
|
|
4'b0001: dat_o <= radr_i[2] ? tdat_o[63:32] : tdat_o[31:0];
|
default: dat_o <= 'd0;
|
default: dat_o <= 'd0;
|
endcase
|
endcase
|
else
|
else
|
dat_o <= 'd0;
|
dat_o <= 'd0;
|
|
|
//always @(posedge clk_i)
|
//always @(posedge clk_i)
|
// if (cs_text) begin
|
// if (cs_text) begin
|
// $display("TC WRite: %h %h", adr_i, dat_i);
|
// $display("TC WRite: %h %h", adr_i, dat_i);
|
// $stop;
|
// $stop;
|
// end
|
// end
|
|
|
// - there is a four cycle latency for reads, an ack is generated
|
// - there is a four cycle latency for reads, an ack is generated
|
// after the synchronous RAM read
|
// after the synchronous RAM read
|
// - writes can be acknowledged right away.
|
// - writes can be acknowledged right away.
|
|
|
ack_gen #(
|
ack_gen #(
|
.READ_STAGES(5),
|
.READ_STAGES(5),
|
.WRITE_STAGES(1),
|
.WRITE_STAGES(1),
|
.REGISTER_OUTPUT(1)
|
.REGISTER_OUTPUT(1)
|
)
|
)
|
uag1 (
|
uag1 (
|
|
.rst_i(rst_i),
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.ce_i(1'b1),
|
.ce_i(1'b1),
|
.i(cs_any),
|
.i((cs_any|cs_config) & ~rwr_i),
|
.we_i(cs_any & rwr_i),
|
.we_i((cs_any|cs_config) & rwr_i),
|
.o(ack_o),
|
.o(ack_o),
|
.rid_i(0),
|
.rid_i(0),
|
.wid_i(0),
|
.wid_i(0),
|
.rid_o(),
|
.rid_o(),
|
.wid_o()
|
.wid_o()
|
);
|
);
|
|
|
//--------------------------------------------------------------------
|
//--------------------------------------------------------------------
|
|
// config
|
|
//--------------------------------------------------------------------
|
|
|
|
initial begin
|
|
for (n3 = 0; n3 < 32; n3 = n3 + 1)
|
|
cfg_dat[n3] = 'd0;
|
|
end
|
|
|
|
always_ff @(posedge clk_i)
|
|
if (rst_i) begin
|
|
tc_ram_addr <= `TC_RAM_ADDR;
|
|
tc_cbm_addr <= `TC_CBM_ADDR;
|
|
tc_reg_addr <= `TC_REG_ADDR;
|
|
end
|
|
else begin
|
|
if (cs_config) begin
|
|
if (rwr_i)
|
|
case(radr_i[7:3])
|
|
5'h02:
|
|
begin
|
|
if (&rsel_i[3:0] && rdat_i[31:0]==32'hFFFFFFFF)
|
|
tc_ram_addr <= 32'hFFFFFFFF; // no memory is needed
|
|
else begin
|
|
if (rsel_i[0]) tc_ram_addr[7:0] <= rdat_i[7:0];
|
|
if (rsel_i[1]) tc_ram_addr[15:8] <= rdat_i[15:8];
|
|
if (rsel_i[2]) tc_ram_addr[23:16] <= rdat_i[23:16];
|
|
if (rsel_i[3]) tc_ram_addr[31:24] <= rdat_i[31:24];
|
|
end
|
|
if (&rsel_i[7:4] && rdat_i[31:0]==32'hFFFFFFFF)
|
|
tc_cbm_addr <= 32'hFFFFFFFF; // no memory is needed
|
|
else begin
|
|
if (rsel_i[4]) tc_cbm_addr[7:0] <= rdat_i[7:0];
|
|
if (rsel_i[5]) tc_cbm_addr[15:8] <= rdat_i[15:8];
|
|
if (rsel_i[6]) tc_cbm_addr[23:16] <= rdat_i[23:16];
|
|
if (rsel_i[7]) tc_cbm_addr[31:24] <= rdat_i[31:24];
|
|
end
|
|
end
|
|
5'h03:
|
|
begin
|
|
if (&rsel_i[3:0] && rdat_i[31:0]==32'hFFFFFFFF)
|
|
tc_reg_addr <= 32'hFFFFFFFF; // no memory is needed
|
|
else begin
|
|
if (rsel_i[0]) tc_reg_addr[7:0] <= rdat_i[7:0];
|
|
if (rsel_i[1]) tc_reg_addr[15:8] <= rdat_i[15:8];
|
|
if (rsel_i[2]) tc_reg_addr[23:16] <= rdat_i[23:16];
|
|
if (rsel_i[3]) tc_reg_addr[31:24] <= rdat_i[31:24];
|
|
end
|
|
end
|
|
default:
|
|
cfg_dat[radr_i[7:3]] <= rdat_i;
|
|
endcase
|
|
else
|
|
case(radr_i[7:3])
|
|
5'h00: cfg_out <= {32'h0,CFG_DEVICE_ID,CFG_VENDOR_ID};
|
|
5'h01: cfg_out <= {8'h00,8'h00,8'h00,8'd32,24'h0,8'h0};
|
|
5'h02: cfg_out <= {tc_cbm_addr,tc_ram_addr};
|
|
5'h03: cfg_out <= {32'hFFFFFFFF,tc_reg_addr};
|
|
5'h04: cfg_out <= 64'hFFFFFFFFFFFFFFFF;
|
|
5'h05: cfg_out <= {CFG_SUBSYSTEM_ID,CFG_SUBSYSTEM_VENDOR_ID,32'h0};
|
|
5'h06: cfg_out <= {24'h00,8'h00,CFG_ROM_ADDR};
|
|
5'h07: cfg_out <= {8'd8,8'd0,8'd0,8'd0,32'h0};
|
|
default: cfg_out <= cfg_dat[radr_i[7:3]];
|
|
endcase
|
|
end
|
|
end
|
|
|
|
|
|
//--------------------------------------------------------------------
|
//--------------------------------------------------------------------
|
//--------------------------------------------------------------------
|
`ifdef USE_CLOCK_GATE
|
`ifdef USE_CLOCK_GATE
|
BUFHCE ucb1 (.I(dot_clk_i), .CE(controller_enable), .O(vclk));
|
BUFHCE ucb1 (.I(dot_clk_i), .CE(controller_enable), .O(vclk));
|
`else
|
`else
|
assign vclk = dot_clk_i;
|
assign vclk = dot_clk_i;
|
`endif
|
`endif
|
|
|
//--------------------------------------------------------------------
|
//--------------------------------------------------------------------
|
// Video Memory
|
// Video Memory
|
//--------------------------------------------------------------------
|
//--------------------------------------------------------------------
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Address Calculation:
|
// Address Calculation:
|
// - Simple: the row times the number of cols plus the col plus the
|
// - Simple: the row times the number of cols plus the col plus the
|
// base screen address
|
// base screen address
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
reg [15:0] rowcol;
|
reg [15:0] rowcol;
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
txtAddr <= startAddress + rowcol + col;
|
txtAddr <= startAddress + rowcol + col;
|
|
|
// Register read-back memory
|
// Register read-back memory
|
// This core to be found under Memory-Cores folder
|
// This core to be found under Memory-Cores folder
|
// Allows reading back of register values by shadowing them with ram
|
// Allows reading back of register values by shadowing them with ram
|
|
|
wire [3:0] rrm_adr = radr_i[6:3];
|
wire [3:0] rrm_adr = radr_i[6:3];
|
wire [63:0] rrm_o;
|
wire [63:0] rrm_o;
|
|
|
regReadbackMem #(.WID(8)) rrm0L
|
regReadbackMem #(.WID(8)) rrm0L
|
(
|
(
|
.wclk(clk_i),
|
.wclk(clk_i),
|
.adr(rrm_adr),
|
.adr(rrm_adr),
|
.wce(cs_reg),
|
.wce(cs_reg),
|
.we(rwr_i & rsel_i[0]),
|
.we(rwr_i & rsel_i[0]),
|
.i(rdat_i[7:0]),
|
.i(rdat_i[7:0]),
|
.o(rrm_o[7:0])
|
.o(rrm_o[7:0])
|
);
|
);
|
|
|
regReadbackMem #(.WID(8)) rrm0H
|
regReadbackMem #(.WID(8)) rrm0H
|
(
|
(
|
.wclk(clk_i),
|
.wclk(clk_i),
|
.adr(rrm_adr),
|
.adr(rrm_adr),
|
.wce(cs_reg),
|
.wce(cs_reg),
|
.we(rwr_i & rsel_i[1]),
|
.we(rwr_i & rsel_i[1]),
|
.i(rdat_i[15:8]),
|
.i(rdat_i[15:8]),
|
.o(rrm_o[15:8])
|
.o(rrm_o[15:8])
|
);
|
);
|
|
|
regReadbackMem #(.WID(8)) rrm1L
|
regReadbackMem #(.WID(8)) rrm1L
|
(
|
(
|
.wclk(clk_i),
|
.wclk(clk_i),
|
.adr(rrm_adr),
|
.adr(rrm_adr),
|
.wce(cs_reg),
|
.wce(cs_reg),
|
.we(rwr_i & rsel_i[2]),
|
.we(rwr_i & rsel_i[2]),
|
.i(rdat_i[23:16]),
|
.i(rdat_i[23:16]),
|
.o(rrm_o[23:16])
|
.o(rrm_o[23:16])
|
);
|
);
|
|
|
regReadbackMem #(.WID(8)) rrm1H
|
regReadbackMem #(.WID(8)) rrm1H
|
(
|
(
|
.wclk(clk_i),
|
.wclk(clk_i),
|
.adr(rrm_adr),
|
.adr(rrm_adr),
|
.wce(cs_reg),
|
.wce(cs_reg),
|
.we(rwr_i & rsel_i[3]),
|
.we(rwr_i & rsel_i[3]),
|
.i(rdat_i[31:24]),
|
.i(rdat_i[31:24]),
|
.o(rrm_o[31:24])
|
.o(rrm_o[31:24])
|
);
|
);
|
|
|
regReadbackMem #(.WID(8)) rrm2L
|
regReadbackMem #(.WID(8)) rrm2L
|
(
|
(
|
.wclk(clk_i),
|
.wclk(clk_i),
|
.adr(rrm_adr),
|
.adr(rrm_adr),
|
.wce(cs_reg),
|
.wce(cs_reg),
|
.we(rwr_i & rsel_i[4]),
|
.we(rwr_i & rsel_i[4]),
|
.i(rdat_i[39:32]),
|
.i(rdat_i[39:32]),
|
.o(rrm_o[39:32])
|
.o(rrm_o[39:32])
|
);
|
);
|
|
|
regReadbackMem #(.WID(8)) rrm2H
|
regReadbackMem #(.WID(8)) rrm2H
|
(
|
(
|
.wclk(clk_i),
|
.wclk(clk_i),
|
.adr(rrm_adr),
|
.adr(rrm_adr),
|
.wce(cs_reg),
|
.wce(cs_reg),
|
.we(rwr_i & rsel_i[5]),
|
.we(rwr_i & rsel_i[5]),
|
.i(rdat_i[47:40]),
|
.i(rdat_i[47:40]),
|
.o(rrm_o[47:40])
|
.o(rrm_o[47:40])
|
);
|
);
|
|
|
regReadbackMem #(.WID(8)) rrm3L
|
regReadbackMem #(.WID(8)) rrm3L
|
(
|
(
|
.wclk(clk_i),
|
.wclk(clk_i),
|
.adr(rrm_adr),
|
.adr(rrm_adr),
|
.wce(cs_reg),
|
.wce(cs_reg),
|
.we(rwr_i & rsel_i[6]),
|
.we(rwr_i & rsel_i[6]),
|
.i(rdat_i[55:48]),
|
.i(rdat_i[55:48]),
|
.o(rrm_o[55:48])
|
.o(rrm_o[55:48])
|
);
|
);
|
|
|
regReadbackMem #(.WID(8)) rrm3H
|
regReadbackMem #(.WID(8)) rrm3H
|
(
|
(
|
.wclk(clk_i),
|
.wclk(clk_i),
|
.adr(rrm_adr),
|
.adr(rrm_adr),
|
.wce(cs_reg),
|
.wce(cs_reg),
|
.we(rwr_i & rsel_i[7]),
|
.we(rwr_i & rsel_i[7]),
|
.i(rdat_i[63:56]),
|
.i(rdat_i[63:56]),
|
.o(rrm_o[63:56])
|
.o(rrm_o[63:56])
|
);
|
);
|
|
|
wire [31:0] lfsr1_o;
|
wire [26:0] lfsr1_o;
|
lfsr #(32) ulfsr1(rst_i, dot_clk_i, 1'b1, 1'b0, lfsr1_o);
|
lfsr27 #(.WID(27)) ulfsr1(rst_i, dot_clk_i, 1'b1, 1'b0, lfsr1_o);
|
wire [63:0] lfsr_o = {6'h20,
|
wire [63:0] lfsr_o = {6'h10,
|
lfsr1_o[26:24],4'b0,lfsr1_o[23:21],4'b0,lfsr1_o[20:18],4'b0,
|
lfsr1_o[26:24],4'b0,lfsr1_o[23:21],4'b0,lfsr1_o[20:18],4'b0,
|
lfsr1_o[17:15],4'b0,lfsr1_o[14:12],4'b0,lfsr1_o[11:9],4'b0,
|
lfsr1_o[17:15],4'b0,lfsr1_o[14:12],4'b0,lfsr1_o[11:9],4'b0,
|
8'h00,lfsr1_o[8:0]
|
7'h00,lfsr1_o[8:0]
|
|
};
|
|
wire [63:0] lfsr_o2 = {6'h10,
|
|
// lfsr1_o[26:24],4'b0,lfsr1_o[23:21],4'b0,lfsr1_o[20:18],4'b0,
|
|
// lfsr1_o[17:15],4'b0,lfsr1_o[14:12],4'b0,lfsr1_o[11:9],4'b0,
|
|
4'b0,lfsr1_o[26:24],4'b0,lfsr1_o[23:21],lfsr1_o[20:18],4'b0,
|
|
4'b0,lfsr1_o[17:15],4'b0,lfsr1_o[14:12],lfsr1_o[11:9],4'b0,
|
|
7'h00,lfsr1_o[8:0]
|
|
};
|
|
wire [63:0] lfsr_o1 = {lfsr1_o[3:0],2'b00,
|
|
// lfsr1_o[26:24],4'b0,lfsr1_o[23:21],4'b0,lfsr1_o[20:18],4'b0,
|
|
// lfsr1_o[17:15],4'b0,lfsr1_o[14:12],4'b0,lfsr1_o[11:9],4'b0,
|
|
4'b0,lfsr1_o[26:24],4'b0,lfsr1_o[23:21],lfsr1_o[20:18],4'b0,
|
|
4'b0,lfsr1_o[17:15],lfsr1_o[14:12],4'b0,4'b0,lfsr1_o[11:9],
|
|
7'h00,lfsr1_o[8:0]
|
};
|
};
|
|
|
/* This snippit of code for performing burst accesses, under construction.
|
/* This snippit of code for performing burst accesses, under construction.
|
wire pe_cs;
|
wire pe_cs;
|
edge_det u1(.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(cs_text), .pe(pe_cs), .ne(), .ee() );
|
edge_det u1(.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(cs_text), .pe(pe_cs), .ne(), .ee() );
|
|
|
reg [14:0] ctr;
|
reg [14:0] ctr;
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
if (pe_cs) begin
|
if (pe_cs) begin
|
if (cti_i==3'b000)
|
if (cti_i==3'b000)
|
ctr <= adr_i[16:3];
|
ctr <= adr_i[16:3];
|
else
|
else
|
ctr <= adr_i[16:3] + 12'd1;
|
ctr <= adr_i[16:3] + 12'd1;
|
cnt <= 3'b000;
|
cnt <= 3'b000;
|
end
|
end
|
else if (cs_text && cnt[2:0]!=3'b100 && cti_i!=3'b000) begin
|
else if (cs_text && cnt[2:0]!=3'b100 && cti_i!=3'b000) begin
|
ctr <= ctr + 2'd1;
|
ctr <= ctr + 2'd1;
|
cnt <= cnt + 3'd1;
|
cnt <= cnt + 3'd1;
|
end
|
end
|
|
|
reg [13:0] radr;
|
reg [13:0] radr;
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
radr <= pe_cs ? adr_i[16:3] : ctr;
|
radr <= pe_cs ? adr_i[16:3] : ctr;
|
*/
|
*/
|
|
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// text screen RAM
|
// text screen RAM
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
rfTextScreenRam screen_ram1
|
rfTextScreenRam #(
|
|
.TEXT_CELL_COUNT(TEXT_CELL_COUNT)
|
|
)
|
|
screen_ram1
|
(
|
(
|
.clka_i(clk_i),
|
.clka_i(clk_i),
|
.csa_i(cs_text),
|
.csa_i(cs_text),
|
.wea_i(rwr_i),
|
.wea_i(rwr_i),
|
.sela_i(rsel_i),
|
.sela_i(rsel_i),
|
.adra_i(radr_i[15:3]),
|
.adra_i(radr_i[16:3]),
|
.data_i(rdat_i),
|
.data_i(rdat_i),
|
.data_o(tdat_o),
|
.data_o(tdat_o),
|
.clkb_i(vclk),
|
.clkb_i(vclk),
|
.csb_i(ld_shft|por),
|
.csb_i(ld_shft|por),
|
.web_i(por),
|
.web_i(por),
|
.selb_i(8'hFF),
|
.selb_i(8'hFF),
|
.adrb_i(txtAddr[12:0]),
|
.adrb_i(txtAddr[13:0]),
|
.datb_i(lfsr_o),
|
.datb_i(lfsr_o),//txtAddr[12:0] > 13'd1664 ? lfsr_o1 : lfsr_o),
|
.datb_o(screen_ram_out)
|
.datb_o(screen_ram_out)
|
);
|
);
|
|
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Character bitmap RAM
|
// Character bitmap RAM
|
// - room for 8160 8x8 characters
|
// - room for 8160 8x8 characters
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
wire [63:0] char_bmp; // character ROM output
|
wire [63:0] char_bmp; // character ROM output
|
rfTextCharRam charRam0
|
rfTextCharRam charRam0
|
(
|
(
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.cs_i(cs_rom),
|
.cs_i(cs_rom),
|
.we_i(rwr_i & ~font_locked),
|
.we_i(rwr_i & ~font_locked),
|
.sel_i(rsel_i),
|
.sel_i(rsel_i),
|
.adr_i(radr_i[15:3]),
|
.adr_i(radr_i[15:3]),
|
.dat_i(rdat_i[63:0]),
|
.dat_i(rdat_i[63:0]),
|
.dat_o(chdat_o),
|
.dat_o(chdat_o),
|
.dot_clk_i(vclk),
|
.dot_clk_i(vclk),
|
.ce_i(ld_shft),
|
.ce_i(ld_shft),
|
.fontAddress_i(fontAddress),
|
.fontAddress_i(fontAddress),
|
.char_code_i(screen_ram_out[12:0]),
|
.char_code_i(screen_ram_out[12:0]),
|
.maxScanpix_i(maxScanpix),
|
.maxScanpix_i(maxScanpix),
|
.maxscanline_i(maxScanlinePlusOne),
|
.maxscanline_i(maxScanlinePlusOne),
|
.scanline_i(rowscan[5:0]),
|
.scanline_i(rowscan[5:0]),
|
.bmp_o(char_bmp)
|
.bmp_o(char_bmp)
|
);
|
);
|
|
|
// pipeline delay - sync color with character bitmap output
|
// pipeline delay - sync color with character bitmap output
|
reg [20:0] txtBkCode1;
|
reg [20:0] txtBkCode1;
|
reg [20:0] txtFgCode1;
|
reg [20:0] txtFgCode1;
|
reg [5:0] txtZorder1;
|
reg [5:0] txtZorder1;
|
always @(posedge vclk)
|
always @(posedge vclk)
|
if (ld_shft) txtBkCode1 <= screen_ram_out[36:16];
|
if (ld_shft) txtBkCode1 <= screen_ram_out[36:16];
|
always @(posedge vclk)
|
always @(posedge vclk)
|
if (ld_shft) txtFgCode1 <= screen_ram_out[57:37];
|
if (ld_shft) txtFgCode1 <= screen_ram_out[57:37];
|
always @(posedge vclk)
|
always @(posedge vclk)
|
if (ld_shft) txtZorder1 <= screen_ram_out[63:58];
|
if (ld_shft) txtZorder1 <= screen_ram_out[63:58];
|
|
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Register read port
|
// Register read port
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
always_comb
|
always_comb
|
if (cs_reg)
|
if (cs_reg)
|
rego <= rrm_o;
|
rego <= rrm_o;
|
else
|
else
|
rego <= 64'h0000;
|
rego <= 64'h0000;
|
|
|
|
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Register write port
|
// Register write port
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
always_ff @(posedge clk_i)
|
always_ff @(posedge clk_i)
|
if (rst_i) begin
|
if (rst_i) begin
|
por <= 1'b1;
|
por <= 1'b1;
|
mcm <= 1'b0;
|
mcm <= 1'b0;
|
|
aam <= 1'b0;
|
controller_enable <= 1'b1;
|
controller_enable <= 1'b1;
|
xscroll <= 5'd0;
|
xscroll <= 5'd0;
|
yscroll <= 5'd0;
|
yscroll <= 5'd0;
|
txtTcCode <= 24'h1ff;
|
txtTcCode <= 24'h1ff;
|
bdrColor <= 32'hFFBF2020;
|
bdrColor <= 32'hFFBF2020;
|
startAddress <= 16'h0000;
|
startAddress <= 16'h0000;
|
fontAddress <= 16'h0000;
|
fontAddress <= 16'h0008;
|
font_locked <= 1'b1;
|
font_locked <= 1'b1;
|
fontAscent <= 6'd12;
|
fontAscent <= 6'd12;
|
cursorStart <= 5'd00;
|
cursorStart <= 5'd00;
|
cursorEnd <= 5'd31;
|
cursorEnd <= 5'd31;
|
cursorPos <= 16'h0003;
|
cursorPos <= 16'h0003;
|
cursorType <= 3'd4; // checker
|
cursorType <= 3'd4; // checker
|
// 104x63
|
// 104x63
|
/*
|
/*
|
windowTop <= 12'd26;
|
windowTop <= 12'd26;
|
windowLeft <= 12'd260;
|
windowLeft <= 12'd260;
|
pixelWidth <= 4'd0;
|
pixelWidth <= 4'd0;
|
pixelHeight <= 4'd1; // 525 pixels (408 with border)
|
pixelHeight <= 4'd1; // 525 pixels (408 with border)
|
*/
|
*/
|
// 52x31
|
// 52x31
|
/*
|
/*
|
// 84x47
|
// 84x47
|
windowTop <= 12'd16;
|
windowTop <= 12'd16;
|
windowLeft <= 12'd90;
|
windowLeft <= 12'd90;
|
pixelWidth <= 4'd1; // 681 pixels
|
pixelWidth <= 4'd1; // 681 pixels
|
pixelHeight <= 4'd1; // 384 pixels
|
pixelHeight <= 4'd1; // 384 pixels
|
*/
|
*/
|
// 64x32
|
// 64x32
|
if (num==4'd1) begin
|
if (num==4'd1) begin
|
windowTop <= 12'd4058;//12'd16;
|
windowTop <= 12'd4058;//12'd16;
|
windowLeft <= 12'd3956;//12'd86;
|
windowLeft <= 12'd3918;//12'd3956;//12'd86;
|
pixelWidth <= 4'd0; // 800 pixels
|
pixelWidth <= 4'd0; // 800 pixels
|
pixelHeight <= 4'd0; // 600 pixels
|
pixelHeight <= 4'd0; // 600 pixels
|
numCols <= COLS;
|
numCols <= COLS;
|
numRows <= ROWS;
|
numRows <= ROWS;
|
maxRowScan <= 6'd17;
|
maxRowScan <= 6'd17;
|
maxScanpix <= 6'd11;
|
maxScanpix <= 6'd11;
|
rBlink <= 3'b111; // 01 = non display
|
rBlink <= 3'b111; // 01 = non display
|
charOutDelay <= 8'd7;
|
charOutDelay <= 8'd5;
|
end
|
end
|
else if (num==4'd2) begin
|
else if (num==4'd2) begin
|
windowTop <= 12'd4032;//12'd16;
|
windowTop <= 12'd4032;//12'd16;
|
windowLeft <= 12'd3720;//12'd86;
|
windowLeft <= 12'd3720;//12'd86;
|
pixelWidth <= 4'd0; // 800 pixels
|
pixelWidth <= 4'd0; // 800 pixels
|
pixelHeight <= 4'd0; // 600 pixels
|
pixelHeight <= 4'd0; // 600 pixels
|
numCols <= 40;
|
numCols <= 40;
|
numRows <= 25;
|
numRows <= 25;
|
maxRowScan <= 5'd7;
|
maxRowScan <= 5'd7;
|
maxScanpix <= 6'd7;
|
maxScanpix <= 6'd7;
|
rBlink <= 3'b111; // 01 = non display
|
rBlink <= 3'b111; // 01 = non display
|
charOutDelay <= 8'd6;
|
charOutDelay <= 8'd6;
|
end
|
end
|
end
|
end
|
else begin
|
else begin
|
|
|
if (bcnt > 6'd10)
|
if (bcnt > 6'd10)
|
por <= 1'b0;
|
por <= 1'b0;
|
|
|
if (cs_reg & rwr_i) begin // register write ?
|
if (cs_reg & rwr_i) begin // register write ?
|
$display("TC Write: r%d=%h", rrm_adr, rdat_i);
|
$display("TC Write: r%d=%h", rrm_adr, rdat_i);
|
case(rrm_adr)
|
case(rrm_adr)
|
4'd0: begin
|
4'd0: begin
|
if (rsel_i[0]) numCols <= rdat_i[7:0];
|
if (rsel_i[0]) numCols <= rdat_i[7:0];
|
if (rsel_i[1]) numRows <= rdat_i[15:8];
|
if (rsel_i[1]) numRows <= rdat_i[15:8];
|
if (rsel_i[2]) charOutDelay <= rdat_i[23:16];
|
if (rsel_i[2]) charOutDelay <= rdat_i[23:16];
|
if (rsel_i[4]) windowLeft[7:0] <= rdat_i[39:32];
|
if (rsel_i[4]) windowLeft[7:0] <= rdat_i[39:32];
|
if (rsel_i[5]) windowLeft[11:8] <= rdat_i[43:40];
|
if (rsel_i[5]) windowLeft[11:8] <= rdat_i[43:40];
|
if (rsel_i[6]) windowTop[7:0] <= rdat_i[55:48];
|
if (rsel_i[6]) windowTop[7:0] <= rdat_i[55:48];
|
if (rsel_i[7]) windowTop[11:8] <= rdat_i[59:56];
|
if (rsel_i[7]) windowTop[11:8] <= rdat_i[59:56];
|
end
|
end
|
4'd1:
|
4'd1:
|
begin
|
begin
|
if (rsel_i[0]) maxRowScan <= rdat_i[4:0];
|
if (rsel_i[0]) maxRowScan <= rdat_i[4:0];
|
if (rsel_i[1]) begin
|
if (rsel_i[1]) begin
|
pixelHeight <= rdat_i[15:12];
|
pixelHeight <= rdat_i[15:12];
|
pixelWidth <= rdat_i[11:8]; // horizontal pixel width
|
pixelWidth <= rdat_i[11:8]; // horizontal pixel width
|
end
|
end
|
if (rsel_i[2]) maxScanpix <= rdat_i[20:16];
|
if (rsel_i[2]) maxScanpix <= rdat_i[20:16];
|
if (rsel_i[3]) por <= rdat_i[24];
|
if (rsel_i[3]) por <= rdat_i[24];
|
if (rsel_i[4]) controller_enable <= rdat_i[32];
|
if (rsel_i[4]) controller_enable <= rdat_i[32];
|
if (rsel_i[5]) mcm <= rdat_i[40];
|
if (rsel_i[5])
|
|
begin
|
|
mcm <= rdat_i[40];
|
|
aam <= rdat_i[41];
|
|
end
|
if (rsel_i[6]) yscroll <= rdat_i[52:48];
|
if (rsel_i[6]) yscroll <= rdat_i[52:48];
|
if (rsel_i[7]) xscroll <= rdat_i[60:56];
|
if (rsel_i[7]) xscroll <= rdat_i[60:56];
|
end
|
end
|
4'd2: // Color Control
|
4'd2: // Color Control
|
begin
|
begin
|
if (rsel_i[0]) txtTcCode[7:0] <= rdat_i[7:0];
|
if (rsel_i[0]) txtTcCode[7:0] <= rdat_i[7:0];
|
if (rsel_i[1]) txtTcCode[15:8] <= rdat_i[15:8];
|
if (rsel_i[1]) txtTcCode[15:8] <= rdat_i[15:8];
|
if (rsel_i[2]) txtTcCode[23:16] <= rdat_i[23:16];
|
if (rsel_i[2]) txtTcCode[23:16] <= rdat_i[23:16];
|
if (rsel_i[3]) txtTcCode[30:24] <= rdat_i[30:24];
|
if (rsel_i[3]) txtTcCode[30:24] <= rdat_i[30:24];
|
if (rsel_i[4]) bdrColor[7:0] <= dat_i[39:32];
|
if (rsel_i[4]) bdrColor[7:0] <= rdat_i[39:32];
|
if (rsel_i[5]) bdrColor[15:8] <= dat_i[47:40];
|
if (rsel_i[5]) bdrColor[15:8] <= rdat_i[47:40];
|
if (rsel_i[6]) bdrColor[23:16] <= dat_i[55:48];
|
if (rsel_i[6]) bdrColor[23:16] <= rdat_i[55:48];
|
if (rsel_i[7]) bdrColor[31:24] <= dat_i[63:56];
|
if (rsel_i[7]) bdrColor[31:24] <= rdat_i[63:56];
|
end
|
end
|
4'd3: // Color Control 2
|
4'd3: // Color Control 2
|
begin
|
begin
|
if (rsel_i[0]) tileColor1[7:0] <= rdat_i[7:0];
|
if (rsel_i[0]) tileColor1[7:0] <= rdat_i[7:0];
|
if (rsel_i[1]) tileColor1[15:8] <= rdat_i[15:8];
|
if (rsel_i[1]) tileColor1[15:8] <= rdat_i[15:8];
|
if (rsel_i[2]) tileColor1[23:16] <= rdat_i[23:16];
|
if (rsel_i[2]) tileColor1[23:16] <= rdat_i[23:16];
|
if (rsel_i[3]) tileColor1[30:24] <= rdat_i[30:24];
|
if (rsel_i[3]) tileColor1[30:24] <= rdat_i[30:24];
|
if (rsel_i[4]) tileColor2[7:0] <= rdat_i[39:32];
|
if (rsel_i[4]) tileColor2[7:0] <= rdat_i[39:32];
|
if (rsel_i[5]) tileColor2[15:8] <= rdat_i[47:40];
|
if (rsel_i[5]) tileColor2[15:8] <= rdat_i[47:40];
|
if (rsel_i[6]) tileColor2[23:16] <= rdat_i[55:48];
|
if (rsel_i[6]) tileColor2[23:16] <= rdat_i[55:48];
|
if (rsel_i[7]) tileColor2[30:24] <= rdat_i[62:56];
|
if (rsel_i[7]) tileColor2[30:24] <= rdat_i[62:56];
|
end
|
end
|
4'd4: // Cursor Control
|
4'd4: // Cursor Control
|
begin
|
begin
|
if (rsel_i[0]) begin
|
if (rsel_i[0]) begin
|
cursorEnd <= rdat_i[4:0]; // scan line sursor starts on
|
cursorEnd <= rdat_i[4:0]; // scan line sursor starts on
|
rBlink <= rdat_i[7:5];
|
rBlink <= rdat_i[7:5];
|
end
|
end
|
if (rsel_i[1]) begin
|
if (rsel_i[1]) begin
|
cursorStart <= rdat_i[12:8]; // scan line cursor ends on
|
cursorStart <= rdat_i[12:8]; // scan line cursor ends on
|
cursorType <= rdat_i[15:13];
|
cursorType <= rdat_i[15:13];
|
end
|
end
|
if (rsel_i[4]) cursorPos[7:0] <= rdat_i[39:32];
|
if (rsel_i[4]) cursorPos[7:0] <= rdat_i[39:32];
|
if (rsel_i[5]) cursorPos[15:8] <= rdat_i[47:40];
|
if (rsel_i[5]) cursorPos[15:8] <= rdat_i[47:40];
|
end
|
end
|
4'd5: // Page flipping / scrolling
|
4'd5: // Page flipping / scrolling
|
begin
|
begin
|
if (rsel_i[0]) startAddress[7:0] <= rdat_i[7:0];
|
if (rsel_i[0]) startAddress[7:0] <= rdat_i[7:0];
|
if (rsel_i[1]) startAddress[15:8] <= rdat_i[15:8];
|
if (rsel_i[1]) startAddress[15:8] <= rdat_i[15:8];
|
end
|
end
|
4'd6: //
|
4'd6: //
|
begin
|
begin
|
if (rsel_i[0]) fontAddress[7:0] <= rdat_i[7:0];
|
if (rsel_i[0]) fontAddress[7:0] <= rdat_i[7:0];
|
if (rsel_i[1]) fontAddress[15:8] <= rdat_i[15:8];
|
if (rsel_i[1]) fontAddress[15:8] <= rdat_i[15:8];
|
if (rsel_i[3]) fontAscent[5:0] <= rdat_i[5:0];
|
if (rsel_i[3]) fontAscent[5:0] <= rdat_i[5:0];
|
if (&rsel_i[7:4]) begin
|
if (&rsel_i[7:4]) begin
|
if (rdat_i[63:32]=="LOCK")
|
if (rdat_i[63:32]=="LOCK")
|
font_locked <= 1'b1;
|
font_locked <= 1'b1;
|
else if (rdat_i[63:32]=="UNLK")
|
else if (rdat_i[63:32]=="UNLK")
|
font_locked <= 1'b0;
|
font_locked <= 1'b0;
|
end
|
end
|
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
|
//--------------------------------------------------------------------
|
//--------------------------------------------------------------------
|
// Cursor image is computed based on the font size, so the available
|
// Cursor image is computed based on the font size, so the available
|
// hardware cursors are really simple. More sophisticated hardware
|
// hardware cursors are really simple. More sophisticated hardware
|
// cursors can be had via the sprite controller.
|
// cursors can be had via the sprite controller.
|
//--------------------------------------------------------------------
|
//--------------------------------------------------------------------
|
|
|
reg [31:0] curout;
|
reg [31:0] curout;
|
integer n2;
|
wire [31:0] curout1;
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
if (ld_shft) begin
|
if (ld_shft) begin
|
curout = 'd0;
|
curout = 'd0;
|
case(cursorType)
|
case(cursorType)
|
// No cursor
|
// No cursor
|
3'd0: ;
|
3'd0: ;
|
// "Box" cursor
|
// "Box" cursor
|
3'd1:
|
3'd1:
|
begin
|
begin
|
case(rowscan)
|
case(rowscan)
|
maxRowScan,5'd0: curout = 32'hFFFFFFFF;
|
maxRowScan,5'd0: curout = 32'hFFFFFFFF;
|
/*
|
/*
|
maxRowScan-1:
|
maxRowScan-1:
|
if (rowscan==maxRowScan-1) begin
|
if (rowscan==maxRowScan-1) begin
|
curout[maxScanpix[5:1]] = 1'b1;
|
curout[maxScanpix[5:1]] = 1'b1;
|
curout[maxScanpix[5:1]+1] = 1'b1;
|
curout[maxScanpix[5:1]+1] = 1'b1;
|
end
|
end
|
*/
|
*/
|
default:
|
default:
|
begin
|
begin
|
curout[maxScanpix] = 1'b1;
|
curout[maxScanpix] = 1'b1;
|
curout[0] = 1'b1;
|
curout[0] = 1'b1;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
// Vertical Line cursor
|
// Vertical Line cursor
|
3'd2: curout[maxScanpix] = 1'b1;
|
3'd2: curout[maxScanpix] = 1'b1;
|
// Underline cursor
|
// Underline cursor
|
3'd3:
|
3'd3:
|
if (rowscan==fontAscent)
|
if (rowscan==fontAscent)
|
curout = 32'hFFFFFFFF;
|
curout = 32'hFFFFFFFF;
|
// Checker cursor
|
// Checker cursor
|
3'd4: curout = rowscan[1] ? 32'h33333333 : 32'hCCCCCCCC;
|
3'd4: curout = rowscan[1] ? 32'h33333333 : 32'hCCCCCCCC;
|
// Solid cursor
|
// Solid cursor
|
3'd7: curout = 32'hFFFFFFFF;
|
3'd7: curout = 32'hFFFFFFFF;
|
default: curout = 32'hFFFFFFFF;
|
default: curout = 32'hFFFFFFFF;
|
endcase
|
endcase
|
end
|
end
|
|
|
|
ft_delay
|
|
#(
|
|
.WID(32),
|
|
.DEP(3)
|
|
)
|
|
uftd1
|
|
(
|
|
.clk(vclk),
|
|
.ce(ld_shft),
|
|
.i(curout),
|
|
.o(curout1)
|
|
);
|
|
|
//-------------------------------------------------------------
|
//-------------------------------------------------------------
|
// Video Stuff
|
// Video Stuff
|
//-------------------------------------------------------------
|
//-------------------------------------------------------------
|
|
|
wire pe_hsync;
|
wire pe_hsync;
|
wire pe_vsync;
|
wire pe_vsync;
|
edge_det edh1
|
edge_det edh1
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
.clk(vclk),
|
.clk(vclk),
|
.ce(1'b1),
|
.ce(1'b1),
|
.i(hsync_i),
|
.i(hsync_i),
|
.pe(pe_hsync),
|
.pe(pe_hsync),
|
.ne(),
|
.ne(),
|
.ee()
|
.ee()
|
);
|
);
|
|
|
edge_det edv1
|
edge_det edv1
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
.clk(vclk),
|
.clk(vclk),
|
.ce(1'b1),
|
.ce(1'b1),
|
.i(vsync_i),
|
.i(vsync_i),
|
.pe(pe_vsync),
|
.pe(pe_vsync),
|
.ne(),
|
.ne(),
|
.ee()
|
.ee()
|
);
|
);
|
|
|
// We generally don't care about the exact reset point, unless debugging in
|
// We generally don't care about the exact reset point, unless debugging in
|
// simulation. The counters will eventually cycle to a proper state. A little
|
// simulation. The counters will eventually cycle to a proper state. A little
|
// bit of logic / routing can be avoided by omitting the reset.
|
// bit of logic / routing can be avoided by omitting the reset.
|
`ifdef SIM
|
`ifdef SIM
|
wire sym_rst = rst_i;
|
wire sym_rst = rst_i;
|
`else
|
`else
|
wire sym_rst = 1'b0;
|
wire sym_rst = 1'b0;
|
`endif
|
`endif
|
|
|
// Raw scanline counter
|
// Raw scanline counter
|
vid_counter #(12) u_vctr (.rst(sym_rst), .clk(vclk), .ce(pe_hsync), .ld(pe_vsync), .d(windowTop), .q(scanline), .tc());
|
vid_counter #(12) u_vctr (.rst(sym_rst), .clk(vclk), .ce(pe_hsync), .ld(pe_vsync), .d(windowTop), .q(scanline), .tc());
|
vid_counter #(12) u_hctr (.rst(sym_rst), .clk(vclk), .ce(1'b1), .ld(pe_hsync), .d(windowLeft), .q(hctr), .tc());
|
vid_counter #(12) u_hctr (.rst(sym_rst), .clk(vclk), .ce(1'b1), .ld(pe_hsync), .d(windowLeft), .q(hctr), .tc());
|
|
|
// Vertical pixel height counter, synchronized to scanline #0
|
// Vertical pixel height counter, synchronized to scanline #0
|
reg [3:0] vpx;
|
reg [3:0] vpx;
|
wire nvp = vpx==pixelHeight;
|
wire nvp = vpx==pixelHeight;
|
always @(posedge vclk)
|
always @(posedge vclk)
|
if (sym_rst)
|
if (sym_rst)
|
vpx <= 4'b0;
|
vpx <= 4'b0;
|
else begin
|
else begin
|
if (pe_hsync) begin
|
if (pe_hsync) begin
|
if (scanline==12'd0)
|
if (scanline==12'd0)
|
vpx <= 4'b0;
|
vpx <= 4'b0;
|
else if (nvp)
|
else if (nvp)
|
vpx <= 4'd0;
|
vpx <= 4'd0;
|
else
|
else
|
vpx <= vpx + 4'd1;
|
vpx <= vpx + 4'd1;
|
end
|
end
|
end
|
end
|
|
|
reg [3:0] hpx;
|
reg [3:0] hpx;
|
assign nhp = hpx==pixelWidth;
|
assign nhp = hpx==pixelWidth;
|
always @(posedge vclk)
|
always @(posedge vclk)
|
if (sym_rst)
|
if (sym_rst)
|
hpx <= 4'b0;
|
hpx <= 4'b0;
|
else begin
|
else begin
|
if (hctr==12'd0)
|
if (hctr==12'd0)
|
hpx <= 4'b0;
|
hpx <= 4'b0;
|
else if (nhp)
|
else if (nhp)
|
hpx <= 4'd0;
|
hpx <= 4'd0;
|
else
|
else
|
hpx <= hpx + 4'd1;
|
hpx <= hpx + 4'd1;
|
end
|
end
|
|
|
// The scanline row within a character bitmap
|
// The scanline row within a character bitmap
|
always @(posedge vclk)
|
always @(posedge vclk)
|
if (sym_rst)
|
if (sym_rst)
|
rowscan <= 5'd0;
|
rowscan <= 5'd0;
|
else begin
|
else begin
|
if (pe_hsync & nvp) begin
|
if (pe_hsync & nvp) begin
|
if (scanline==12'd0)
|
if (scanline==12'd0)
|
rowscan <= yscroll;
|
rowscan <= yscroll;
|
else if (rowscan==maxRowScan)
|
else if (rowscan==maxRowScan)
|
rowscan <= 5'd0;
|
rowscan <= 5'd0;
|
else
|
else
|
rowscan <= rowscan + 5'd1;
|
rowscan <= rowscan + 5'd1;
|
end
|
end
|
end
|
end
|
|
|
assign nxt_col = colscan==maxScanpix;
|
assign nxt_col = colscan==maxScanpix;
|
always @(posedge vclk)
|
always @(posedge vclk)
|
if (sym_rst)
|
if (sym_rst)
|
colscan <= 5'd0;
|
colscan <= 5'd0;
|
else begin
|
else begin
|
if (nhp) begin
|
if (nhp) begin
|
if (hctr==12'd0)
|
if (hctr==12'd0)
|
colscan <= xscroll;
|
colscan <= xscroll;
|
else if (nxt_col)
|
else if (nxt_col)
|
colscan <= 5'd0;
|
colscan <= 5'd0;
|
else
|
else
|
colscan <= colscan + 5'd1;
|
colscan <= colscan + 5'd1;
|
end
|
end
|
end
|
end
|
|
|
// The screen row
|
// The screen row
|
always @(posedge vclk)
|
always @(posedge vclk)
|
if (sym_rst)
|
if (sym_rst)
|
row <= 8'd0;
|
row <= 8'd0;
|
else begin
|
else begin
|
if (pe_hsync & nvp) begin
|
if (pe_hsync & nvp) begin
|
if (scanline==12'd0)
|
if (scanline==12'd0)
|
row <= 8'd0;
|
row <= 8'd0;
|
else if (rowscan==maxRowScan)
|
else if (rowscan==maxRowScan)
|
row <= row + 8'd1;
|
row <= row + 8'd1;
|
end
|
end
|
end
|
end
|
|
|
// The screen column
|
// The screen column
|
always @(posedge vclk)
|
always @(posedge vclk)
|
if (sym_rst)
|
if (sym_rst)
|
col <= 8'd0;
|
col <= 8'd0;
|
else begin
|
else begin
|
if (hctr==12'd0)
|
if (hctr==12'd0)
|
col <= 8'd0;
|
col <= 8'd0;
|
else if (nhp) begin
|
else if (nhp) begin
|
if (nxt_col)
|
if (nxt_col)
|
col <= col + 8'd1;
|
col <= col + 8'd1;
|
end
|
end
|
end
|
end
|
|
|
// More useful, the offset of the start of the text display on a line.
|
// More useful, the offset of the start of the text display on a line.
|
always @(posedge vclk)
|
always @(posedge vclk)
|
if (sym_rst)
|
if (sym_rst)
|
rowcol <= 16'd0;
|
rowcol <= 16'd0;
|
else begin
|
else begin
|
if (pe_hsync & nvp) begin
|
if (pe_hsync & nvp) begin
|
if (scanline==12'd0)
|
if (scanline==12'd0)
|
rowcol <= 8'd0;
|
rowcol <= 8'd0;
|
else if (rowscan==maxRowScan)
|
else if (rowscan==maxRowScan)
|
rowcol <= rowcol + numCols;
|
rowcol <= rowcol + numCols;
|
end
|
end
|
end
|
end
|
|
|
// Takes 3 clock for scanline to become stable, but should be stable before any
|
// Takes 3 clock for scanline to become stable, but should be stable before any
|
// chars are displayed.
|
// chars are displayed.
|
reg [13:0] rxmslp1;
|
reg [13:0] rxmslp1;
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
maxScanlinePlusOne <= maxRowScan + 4'd1;
|
maxScanlinePlusOne <= maxRowScan + 4'd1;
|
|
|
|
|
// Blink counter
|
// Blink counter
|
//
|
//
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
if (sym_rst)
|
if (sym_rst)
|
bcnt <= 6'd0;
|
bcnt <= 6'd0;
|
else begin
|
else begin
|
if (pe_vsync)
|
if (pe_vsync)
|
bcnt <= bcnt + 6'd1;
|
bcnt <= bcnt + 6'd1;
|
end
|
end
|
|
|
reg blink_en;
|
reg blink_en;
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
blink_en <= (cursorPos+3==txtAddr);// && (rowscan[4:0] >= cursorStart) && (rowscan[4:0] <= cursorEnd);
|
blink_en <= (cursorPos+charOutDelay-2'd1==txtAddr);// && (rowscan[4:0] >= cursorStart) && (rowscan[4:0] <= cursorEnd);
|
|
|
VT151 ub2
|
VT151 ub2
|
(
|
(
|
.e_n(!blink_en),
|
.e_n(!blink_en),
|
.s(rBlink),
|
.s(rBlink),
|
.i0(1'b1), .i1(1'b0), .i2(bcnt[4]), .i3(bcnt[5]),
|
.i0(1'b1), .i1(1'b0), .i2(bcnt[4]), .i3(bcnt[5]),
|
.i4(1'b1), .i5(1'b0), .i6(bcnt[4]), .i7(bcnt[5]),
|
.i4(1'b1), .i5(1'b0), .i6(bcnt[4]), .i7(bcnt[5]),
|
.z(blink),
|
.z(blink),
|
.z_n()
|
.z_n()
|
);
|
);
|
|
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
if (ld_shft)
|
if (ld_shft)
|
bkColor40 <= {txtZorder1[5:2],txtBkCode1[20:14],5'b0,txtBkCode1[13:7],5'b0,txtBkCode1[6:0],5'b0};
|
bkColor40 <= {txtZorder1[5:2],txtBkCode1[20:14],5'b0,txtBkCode1[13:7],5'b0,txtBkCode1[6:0],5'b0};
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
if (ld_shft)
|
if (ld_shft)
|
bkColor40d <= bkColor40;
|
bkColor40d <= bkColor40;
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
if (nhp)
|
if (ld_shft)
|
bkColor40d2 <= bkColor40d;
|
bkColor40d2 <= bkColor40d;
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
|
if (nhp)
|
|
bkColor40d3 <= bkColor40d2;
|
|
always_ff @(posedge vclk)
|
if (ld_shft)
|
if (ld_shft)
|
fgColor40 <= {txtZorder1[5:2],txtFgCode1[20:14],5'b0,txtFgCode1[13:7],5'b0,txtFgCode1[6:0],5'b0};
|
fgColor40 <= {txtZorder1[5:2],txtFgCode1[20:14],5'b0,txtFgCode1[13:7],5'b0,txtFgCode1[6:0],5'b0};
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
if (ld_shft)
|
if (ld_shft)
|
fgColor40d <= fgColor40;
|
fgColor40d <= fgColor40;
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
if (nhp)
|
if (ld_shft)
|
fgColor40d2 <= fgColor40d;
|
fgColor40d2 <= fgColor40d;
|
|
always_ff @(posedge vclk)
|
|
if (nhp)
|
|
fgColor40d3 <= fgColor40d2;
|
|
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
if (ld_shft)
|
if (ld_shft)
|
bgt <= txtBkCode1=={txtTcCode[26:20],txtTcCode[17:11],txtTcCode[8:2]};
|
bgt <= txtBkCode1=={txtTcCode[26:20],txtTcCode[17:11],txtTcCode[8:2]};
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
if (ld_shft)
|
if (ld_shft)
|
bgtd <= bgt;
|
bgtd <= bgt;
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
if (nhp)
|
if (nhp)
|
bgtd2 <= bgtd;
|
bgtd2 <= bgtd;
|
|
|
// Convert character bitmap to pixels
|
// Convert character bitmap to pixels
|
reg [63:0] charout1;
|
reg [63:0] charout1;
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
charout1 <= blink ? (char_bmp ^ curout) : char_bmp;
|
charout1 <= blink ? (char_bmp ^ curout1) : char_bmp;
|
|
|
// Convert parallel to serial
|
// Convert parallel to serial
|
rfTextShiftRegister ups1
|
rfTextShiftRegister ups1
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
.clk(vclk),
|
.clk(vclk),
|
.mcm(mcm),
|
.mcm(mcm),
|
|
// .aam(aam),
|
.ce(nhp),
|
.ce(nhp),
|
.ld(ld_shft),
|
.ld(ld_shft),
|
.a(maxScanpix[5:0]),
|
.a(maxScanpix[5:0]),
|
.qin(2'b0),
|
.qin(2'b0),
|
.d(charout1),
|
.d(charout1),
|
.qh(pix)
|
.qh(pix)
|
);
|
);
|
|
|
// Pipelining Effect:
|
// Pipelining Effect:
|
// - character output is delayed by 2 or 3 character times relative to the video counters
|
// - character output is delayed by 2 or 3 character times relative to the video counters
|
// depending on the resolution selected
|
// depending on the resolution selected
|
// - this means we must adapt the blanking signal by shifting the blanking window
|
// - this means we must adapt the blanking signal by shifting the blanking window
|
// two or three character times.
|
// two or three character times.
|
wire bpix = hctr[2] ^ rowscan[4];// ^ blink;
|
wire bpix = hctr[2] ^ rowscan[4];// ^ blink;
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
if (nhp)
|
if (nhp)
|
iblank <= (row >= numRows) || (col >= numCols + charOutDelay) || (col < charOutDelay);
|
iblank <= (row >= numRows) || (col >= numCols + charOutDelay) || (col < charOutDelay);
|
|
|
|
`ifdef SUPPORT_AAM
|
|
function [11:0] fnBlendComponent;
|
|
input [11:0] c1;
|
|
input [11:0] c2;
|
|
input [1:0] pix;
|
|
case(pix)
|
|
2'b00: fnBlendComponent = c2;
|
|
2'b01: fnBlendComponent = ((c1 * 4'd5) + (c2 * 4'd11)) >> 4;
|
|
2'b10: fnBlendComponent = ((c1 * 4'd11) + (c2 * 4'd5)) >> 4;
|
|
2'b11: fnBlendComponent = c1;
|
|
endcase
|
|
endfunction
|
|
|
|
function [39:0] fnBlend;
|
|
input [39:0] c1;
|
|
input [39:0] c2;
|
|
input [1:0] pix;
|
|
fnBlend = {
|
|
|pix ? c1[39:36] : c2[39:36],
|
|
fnBlendComponent(c1[35:24],c2[35:24]),
|
|
fnBlendComponent(c1[23:12],c2[23:12]),
|
|
fnBlendComponent(c1[11: 0],c2[11: 0])
|
|
};
|
|
endfunction
|
|
`endif
|
|
|
// Choose between input RGB and controller generated RGB
|
// Choose between input RGB and controller generated RGB
|
// Select between foreground and background colours.
|
// Select between foreground and background colours.
|
// Note the ungated dot clock must be used here, or output from other
|
// Note the ungated dot clock must be used here, or output from other
|
// controllers would not be visible if the clock were gated off.
|
// controllers would not be visible if the clock were gated off.
|
always_ff @(posedge dot_clk_i)
|
always_ff @(posedge dot_clk_i)
|
casez({controller_enable&xonoff_i,blank_i,iblank,border_i,bpix,mcm,pix})
|
casez({controller_enable&xonoff_i,blank_i,iblank,border_i,bpix,mcm,aam,pix})
|
8'b01??????: zrgb_o <= 40'h00000000;
|
9'b01???????: zrgb_o <= 40'h00000000;
|
8'b11??????: zrgb_o <= 40'h00000000;
|
9'b11???????: zrgb_o <= 40'h00000000;
|
8'b1001????: zrgb_o <= {bdrColor[30:27],bdrColor[26:18],3'b0,bdrColor[17:9],3'b0,bdrColor[8:0],3'b0};
|
9'b1001?????: zrgb_o <= {bdrColor[30:27],bdrColor[26:18],3'b0,bdrColor[17:9],3'b0,bdrColor[8:0],3'b0};
|
8'b1000?00?: zrgb_o <= (zrgb_i[39:36] > bkColor40d2[39:36]) ? zrgb_i : bkColor40d2;
|
`ifdef SUPPORT_AAM
|
8'b1000?01?: zrgb_o <= fgColor40d2; // ToDo: compare z-order
|
9'b1000?01??: zrgb_o <= fnBlend(fgColor40d3,zrgb_i[39:36] > bkColor40d3[39:36]) ? zrgb_i : bkColor40d3, pix);
|
8'b1000?100: zrgb_o <= (zrgb_i[39:36] > bkColor40d2[39:36]) ? zrgb_i : bkColor40d2;
|
`endif
|
8'b1000?101: zrgb_o <= fgColor40d2;
|
9'b1000?000?: zrgb_o <= (zrgb_i[39:36] > bkColor40d3[39:36]) ? zrgb_i : bkColor40d3;
|
8'b1000?110: zrgb_o <= {tileColor1[30:27],tileColor1[26:18],3'b0,tileColor1[17:9],3'b0,tileColor1[8:0],3'b0};
|
9'b1000?001?: zrgb_o <= fgColor40d3; // ToDo: compare z-order
|
8'b1000?111: zrgb_o <= {tileColor2[30:27],tileColor2[26:18],3'b0,tileColor2[17:9],3'b0,tileColor2[8:0],3'b0};
|
9'b1000?1000: zrgb_o <= (zrgb_i[39:36] > bkColor40d3[39:36]) ? zrgb_i : bkColor40d3;
|
|
9'b1000?1001: zrgb_o <= fgColor40d3;
|
|
9'b1000?1010: zrgb_o <= {tileColor1[30:27],tileColor1[26:18],3'b0,tileColor1[17:9],3'b0,tileColor1[8:0],3'b0};
|
|
9'b1000?1011: zrgb_o <= {tileColor2[30:27],tileColor2[26:18],3'b0,tileColor2[17:9],3'b0,tileColor2[8:0],3'b0};
|
// 6'b1010?0: zrgb_o <= bgtd ? zrgb_i : bkColor32d;
|
// 6'b1010?0: zrgb_o <= bgtd ? zrgb_i : bkColor32d;
|
default: zrgb_o <= zrgb_i;
|
default: zrgb_o <= zrgb_i;
|
endcase
|
endcase
|
|
|
endmodule
|
endmodule
|
|
|
|
|