-----------------------------------------------------------------
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-----------------------------------------------------------------
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-- --
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-- --
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-----------------------------------------------------------------
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-----------------------------------------------------------------
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-- --
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-- --
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-- Copyright (C) 2017 Stefano Tonello --
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-- Copyright (C) 2017 Stefano Tonello --
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-- --
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-- --
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-- This source file may be used and distributed without --
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-- This source file may be used and distributed without --
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-- restriction provided that this copyright statement is not --
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-- restriction provided that this copyright statement is not --
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-- removed from the file and that any derivative work contains --
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-- removed from the file and that any derivative work contains --
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-- the original copyright notice and the associated disclaimer.--
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-- the original copyright notice and the associated disclaimer.--
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-- --
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-- --
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY --
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY --
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED --
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED --
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR --
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR --
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, --
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, --
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR --
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR --
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT --
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT --
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --
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-- POSSIBILITY OF SUCH DAMAGE. --
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-- POSSIBILITY OF SUCH DAMAGE. --
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-- --
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-- --
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-----------------------------------------------------------------
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-----------------------------------------------------------------
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|
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---------------------------------------------------------------
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---------------------------------------------------------------
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-- RV01 CPU module
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-- RV01 CPU module
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---------------------------------------------------------------
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---------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use STD.textio.all;
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use STD.textio.all;
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|
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library work;
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library work;
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use work.RV01_CONSTS_PKG.all;
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use work.RV01_CONSTS_PKG.all;
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use work.RV01_TYPES_PKG.all;
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use work.RV01_TYPES_PKG.all;
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use WORK.RV01_FUNCS_PKG.all;
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use WORK.RV01_FUNCS_PKG.all;
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use WORK.RV01_ARITH_PKG.all;
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use WORK.RV01_ARITH_PKG.all;
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use work.RV01_IDEC_PKG.all;
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use work.RV01_IDEC_PKG.all;
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use WORK.RV01_OP_PKG.all;
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use WORK.RV01_OP_PKG.all;
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use WORK.RV01_CSR_PKG.all;
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use WORK.RV01_CSR_PKG.all;
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|
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entity RV01_CPU_2W is
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entity RV01_CPU_2W is
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generic(
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generic(
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-- synthesis translate_off
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-- synthesis translate_off
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ST_FILENAME : string := "NONE";
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ST_FILENAME : string := "NONE";
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WB_FILENAME : string := "NONE";
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WB_FILENAME : string := "NONE";
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-- synthesis translate_on
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-- synthesis translate_on
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IMEM_SIZE : natural := 1024*32; -- 128Kb
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IMEM_SIZE : natural := 1024*32; -- 128Kb
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DMEM_SIZE : natural := 1024*16; -- 64Kb
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DMEM_SIZE : natural := 1024*16; -- 64Kb
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IMEM_LOWM : std_logic := '1';
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IMEM_LOWM : std_logic := '1';
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BHT_SIZE : natural := 256;
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BHT_SIZE : natural := 256;
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CFG_FLAGS : std_logic_vector(16-1 downto 0) := "00000000"&"01100111";
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CFG_FLAGS : std_logic_vector(16-1 downto 0) := "00000000"&"01100111";
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SIMULATION_ONLY : std_logic := '1'
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SIMULATION_ONLY : std_logic := '1'
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);
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);
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port(
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port(
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CLK_i : in std_logic; -- clock
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CLK_i : in std_logic; -- clock
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RST_i : in std_logic; -- reset
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RST_i : in std_logic; -- reset
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-- Instruction memory interface
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-- Instruction memory interface
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INSTR_i : in std_logic_vector(ILEN*2-1 downto 0); -- two instructions!
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INSTR_i : in std_logic_vector(ILEN*2-1 downto 0); -- two instructions!
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-- Data memory interface
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-- Data memory interface
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DDAT0_i : in std_logic_vector(SDLEN-1 downto 0); -- data port #0 data-in
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DDAT0_i : in std_logic_vector(SDLEN-1 downto 0); -- data port #0 data-in
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DDAT1_i : in std_logic_vector(SDLEN-1 downto 0); -- data port #1 data-in
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DDAT1_i : in std_logic_vector(SDLEN-1 downto 0); -- data port #1 data-in
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IADR_ERR_i : in std_logic; -- instr. port address error
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IADR_ERR_i : in std_logic; -- instr. port address error
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DADR0_ERR_i : in std_logic; -- data port #0 address error
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DADR0_ERR_i : in std_logic; -- data port #0 address error
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DADR1_ERR_i : in std_logic; -- data port #1 address error
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DADR1_ERR_i : in std_logic; -- data port #1 address error
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IDADR_CFLT_i : in std_logic; -- address conflict error
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IDADR_CFLT_i : in std_logic; -- address conflict error
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-- Check enable (simulation only)
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-- Check enable (simulation only)
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CHK_ENB_i : in std_logic;
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CHK_ENB_i : in std_logic;
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-- External Interrupt (from PLIC)
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-- External Interrupt (from PLIC)
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EXT_INT_i : in std_logic;
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EXT_INT_i : in std_logic;
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-- Host interface
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-- Host interface
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MFROMHOST_WE_i : in std_logic; -- MFROMHOST write-enable
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MFROMHOST_WE_i : in std_logic; -- MFROMHOST write-enable
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MFROMHOST_i : in std_logic_vector(SDLEN-1 downto 0); -- MFROMHOST data-in
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MFROMHOST_i : in std_logic_vector(SDLEN-1 downto 0); -- MFROMHOST data-in
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-- Control Port
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-- Control Port
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CP_RE_i : in std_logic; -- CP read-enable
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CP_RE_i : in std_logic; -- CP read-enable
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CP_WE_i : in std_logic; -- CP write-enable
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CP_WE_i : in std_logic; -- CP write-enable
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CP_ADR_i : in std_logic_vector(17-1 downto 0); -- CP address
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CP_ADR_i : in std_logic_vector(17-1 downto 0); -- CP address
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CP_D_i : in std_logic_vector(SDLEN-1 downto 0); -- CP data-in
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CP_D_i : in std_logic_vector(SDLEN-1 downto 0); -- CP data-in
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|
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HALT_o : out std_logic; -- halt flag
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HALT_o : out std_logic; -- halt flag
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-- Instruction memory interface
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-- Instruction memory interface
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IADR_o : out unsigned(ALEN-1 downto 0); -- instr. port address
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IADR_o : out unsigned(ALEN-1 downto 0); -- instr. port address
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-- Data memory interface
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-- Data memory interface
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DRE_o : out std_logic_vector(2-1 downto 0); -- data port #0/1 read-enable
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DRE_o : out std_logic_vector(2-1 downto 0); -- data port #0/1 read-enable
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DWE0_o : out std_logic; -- data port #0 write-enable
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DWE0_o : out std_logic; -- data port #0 write-enable
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DBE_o : out std_logic_vector(4-1 downto 0); -- data port #0 byte-enable
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DBE_o : out std_logic_vector(4-1 downto 0); -- data port #0 byte-enable
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DADR0_o : out unsigned(ALEN-1 downto 0); -- data port #0 address
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DADR0_o : out unsigned(ALEN-1 downto 0); -- data port #0 address
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DADR1_o : out unsigned(ALEN-1 downto 0); -- data port #1 address
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DADR1_o : out unsigned(ALEN-1 downto 0); -- data port #1 address
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DIADR0_o : out unsigned(ALEN-1 downto 0); -- data port #0 address
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DIADR0_o : out unsigned(ALEN-1 downto 0); -- data port #0 address
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DIADR1_o : out unsigned(ALEN-1 downto 0); -- data port #1 address
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DIADR1_o : out unsigned(ALEN-1 downto 0); -- data port #1 address
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DIMS_o : out std_logic_vector(2-1 downto 0); -- data port #0/1 mem. select
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DIMS_o : out std_logic_vector(2-1 downto 0); -- data port #0/1 mem. select
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DDAT0_o : out std_logic_vector(SDLEN-1 downto 0); -- data port #0 data-out
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DDAT0_o : out std_logic_vector(SDLEN-1 downto 0); -- data port #0 data-out
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-- Host interface
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-- Host interface
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MTOHOST_OE_o : out std_logic; -- MTOHOST output-enable
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MTOHOST_OE_o : out std_logic; -- MTOHOST output-enable
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MTOHOST_o : out std_logic_vector(SDLEN-1 downto 0); -- MTOHOST data-out
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MTOHOST_o : out std_logic_vector(SDLEN-1 downto 0); -- MTOHOST data-out
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-- Control port
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-- Control port
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CP_Q_o : out std_logic_vector(SDLEN-1 downto 0) -- CP data-out
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CP_Q_o : out std_logic_vector(SDLEN-1 downto 0) -- CP data-out
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);
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);
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end RV01_CPU_2W;
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end RV01_CPU_2W;
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architecture ARC of RV01_CPU_2W is
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architecture ARC of RV01_CPU_2W is
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|
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constant SZERO : SDWORD_T := (others => '0');
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constant SZERO : SDWORD_T := (others => '0');
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constant LZERO : LDWORD_T := (others => '0');
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constant LZERO : LDWORD_T := (others => '0');
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constant PARALLEL_EXECUTION_ENABLED : std_logic := CFG_FLAGS(0);
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constant PARALLEL_EXECUTION_ENABLED : std_logic := CFG_FLAGS(0);
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constant DELAYED_EXECUTION_ENABLED : std_logic := CFG_FLAGS(1);
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constant DELAYED_EXECUTION_ENABLED : std_logic := CFG_FLAGS(1);
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constant BRANCH_PREDICTION_ENABLED : std_logic := CFG_FLAGS(2);
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constant BRANCH_PREDICTION_ENABLED : std_logic := CFG_FLAGS(2);
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constant JALR_PREDICTION_ENABLED : std_logic := CFG_FLAGS(3);
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constant JALR_PREDICTION_ENABLED : std_logic := CFG_FLAGS(3);
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constant FPU_PRESENT : std_logic := CFG_FLAGS(4);
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constant FPU_PRESENT : std_logic := CFG_FLAGS(4);
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constant DM_PRESENT : std_logic := CFG_FLAGS(5);
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constant DM_PRESENT : std_logic := CFG_FLAGS(5);
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-- number of (superscalar) ways
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-- number of (superscalar) ways
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constant NW : natural := 2;
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constant NW : natural := 2;
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component RV01_FTCHLOG_1W is
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component RV01_FTCHLOG_1W is
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port(
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port(
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CLK_i : in std_logic;
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CLK_i : in std_logic;
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RST_i : in std_logic;
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RST_i : in std_logic;
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STRT_i : in std_logic;
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STRT_i : in std_logic;
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STRTPC_i : in ADR_T;
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STRTPC_i : in ADR_T;
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HALT_i : in std_logic;
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HALT_i : in std_logic;
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BJX_i : in std_logic;
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BJX_i : in std_logic;
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BJTA_i : in ADR_T;
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BJTA_i : in ADR_T;
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PBX_i : in std_logic;
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PBX_i : in std_logic;
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PBTA_i : in ADR_T;
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PBTA_i : in ADR_T;
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KLL1_i : in std_logic;
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KLL1_i : in std_logic;
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PJRX_i : std_logic;
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PJRX_i : std_logic;
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PJRTA_i : in ADR_T;
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PJRTA_i : in ADR_T;
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EXCP_i : in std_logic;
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EXCP_i : in std_logic;
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ERET_i : in std_logic;
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ERET_i : in std_logic;
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RFTCH_i : in std_logic;
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RFTCH_i : in std_logic;
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ETVA_i : in ADR_T;
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ETVA_i : in ADR_T;
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PSTALL_i : in std_logic;
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PSTALL_i : in std_logic;
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DHALT_i : in std_logic;
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DHALT_i : in std_logic;
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|
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IFV_o : out std_logic;
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IFV_o : out std_logic;
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IADR0_o : out ADR_T;
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IADR0_o : out ADR_T;
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IADR_MIS_o : out std_logic
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IADR_MIS_o : out std_logic
|
);
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);
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end component;
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end component;
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|
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component RV01_FTCHLOG_2W is
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component RV01_FTCHLOG_2W is
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port(
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port(
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CLK_i : in std_logic;
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CLK_i : in std_logic;
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RST_i : in std_logic;
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RST_i : in std_logic;
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STRT_i : in std_logic;
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STRT_i : in std_logic;
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STRTPC_i : in ADR_T;
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STRTPC_i : in ADR_T;
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HALT_i : in std_logic;
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HALT_i : in std_logic;
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BJX_i : in std_logic;
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BJX_i : in std_logic;
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BJTA_i : in ADR_T;
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BJTA_i : in ADR_T;
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PBX_i : in std_logic;
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PBX_i : in std_logic;
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PBTA_i : in ADR_T;
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PBTA_i : in ADR_T;
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KLL1_i : in std_logic;
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KLL1_i : in std_logic;
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PJRX_i : in std_logic;
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PJRX_i : in std_logic;
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PJRTA_i : in ADR_T;
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PJRTA_i : in ADR_T;
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EXCP_i : in std_logic;
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EXCP_i : in std_logic;
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ERET_i : in std_logic;
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ERET_i : in std_logic;
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RFTCH_i : in std_logic;
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RFTCH_i : in std_logic;
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ETVA_i : in ADR_T;
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ETVA_i : in ADR_T;
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PSTALL_i : in std_logic;
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PSTALL_i : in std_logic;
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DHALT_i : in std_logic;
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DHALT_i : in std_logic;
|
|
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IFV_o : out std_logic_vector(2-1 downto 0);
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IFV_o : out std_logic_vector(2-1 downto 0);
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IADR0_o : out ADR_T;
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IADR0_o : out ADR_T;
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IADR1_o : out ADR_T;
|
IADR1_o : out ADR_T;
|
IADR_MIS_o : out std_logic
|
IADR_MIS_o : out std_logic
|
);
|
);
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end component;
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end component;
|
|
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component RV01_IFQ is
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component RV01_IFQ is
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port(
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port(
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CLK_i : in std_logic;
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CLK_i : in std_logic;
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RST_i : in std_logic;
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RST_i : in std_logic;
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ID_HALT_i : in std_logic;
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ID_HALT_i : in std_logic;
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IX_BJX_i : in std_logic;
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IX_BJX_i : in std_logic;
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ID_ISSUE_i : in std_logic_vector(2-1 downto 0);
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ID_ISSUE_i : in std_logic_vector(2-1 downto 0);
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IF_V_i : in std_logic_vector(2-1 downto 0);
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IF_V_i : in std_logic_vector(2-1 downto 0);
|
IF_PC0_i : in unsigned(ALEN-1 downto 0);
|
IF_PC0_i : in unsigned(ALEN-1 downto 0);
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IF_PC1_i : in unsigned(ALEN-1 downto 0);
|
IF_PC1_i : in unsigned(ALEN-1 downto 0);
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IF_INSTR0_i : in std_logic_vector(ILEN-1 downto 0);
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IF_INSTR0_i : in std_logic_vector(ILEN-1 downto 0);
|
IF_INSTR1_i : in std_logic_vector(ILEN-1 downto 0);
|
IF_INSTR1_i : in std_logic_vector(ILEN-1 downto 0);
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IF_DEC_INSTR0_i : in DEC_INSTR_T;
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IF_DEC_INSTR0_i : in DEC_INSTR_T;
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IF_DEC_INSTR1_i : in DEC_INSTR_T;
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IF_DEC_INSTR1_i : in DEC_INSTR_T;
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IF_OPA_PC0_i : in std_logic;
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IF_OPA_PC0_i : in std_logic;
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IF_OPA_PC1_i : in std_logic;
|
IF_OPA_PC1_i : in std_logic;
|
IF_OPB_IMM0_i : in std_logic;
|
IF_OPB_IMM0_i : in std_logic;
|
IF_OPB_IMM1_i : in std_logic;
|
IF_OPB_IMM1_i : in std_logic;
|
IF_BPVD0_i : in std_logic_vector(3-1 downto 0);
|
IF_BPVD0_i : in std_logic_vector(3-1 downto 0);
|
IF_BPVD1_i : in std_logic_vector(3-1 downto 0);
|
IF_BPVD1_i : in std_logic_vector(3-1 downto 0);
|
|
|
PSTALL_o : out std_logic;
|
PSTALL_o : out std_logic;
|
ID_V_o : out std_logic_vector(2-1 downto 0);
|
ID_V_o : out std_logic_vector(2-1 downto 0);
|
ID_PC0_o : out unsigned(ALEN-1 downto 0);
|
ID_PC0_o : out unsigned(ALEN-1 downto 0);
|
ID_PC1_o : out unsigned(ALEN-1 downto 0);
|
ID_PC1_o : out unsigned(ALEN-1 downto 0);
|
ID_INSTR0_o : out std_logic_vector(ILEN-1 downto 0);
|
ID_INSTR0_o : out std_logic_vector(ILEN-1 downto 0);
|
ID_INSTR1_o : out std_logic_vector(ILEN-1 downto 0);
|
ID_INSTR1_o : out std_logic_vector(ILEN-1 downto 0);
|
ID_DEC_INSTR0_o : out DEC_INSTR_T;
|
ID_DEC_INSTR0_o : out DEC_INSTR_T;
|
ID_DEC_INSTR1_o : out DEC_INSTR_T;
|
ID_DEC_INSTR1_o : out DEC_INSTR_T;
|
ID_OPA_PC0_o : out std_logic;
|
ID_OPA_PC0_o : out std_logic;
|
ID_OPA_PC1_o : out std_logic;
|
ID_OPA_PC1_o : out std_logic;
|
ID_OPB_IMM0_o : out std_logic;
|
ID_OPB_IMM0_o : out std_logic;
|
ID_OPB_IMM1_o : out std_logic;
|
ID_OPB_IMM1_o : out std_logic;
|
ID_BPVD0_o : out std_logic_vector(3-1 downto 0);
|
ID_BPVD0_o : out std_logic_vector(3-1 downto 0);
|
ID_BPVD1_o : out std_logic_vector(3-1 downto 0)
|
ID_BPVD1_o : out std_logic_vector(3-1 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_IDEC is
|
component RV01_IDEC is
|
port(
|
port(
|
INSTR_i : in std_logic_vector(ILEN-1 downto 0);
|
INSTR_i : in std_logic_vector(ILEN-1 downto 0);
|
IADR_MIS_i : in std_logic;
|
IADR_MIS_i : in std_logic;
|
IADR_ERR_i : in std_logic;
|
IADR_ERR_i : in std_logic;
|
|
|
OPA_PC_o : out std_logic;
|
OPA_PC_o : out std_logic;
|
OPB_IMM_o : out std_logic;
|
OPB_IMM_o : out std_logic;
|
DEC_INSTR_o : out DEC_INSTR_T
|
DEC_INSTR_o : out DEC_INSTR_T
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_PXLOG is
|
component RV01_PXLOG is
|
port(
|
port(
|
ID_INSTR0_i : in DEC_INSTR_T;
|
ID_INSTR0_i : in DEC_INSTR_T;
|
ID_INSTR1_i : in DEC_INSTR_T;
|
ID_INSTR1_i : in DEC_INSTR_T;
|
ID_V_i : in std_logic_vector(2-1 downto 0);
|
ID_V_i : in std_logic_vector(2-1 downto 0);
|
ID_FWDE_i : in std_logic_vector(2-1 downto 0);
|
ID_FWDE_i : in std_logic_vector(2-1 downto 0);
|
|
|
PXE1_o : out std_logic
|
PXE1_o : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_ISSLOG is
|
component RV01_ISSLOG is
|
generic(
|
generic(
|
NW : natural := 2
|
NW : natural := 2
|
);
|
);
|
port(
|
port(
|
V_i : in std_logic_vector(NW-1 downto 0);
|
V_i : in std_logic_vector(NW-1 downto 0);
|
BJX_i : in std_logic;
|
BJX_i : in std_logic;
|
PC1_i : in ADR_T;
|
PC1_i : in ADR_T;
|
PS_i : in std_logic_vector(NW-1 downto 0);
|
PS_i : in std_logic_vector(NW-1 downto 0);
|
SBF_i : in std_logic;
|
SBF_i : in std_logic;
|
DIV_STRT_i : in std_logic;
|
DIV_STRT_i : in std_logic;
|
DIV_BSY_i : in std_logic;
|
DIV_BSY_i : in std_logic;
|
SEQX_i : in std_logic;
|
SEQX_i : in std_logic;
|
PXE_i : in std_logic;
|
PXE_i : in std_logic;
|
PXE1_i : in std_logic;
|
PXE1_i : in std_logic;
|
STEP_i : in std_logic;
|
STEP_i : in std_logic;
|
PSLP_i : in std_logic;
|
PSLP_i : in std_logic;
|
|
|
V_o : out std_logic_vector(NW-1 downto 0);
|
V_o : out std_logic_vector(NW-1 downto 0);
|
JLRA_o : out ADR_VEC_T(NW-1 downto 0);
|
JLRA_o : out ADR_VEC_T(NW-1 downto 0);
|
ISSUE_o : out std_logic_vector(NW-1 downto 0)
|
ISSUE_o : out std_logic_vector(NW-1 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_PIPE_A_DEC is
|
component RV01_PIPE_A_DEC is
|
port(
|
port(
|
INSTR_i : in DEC_INSTR_T;
|
INSTR_i : in DEC_INSTR_T;
|
|
|
FWDE_o : out std_logic;
|
FWDE_o : out std_logic;
|
SEL_o : out std_logic_vector(4-1 downto 0)
|
SEL_o : out std_logic_vector(4-1 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_FWDLOG_2W_P6 is
|
component RV01_FWDLOG_2W_P6 is
|
port(
|
port(
|
ID_RX_i : in RID_T;
|
ID_RX_i : in RID_T;
|
ID_RRX_i : in std_logic;
|
ID_RRX_i : in std_logic;
|
IX1_INSTR0_i : in DEC_INSTR_T;
|
IX1_INSTR0_i : in DEC_INSTR_T;
|
IX2_INSTR0_i : in DEC_INSTR_T;
|
IX2_INSTR0_i : in DEC_INSTR_T;
|
IX3_INSTR0_i : in DEC_INSTR_T;
|
IX3_INSTR0_i : in DEC_INSTR_T;
|
IX1_INSTR1_i : in DEC_INSTR_T;
|
IX1_INSTR1_i : in DEC_INSTR_T;
|
IX2_INSTR1_i : in DEC_INSTR_T;
|
IX2_INSTR1_i : in DEC_INSTR_T;
|
IX3_INSTR1_i : in DEC_INSTR_T;
|
IX3_INSTR1_i : in DEC_INSTR_T;
|
IX1_PA_RES0_i : in SDWORD_T;
|
IX1_PA_RES0_i : in SDWORD_T;
|
IX1_PA_RES1_i : in SDWORD_T;
|
IX1_PA_RES1_i : in SDWORD_T;
|
IX2_PA_RES0_i : in SDWORD_T;
|
IX2_PA_RES0_i : in SDWORD_T;
|
IX2_PA_RES1_i : in SDWORD_T;
|
IX2_PA_RES1_i : in SDWORD_T;
|
IX3_PA_RES0_i : in SDWORD_T;
|
IX3_PA_RES0_i : in SDWORD_T;
|
IX3_PA_RES1_i : in SDWORD_T;
|
IX3_PA_RES1_i : in SDWORD_T;
|
ID_OPX_NOFWD_i : in SDWORD_T;
|
ID_OPX_NOFWD_i : in SDWORD_T;
|
IX1_V_i : in std_logic_vector(2-1 downto 0);
|
IX1_V_i : in std_logic_vector(2-1 downto 0);
|
IX2_V_i : in std_logic_vector(2-1 downto 0);
|
IX2_V_i : in std_logic_vector(2-1 downto 0);
|
IX3_V_i : in std_logic_vector(2-1 downto 0);
|
IX3_V_i : in std_logic_vector(2-1 downto 0);
|
IX1_FWDE_i : in std_logic_vector(2-1 downto 0);
|
IX1_FWDE_i : in std_logic_vector(2-1 downto 0);
|
IX2_FWDE_i : in std_logic_vector(2-1 downto 0);
|
IX2_FWDE_i : in std_logic_vector(2-1 downto 0);
|
IX3_FWDE_i : in std_logic_vector(2-1 downto 0);
|
IX3_FWDE_i : in std_logic_vector(2-1 downto 0);
|
NOREGS_i : in std_logic;
|
NOREGS_i : in std_logic;
|
NOREGD_i : in SDWORD_T;
|
NOREGD_i : in SDWORD_T;
|
|
|
ID_OPX_o : out SDWORD_T
|
ID_OPX_o : out SDWORD_T
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_PIPE_B is
|
component RV01_PIPE_B is
|
port(
|
port(
|
CLK_i : in std_logic;
|
CLK_i : in std_logic;
|
OP_i : in ALU_OP_T;
|
OP_i : in ALU_OP_T;
|
SU_i : in std_logic;
|
SU_i : in std_logic;
|
PC0_i : in unsigned(SDLEN-1 downto 0);
|
PC0_i : in unsigned(SDLEN-1 downto 0);
|
PC1_i : in unsigned(SDLEN-1 downto 0);
|
PC1_i : in unsigned(SDLEN-1 downto 0);
|
OPA_i : in SDWORD_T;
|
OPA_i : in SDWORD_T;
|
OPB_i : in SDWORD_T;
|
OPB_i : in SDWORD_T;
|
|
|
RES_o : out SDWORD_T
|
RES_o : out SDWORD_T
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_BJXLOG is
|
component RV01_BJXLOG is
|
generic(
|
generic(
|
JRPE : std_logic := '1'
|
JRPE : std_logic := '1'
|
);
|
);
|
port(
|
port(
|
CLK_i : in std_logic;
|
CLK_i : in std_logic;
|
RST_i : in std_logic;
|
RST_i : in std_logic;
|
BJ_OP_i : in BJ_OP_T;
|
BJ_OP_i : in BJ_OP_T;
|
SU_i : in std_logic;
|
SU_i : in std_logic;
|
PC_i : in ADR_T;
|
PC_i : in ADR_T;
|
OPA_i : in SDWORD_T;
|
OPA_i : in SDWORD_T;
|
OPB_i : in SDWORD_T;
|
OPB_i : in SDWORD_T;
|
IMM_i : in SDWORD_T;
|
IMM_i : in SDWORD_T;
|
IV_i : in std_logic;
|
IV_i : in std_logic;
|
FSTLL_i : in std_logic;
|
FSTLL_i : in std_logic;
|
MPJRX_i : in std_logic;
|
MPJRX_i : in std_logic;
|
|
|
BJX_o : out std_logic;
|
BJX_o : out std_logic;
|
BJTA_o : out ADR_T
|
BJTA_o : out ADR_T
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_LSU is
|
component RV01_LSU is
|
port(
|
port(
|
CLK_i : in std_logic;
|
CLK_i : in std_logic;
|
RST_i : in std_logic;
|
RST_i : in std_logic;
|
IV_i : in std_logic;
|
IV_i : in std_logic;
|
LS_OP_i : in LS_OP_T;
|
LS_OP_i : in LS_OP_T;
|
SU_i : in std_logic;
|
SU_i : in std_logic;
|
OPA_i : in SDWORD_T;
|
OPA_i : in SDWORD_T;
|
OPB_i : in SDWORD_T;
|
OPB_i : in SDWORD_T;
|
IMM_i : in SDWORD_T;
|
IMM_i : in SDWORD_T;
|
LDAT_i : in std_logic_vector(SDLEN-1 downto 0);
|
LDAT_i : in std_logic_vector(SDLEN-1 downto 0);
|
|
|
RE_o : out std_logic;
|
RE_o : out std_logic;
|
WE_o : out std_logic;
|
WE_o : out std_logic;
|
MALGN_o : out std_logic;
|
MALGN_o : out std_logic;
|
ADR_o : out unsigned(ALEN-1 downto 0);
|
ADR_o : out unsigned(ALEN-1 downto 0);
|
SBE_o : out std_logic_vector(4-1 downto 0);
|
SBE_o : out std_logic_vector(4-1 downto 0);
|
SDAT_o : out std_logic_vector(SDLEN-1 downto 0);
|
SDAT_o : out std_logic_vector(SDLEN-1 downto 0);
|
LDATV_o : out std_logic;
|
LDATV_o : out std_logic;
|
LDAT_o : out SDWORD_T
|
LDAT_o : out SDWORD_T
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_SBUF_2W is
|
component RV01_SBUF_2W is
|
generic(
|
generic(
|
NW : natural := 2;
|
NW : natural := 2;
|
DEPTH : natural := 4;
|
DEPTH : natural := 4;
|
SIMULATION_ONLY : std_logic := '0'
|
SIMULATION_ONLY : std_logic := '0'
|
);
|
);
|
port(
|
port(
|
CLK_i : in std_logic;
|
CLK_i : in std_logic;
|
RST_i : in std_logic;
|
RST_i : in std_logic;
|
CLRB_i : in std_logic;
|
CLRB_i : in std_logic;
|
KTS_i : in std_logic;
|
KTS_i : in std_logic;
|
RE_i : in std_logic_vector(NW-1 downto 0);
|
RE_i : in std_logic_vector(NW-1 downto 0);
|
WE_i : in std_logic_vector(NW-1 downto 0);
|
WE_i : in std_logic_vector(NW-1 downto 0);
|
BE0_i : in std_logic_vector(4-1 downto 0);
|
BE0_i : in std_logic_vector(4-1 downto 0);
|
BE1_i : in std_logic_vector(4-1 downto 0);
|
BE1_i : in std_logic_vector(4-1 downto 0);
|
D0_i : in std_logic_vector(SDLEN-1 downto 0);
|
D0_i : in std_logic_vector(SDLEN-1 downto 0);
|
D1_i : in std_logic_vector(SDLEN-1 downto 0);
|
D1_i : in std_logic_vector(SDLEN-1 downto 0);
|
IX1_V_i : std_logic_vector(2-1 downto 0);
|
IX1_V_i : std_logic_vector(2-1 downto 0);
|
LS_OP0_i : in LS_OP_T;
|
LS_OP0_i : in LS_OP_T;
|
LS_OP1_i : in LS_OP_T;
|
LS_OP1_i : in LS_OP_T;
|
DADR0_i : in ADR_T;
|
DADR0_i : in ADR_T;
|
DADR1_i : in ADR_T;
|
DADR1_i : in ADR_T;
|
SADR0_i : in ADR_T;
|
SADR0_i : in ADR_T;
|
SADR1_i : in ADR_T;
|
SADR1_i : in ADR_T;
|
|
|
BF_o : out std_logic;
|
BF_o : out std_logic;
|
NOPR_o : out std_logic;
|
NOPR_o : out std_logic;
|
S2LAC_o : out std_logic_vector(2-1 downto 0);
|
S2LAC_o : out std_logic_vector(2-1 downto 0);
|
WE_o : out std_logic;
|
WE_o : out std_logic;
|
LS_OP_o : out LS_OP_T;
|
LS_OP_o : out LS_OP_T;
|
BE_o : out std_logic_vector(4-1 downto 0);
|
BE_o : out std_logic_vector(4-1 downto 0);
|
Q_o : out std_logic_vector(SDLEN-1 downto 0);
|
Q_o : out std_logic_vector(SDLEN-1 downto 0);
|
SADR_o : out ADR_T
|
SADR_o : out ADR_T
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_REGFILE_32X32_2W is
|
component RV01_REGFILE_32X32_2W is
|
port(
|
port(
|
CLK_i : in std_logic;
|
CLK_i : in std_logic;
|
RA0_i : in RID_T;
|
RA0_i : in RID_T;
|
RA1_i : in RID_T;
|
RA1_i : in RID_T;
|
RA2_i : in RID_T;
|
RA2_i : in RID_T;
|
RA3_i : in RID_T;
|
RA3_i : in RID_T;
|
WA0_i : in RID_T;
|
WA0_i : in RID_T;
|
WA1_i : in RID_T;
|
WA1_i : in RID_T;
|
WE0_i : in std_logic;
|
WE0_i : in std_logic;
|
WE1_i : in std_logic;
|
WE1_i : in std_logic;
|
D0_i : in std_logic_vector(SDLEN-1 downto 0);
|
D0_i : in std_logic_vector(SDLEN-1 downto 0);
|
D1_i : in std_logic_vector(SDLEN-1 downto 0);
|
D1_i : in std_logic_vector(SDLEN-1 downto 0);
|
|
|
Q0_o : out std_logic_vector(SDLEN-1 downto 0);
|
Q0_o : out std_logic_vector(SDLEN-1 downto 0);
|
Q1_o : out std_logic_vector(SDLEN-1 downto 0);
|
Q1_o : out std_logic_vector(SDLEN-1 downto 0);
|
Q2_o : out std_logic_vector(SDLEN-1 downto 0);
|
Q2_o : out std_logic_vector(SDLEN-1 downto 0);
|
Q3_o : out std_logic_vector(SDLEN-1 downto 0)
|
Q3_o : out std_logic_vector(SDLEN-1 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_DIVLOG is
|
component RV01_DIVLOG is
|
port(
|
port(
|
V_i : in std_logic;
|
V_i : in std_logic;
|
INSTR_i : in DEC_INSTR_T;
|
INSTR_i : in DEC_INSTR_T;
|
DIV_V_i : in std_logic;
|
DIV_V_i : in std_logic;
|
|
|
DIV_STRT_o : out std_logic;
|
DIV_STRT_o : out std_logic;
|
DIV_QS_o : out std_logic;
|
DIV_QS_o : out std_logic;
|
DIV_CLRV_o : out std_logic
|
DIV_CLRV_o : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_DIVIDER_R2 is
|
component RV01_DIVIDER_R2 is
|
port(
|
port(
|
CLK_i : in std_logic;
|
CLK_i : in std_logic;
|
RST_i : in std_logic;
|
RST_i : in std_logic;
|
STRT_i : in std_logic;
|
STRT_i : in std_logic;
|
SU_i : in std_logic;
|
SU_i : in std_logic;
|
QS_i : in std_logic;
|
QS_i : in std_logic;
|
DD_i : in SDWORD_T;
|
DD_i : in SDWORD_T;
|
DR_i : in SDWORD_T;
|
DR_i : in SDWORD_T;
|
CLRD_i : in std_logic;
|
CLRD_i : in std_logic;
|
CLRV_i : in std_logic;
|
CLRV_i : in std_logic;
|
|
|
Q_o : out SDWORD_T;
|
Q_o : out SDWORD_T;
|
QV_o : out std_logic;
|
QV_o : out std_logic;
|
BSY_o : out std_logic
|
BSY_o : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_CSRU is
|
component RV01_CSRU is
|
generic(
|
generic(
|
PXE : std_logic := '1';
|
PXE : std_logic := '1';
|
FPU_PRESENT : std_logic := '0';
|
FPU_PRESENT : std_logic := '0';
|
NW : natural := 2
|
NW : natural := 2
|
);
|
);
|
port(
|
port(
|
CLK_i : in std_logic;
|
CLK_i : in std_logic;
|
RST_i : in std_logic;
|
RST_i : in std_logic;
|
IX1_V0_i : in std_logic;
|
IX1_V0_i : in std_logic;
|
CS_OP_i : in CS_OP_T;
|
CS_OP_i : in CS_OP_T;
|
RS1_i : in RID_T;
|
RS1_i : in RID_T;
|
ADR_i : in signed(12-1 downto 0);
|
ADR_i : in signed(12-1 downto 0);
|
WE_i : in std_logic;
|
WE_i : in std_logic;
|
CSRD_i : in SDWORD_T;
|
CSRD_i : in SDWORD_T;
|
EXCP_i : in std_logic;
|
EXCP_i : in std_logic;
|
EPC_i : in unsigned(ALEN-1 downto 0);
|
EPC_i : in unsigned(ALEN-1 downto 0);
|
ECAUSE_i : in std_logic_vector(5-1 downto 0);
|
ECAUSE_i : in std_logic_vector(5-1 downto 0);
|
EBADR_i : in unsigned(ALEN-1 downto 0);
|
EBADR_i : in unsigned(ALEN-1 downto 0);
|
ERET_i : in std_logic;
|
ERET_i : in std_logic;
|
IX3_V_i : in std_logic_vector(NW-1 downto 0);
|
IX3_V_i : in std_logic_vector(NW-1 downto 0);
|
NOPR_i : in std_logic;
|
NOPR_i : in std_logic;
|
HALT_i : in std_logic;
|
HALT_i : in std_logic;
|
STOPCYCLE_i : in std_logic;
|
STOPCYCLE_i : in std_logic;
|
STOPTIME_i : in std_logic;
|
STOPTIME_i : in std_logic;
|
MFROMHOST_WE_i : in std_logic;
|
MFROMHOST_WE_i : in std_logic;
|
MFROMHOST_i : in std_logic_vector(SDLEN-1 downto 0);
|
MFROMHOST_i : in std_logic_vector(SDLEN-1 downto 0);
|
DMODE_i : in std_logic;
|
DMODE_i : in std_logic;
|
DIE_i : in std_logic;
|
DIE_i : in std_logic;
|
CPRE_i : in std_logic;
|
CPRE_i : in std_logic;
|
CPWE_i : in std_logic;
|
CPWE_i : in std_logic;
|
CPADR_i : in std_logic_vector(17-1 downto 0);
|
CPADR_i : in std_logic_vector(17-1 downto 0);
|
CPD_i : in std_logic_vector(SDLEN-1 downto 0);
|
CPD_i : in std_logic_vector(SDLEN-1 downto 0);
|
|
|
PXE_o : out std_logic;
|
PXE_o : out std_logic;
|
MSTATUS_o : out SDWORD_T;
|
MSTATUS_o : out SDWORD_T;
|
MEPC_o : out unsigned(ALEN-1 downto 0);
|
MEPC_o : out unsigned(ALEN-1 downto 0);
|
MBASE_o : out unsigned(ALEN-1 downto 0);
|
MBASE_o : out unsigned(ALEN-1 downto 0);
|
MBOUND_o : out unsigned(ALEN-1 downto 0);
|
MBOUND_o : out unsigned(ALEN-1 downto 0);
|
MIBASE_o : out unsigned(ALEN-1 downto 0);
|
MIBASE_o : out unsigned(ALEN-1 downto 0);
|
MIBOUND_o : out unsigned(ALEN-1 downto 0);
|
MIBOUND_o : out unsigned(ALEN-1 downto 0);
|
MDBASE_o : out unsigned(ALEN-1 downto 0);
|
MDBASE_o : out unsigned(ALEN-1 downto 0);
|
MDBOUND_o : out unsigned(ALEN-1 downto 0);
|
MDBOUND_o : out unsigned(ALEN-1 downto 0);
|
ETVA_o : out ADR_T;
|
ETVA_o : out ADR_T;
|
MTOHOST_o : out std_logic_vector(SDLEN-1 downto 0);
|
MTOHOST_o : out std_logic_vector(SDLEN-1 downto 0);
|
MTOHOST_OE_o : out std_logic;
|
MTOHOST_OE_o : out std_logic;
|
ILLG_o : out std_logic;
|
ILLG_o : out std_logic;
|
SFT_INT_o : out std_logic;
|
SFT_INT_o : out std_logic;
|
TMR_INT_o : out std_logic;
|
TMR_INT_o : out std_logic;
|
FFLAGS_o : out std_logic_vector(5-1 downto 0);
|
FFLAGS_o : out std_logic_vector(5-1 downto 0);
|
FRM_o : out std_logic_vector(3-1 downto 0);
|
FRM_o : out std_logic_vector(3-1 downto 0);
|
IE_o : out std_logic;
|
IE_o : out std_logic;
|
CSRQ_o : out SDWORD_T;
|
CSRQ_o : out SDWORD_T;
|
CPQ_o : out std_logic_vector(SDLEN-1 downto 0)
|
CPQ_o : out std_logic_vector(SDLEN-1 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_DBGLOG_IX2 is
|
component RV01_DBGLOG_IX2 is
|
generic(
|
generic(
|
NW : natural := 2
|
NW : natural := 2
|
);
|
);
|
port(
|
port(
|
CLK_i : in std_logic;
|
CLK_i : in std_logic;
|
RST_i : in std_logic;
|
RST_i : in std_logic;
|
V_i : in std_logic_vector(NW-1 downto 0);
|
V_i : in std_logic_vector(NW-1 downto 0);
|
IMNMC0_i : in INST_MNEMONIC_T;
|
IMNMC0_i : in INST_MNEMONIC_T;
|
RFTCH0_i : in std_logic;
|
RFTCH0_i : in std_logic;
|
STEP_i : in std_logic;
|
STEP_i : in std_logic;
|
HOBRK_i : in std_logic;
|
HOBRK_i : in std_logic;
|
HRQ_i : in std_logic;
|
HRQ_i : in std_logic;
|
|
|
STEP_o : out std_logic;
|
STEP_o : out std_logic;
|
HALT_o : out std_logic_vector(NW-1 downto 0);
|
HALT_o : out std_logic_vector(NW-1 downto 0);
|
HIS_o : out std_logic
|
HIS_o : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_HLTLOG_IX2 is
|
component RV01_HLTLOG_IX2 is
|
generic(
|
generic(
|
NW : natural := 2
|
NW : natural := 2
|
);
|
);
|
port(
|
port(
|
IMNMC0_i : in INST_MNEMONIC_T;
|
IMNMC0_i : in INST_MNEMONIC_T;
|
V_i : in std_logic_vector(NW-1 downto 0);
|
V_i : in std_logic_vector(NW-1 downto 0);
|
PC0_i : in unsigned(ALEN-1 downto 0);
|
PC0_i : in unsigned(ALEN-1 downto 0);
|
PC1_i : in unsigned(ALEN-1 downto 0);
|
PC1_i : in unsigned(ALEN-1 downto 0);
|
HOBRK_i : in std_logic;
|
HOBRK_i : in std_logic;
|
HOADR_i : in std_logic_vector(NW-1 downto 0);
|
HOADR_i : in std_logic_vector(NW-1 downto 0);
|
HADR_i : in unsigned(ALEN-1 downto 0);
|
HADR_i : in unsigned(ALEN-1 downto 0);
|
HRQ_i : in std_logic;
|
HRQ_i : in std_logic;
|
|
|
HALT_o : out std_logic_vector(NW-1 downto 0);
|
HALT_o : out std_logic_vector(NW-1 downto 0);
|
HIS_o : out std_logic
|
HIS_o : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_EXCPLOG_IX1 is
|
component RV01_EXCPLOG_IX1 is
|
generic(
|
generic(
|
NW : natural := 2
|
NW : natural := 2
|
);
|
);
|
port(
|
port(
|
INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
|
INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
|
MALGN_i : in std_logic_vector(NW-1 downto 0);
|
MALGN_i : in std_logic_vector(NW-1 downto 0);
|
S2LAC_i : in std_logic_vector(NW-1 downto 0);
|
S2LAC_i : in std_logic_vector(NW-1 downto 0);
|
B2BAC_i : in std_logic;
|
B2BAC_i : in std_logic;
|
DIV_V_i : in std_logic;
|
DIV_V_i : in std_logic;
|
IDADR_CFLT_i : in std_logic;
|
IDADR_CFLT_i : in std_logic;
|
|
|
PSLP_o : out std_logic;
|
PSLP_o : out std_logic;
|
INSTR_o : out DEC_INSTR_VEC_T(NW-1 downto 0)
|
INSTR_o : out DEC_INSTR_VEC_T(NW-1 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_EXCPLOG_IX2 is
|
component RV01_EXCPLOG_IX2 is
|
generic(
|
generic(
|
NW : natural := 2
|
NW : natural := 2
|
);
|
);
|
port(
|
port(
|
V_i : in std_logic_vector(2-1 downto 0); -- slot #0,1 valid flag
|
V_i : in std_logic_vector(2-1 downto 0); -- slot #0,1 valid flag
|
INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0); -- slot #0/1 inst.
|
INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0); -- slot #0/1 inst.
|
PC0_i : in ADR_T; -- slot #0 pc
|
PC0_i : in ADR_T; -- slot #0 pc
|
PC1_i : in ADR_T; -- slot #1 pc
|
PC1_i : in ADR_T; -- slot #1 pc
|
DADR0_i : in ADR_T; -- slot #0 L/S addr.
|
DADR0_i : in ADR_T; -- slot #0 L/S addr.
|
DADR1_i : in ADR_T; -- slot #1 L/S addr.
|
DADR1_i : in ADR_T; -- slot #1 L/S addr.
|
HALT_i : in std_logic_vector(2-1 downto 0); -- halt request flag
|
HALT_i : in std_logic_vector(2-1 downto 0); -- halt request flag
|
RSM_i : in std_logic; -- resume flag
|
RSM_i : in std_logic; -- resume flag
|
DRSM_i : in std_logic; -- debug resume flag
|
DRSM_i : in std_logic; -- debug resume flag
|
EXT_INT_i : in std_logic; -- external int. flag
|
EXT_INT_i : in std_logic; -- external int. flag
|
SFT_INT_i : in std_logic; -- soft int. flag
|
SFT_INT_i : in std_logic; -- soft int. flag
|
TMR_INT_i : in std_logic; -- timer int. flag
|
TMR_INT_i : in std_logic; -- timer int. flag
|
ETVA_i : in ADR_T; -- exc. target vector addr.
|
ETVA_i : in ADR_T; -- exc. target vector addr.
|
MEPC_i : in ADR_T; -- mepc CSR
|
MEPC_i : in ADR_T; -- mepc CSR
|
DADR0_ERR_i : in std_logic; -- slot #0 L/S addr. err.
|
DADR0_ERR_i : in std_logic; -- slot #0 L/S addr. err.
|
DADR1_ERR_i : in std_logic; -- slot #1 L/S addr. err.
|
DADR1_ERR_i : in std_logic; -- slot #1 L/S addr. err.
|
CSR_ILLG_i : in std_logic;
|
CSR_ILLG_i : in std_logic;
|
IE_i : in std_logic;
|
IE_i : in std_logic;
|
STEP_i : in std_logic;
|
STEP_i : in std_logic;
|
|
|
V_o : out std_logic_vector(2-1 downto 0); -- slot #0,1 valid flag
|
V_o : out std_logic_vector(2-1 downto 0); -- slot #0,1 valid flag
|
EV_o : out std_logic_vector(2-1 downto 0); -- slot #0,1 excp. valid flag
|
EV_o : out std_logic_vector(2-1 downto 0); -- slot #0,1 excp. valid flag
|
INSTR_o : out DEC_INSTR_VEC_T(NW-1 downto 0); -- slot #0/1 inst.
|
INSTR_o : out DEC_INSTR_VEC_T(NW-1 downto 0); -- slot #0/1 inst.
|
EERTA_o : out ADR_T -- exception, eret and re-fetch target addr.
|
EERTA_o : out ADR_T -- exception, eret and re-fetch target addr.
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_EXCPLOG_IX3 is
|
component RV01_EXCPLOG_IX3 is
|
generic(
|
generic(
|
NW : natural := 2
|
NW : natural := 2
|
);
|
);
|
port(
|
port(
|
V_i : in std_logic_vector(2-1 downto 0); -- slot #0,1 valid flag
|
V_i : in std_logic_vector(2-1 downto 0); -- slot #0,1 valid flag
|
EV_i : in std_logic_vector(2-1 downto 0); -- slot #0,1 valid flag
|
EV_i : in std_logic_vector(2-1 downto 0); -- slot #0,1 valid flag
|
INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0); -- slot #0/1 inst.
|
INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0); -- slot #0/1 inst.
|
PC0_i : in ADR_T; -- slot #0 pc
|
PC0_i : in ADR_T; -- slot #0 pc
|
PC1_i : in ADR_T; -- slot #1 pc
|
PC1_i : in ADR_T; -- slot #1 pc
|
DADR0_i : in ADR_T; -- slot #0 L/S addr.
|
DADR0_i : in ADR_T; -- slot #0 L/S addr.
|
DADR1_i : in ADR_T; -- slot #1 L/S addr.
|
DADR1_i : in ADR_T; -- slot #1 L/S addr.
|
HALT_i : in std_logic; -- halt flag
|
HALT_i : in std_logic; -- halt flag
|
HIS_i : in std_logic; -- halt instruction selector
|
HIS_i : in std_logic; -- halt instruction selector
|
|
|
EXCP_o : out std_logic; -- exc. flag
|
EXCP_o : out std_logic; -- exc. flag
|
ERET_o : out std_logic; -- return from exc. flag
|
ERET_o : out std_logic; -- return from exc. flag
|
RFTCH_o : out std_logic; -- re-fetch flag
|
RFTCH_o : out std_logic; -- re-fetch flag
|
KPRD_o : out std_logic_vector(2-1 downto 0); -- slot #0/1 keep pipe reg. data flag
|
KPRD_o : out std_logic_vector(2-1 downto 0); -- slot #0/1 keep pipe reg. data flag
|
CLRP_o : out std_logic; -- clear pipe flag
|
CLRP_o : out std_logic; -- clear pipe flag
|
CLRB_o : out std_logic; -- clear store buffer flag
|
CLRB_o : out std_logic; -- clear store buffer flag
|
CLRD_o : out std_logic; -- clear divider flag
|
CLRD_o : out std_logic; -- clear divider flag
|
EPC_o : out ADR_T; -- exc. pc
|
EPC_o : out ADR_T; -- exc. pc
|
ECAUSE_o : out std_logic_vector(5-1 downto 0); -- exc. cause
|
ECAUSE_o : out std_logic_vector(5-1 downto 0); -- exc. cause
|
EDADR_o : out ADR_T -- exc. L/S addr.
|
EDADR_o : out ADR_T -- exc. L/S addr.
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_BPU is
|
component RV01_BPU is
|
generic(
|
generic(
|
BHT_SIZE : natural := 64;
|
BHT_SIZE : natural := 64;
|
PXE : std_logic := '1';
|
PXE : std_logic := '1';
|
NW : natural := 2
|
NW : natural := 2
|
);
|
);
|
port(
|
port(
|
CLK_i : in std_logic;
|
CLK_i : in std_logic;
|
RST_i : in std_logic;
|
RST_i : in std_logic;
|
INIT_STRT_i : in std_logic;
|
INIT_STRT_i : in std_logic;
|
IF_V_i : in std_logic_vector(NW-1 downto 0);
|
IF_V_i : in std_logic_vector(NW-1 downto 0);
|
IF_PC_i : in ADR_VEC_T(NW-1 downto 0);
|
IF_PC_i : in ADR_VEC_T(NW-1 downto 0);
|
IF2_V_i : in std_logic_vector(NW-1 downto 0);
|
IF2_V_i : in std_logic_vector(NW-1 downto 0);
|
IF2_PC_i : in ADR_VEC_T(NW-1 downto 0);
|
IF2_PC_i : in ADR_VEC_T(NW-1 downto 0);
|
BHT_BTA_i : in ADR_VEC_T(NW-1 downto 0);
|
BHT_BTA_i : in ADR_VEC_T(NW-1 downto 0);
|
BHT_PC_i : in ADR_VEC_T(NW-1 downto 0);
|
BHT_PC_i : in ADR_VEC_T(NW-1 downto 0);
|
BHT_CNT0_i : in std_logic_vector(2-1 downto 0);
|
BHT_CNT0_i : in std_logic_vector(2-1 downto 0);
|
BHT_CNT1_i : in std_logic_vector(2-1 downto 0);
|
BHT_CNT1_i : in std_logic_vector(2-1 downto 0);
|
BHT_WE_i : in std_logic_vector(NW-1 downto 0);
|
BHT_WE_i : in std_logic_vector(NW-1 downto 0);
|
|
|
INIT_END_o : out std_logic;
|
INIT_END_o : out std_logic;
|
PBX_o : out std_logic;
|
PBX_o : out std_logic;
|
KLL1_o : out std_logic;
|
KLL1_o : out std_logic;
|
PBTA_o : out unsigned(ALEN-1 downto 0);
|
PBTA_o : out unsigned(ALEN-1 downto 0);
|
BPVD0_o : out std_logic_vector(3-1 downto 0);
|
BPVD0_o : out std_logic_vector(3-1 downto 0);
|
BPVD1_o : out std_logic_vector(3-1 downto 0)
|
BPVD1_o : out std_logic_vector(3-1 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_BJXLOG_BV is
|
component RV01_BJXLOG_BV is
|
generic(
|
generic(
|
JRPE : std_logic := '1'
|
JRPE : std_logic := '1'
|
);
|
);
|
port(
|
port(
|
CLK_i : in std_logic;
|
CLK_i : in std_logic;
|
RST_i : in std_logic;
|
RST_i : in std_logic;
|
BJ_OP_i : in BJ_OP_T;
|
BJ_OP_i : in BJ_OP_T;
|
SU_i : in std_logic;
|
SU_i : in std_logic;
|
PC_i : in ADR_T;
|
PC_i : in ADR_T;
|
OPA_i : in SDWORD_T;
|
OPA_i : in SDWORD_T;
|
OPB_i : in SDWORD_T;
|
OPB_i : in SDWORD_T;
|
IMM_i : in SDWORD_T;
|
IMM_i : in SDWORD_T;
|
IV_i : in std_logic;
|
IV_i : in std_logic;
|
FSTLL_i : in std_logic;
|
FSTLL_i : in std_logic;
|
BPVD_i : std_logic_vector(3-1 downto 0);
|
BPVD_i : std_logic_vector(3-1 downto 0);
|
MPJRX_i : in std_logic;
|
MPJRX_i : in std_logic;
|
|
|
BJX_o : out std_logic;
|
BJX_o : out std_logic;
|
BJTA_o : out unsigned(ALEN-1 downto 0);
|
BJTA_o : out unsigned(ALEN-1 downto 0);
|
BHT_WE_o : out std_logic;
|
BHT_WE_o : out std_logic;
|
BHT_TA_o : out ADR_T;
|
BHT_TA_o : out ADR_T;
|
BHT_PC_o : out ADR_T;
|
BHT_PC_o : out ADR_T;
|
BHT_CNT_o : out std_logic_vector(2-1 downto 0)
|
BHT_CNT_o : out std_logic_vector(2-1 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_JRPU is
|
component RV01_JRPU is
|
generic(
|
generic(
|
RAS_DEPTH : natural := 4;
|
RAS_DEPTH : natural := 4;
|
JRVQ_DEPTH : natural := 2;
|
JRVQ_DEPTH : natural := 2;
|
PXE : std_logic := '1';
|
PXE : std_logic := '1';
|
NW : natural := 2
|
NW : natural := 2
|
);
|
);
|
port(
|
port(
|
CLK_i : in std_logic;
|
CLK_i : in std_logic;
|
RST_i : in std_logic;
|
RST_i : in std_logic;
|
CLR_i : in std_logic;
|
CLR_i : in std_logic;
|
KLL1_i : in std_logic;
|
KLL1_i : in std_logic;
|
FSTLL_i : in std_logic;
|
FSTLL_i : in std_logic;
|
BJX_i : in std_logic;
|
BJX_i : in std_logic;
|
-- prediction inputs
|
-- prediction inputs
|
INSTR_i : in std_logic_vector(ILEN*2-1 downto 0);
|
INSTR_i : in std_logic_vector(ILEN*2-1 downto 0);
|
IF2_V_i : in std_logic_vector(NW-1 downto 0);
|
IF2_V_i : in std_logic_vector(NW-1 downto 0);
|
IF2_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
|
IF2_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
|
IF2_PC_i : in ADR_VEC_T(NW-1 downto 0);
|
IF2_PC_i : in ADR_VEC_T(NW-1 downto 0);
|
-- verification inputs
|
-- verification inputs
|
IX1_V_i : in std_logic_vector(NW-1 downto 0);
|
IX1_V_i : in std_logic_vector(NW-1 downto 0);
|
IX1_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
|
IX1_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
|
IX1_OPA0_i : SDWORD_T;
|
IX1_OPA0_i : SDWORD_T;
|
IX1_OPA1_i : SDWORD_T;
|
IX1_OPA1_i : SDWORD_T;
|
IX1_PCP4_i : ADR_VEC_T(NW-1 downto 0);
|
IX1_PCP4_i : ADR_VEC_T(NW-1 downto 0);
|
-- RAS management
|
-- RAS management
|
IX3_V_i : in std_logic_vector(NW-1 downto 0);
|
IX3_V_i : in std_logic_vector(NW-1 downto 0);
|
IX3_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
|
IX3_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
|
IX3_PCP4_i : ADR_VEC_T(NW-1 downto 0);
|
IX3_PCP4_i : ADR_VEC_T(NW-1 downto 0);
|
|
|
KLL1_o : out std_logic;
|
KLL1_o : out std_logic;
|
PJRX_o : out std_logic;
|
PJRX_o : out std_logic;
|
PJRTA_o : out ADR_T;
|
PJRTA_o : out ADR_T;
|
MPJRX_o : out std_logic_vector(NW-1 downto 0)
|
MPJRX_o : out std_logic_vector(NW-1 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_PIPE_A_ALU is
|
component RV01_PIPE_A_ALU is
|
port(
|
port(
|
SEL_i : in std_logic_vector(4-1 downto 0);
|
SEL_i : in std_logic_vector(4-1 downto 0);
|
SU_i : in std_logic;
|
SU_i : in std_logic;
|
OP_i : in ALU_OP_T;
|
OP_i : in ALU_OP_T;
|
OPA_i : in SDWORD_T;
|
OPA_i : in SDWORD_T;
|
OPB_i : in SDWORD_T;
|
OPB_i : in SDWORD_T;
|
|
|
RES_o : out SDWORD_T -- result
|
RES_o : out SDWORD_T -- result
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_PIPE_A_RMX_X2 is
|
|
generic(
|
|
NW : natural := 2
|
|
);
|
|
port(
|
|
OPA_V_i : in std_logic;
|
|
OPB_V_i : in std_logic;
|
|
OPA_i : in SDWORD_T;
|
|
OPB_i : in SDWORD_T;
|
|
INSTR_i : in DEC_INSTR_T;
|
|
IX3_V_i : in std_logic_vector(NW-1 downto 0);
|
|
IX3_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
|
|
IX3_RES0_i : in SDWORD_T;
|
|
IX3_RES1_i : in SDWORD_T;
|
|
|
|
OPA_V_o : out std_logic;
|
|
OPB_V_o : out std_logic;
|
|
OPA_o : out SDWORD_T;
|
|
OPB_o : out SDWORD_T
|
|
);
|
|
end component;
|
|
|
|
component RV01_PSTLLOG_2W_P6 is
|
component RV01_PSTLLOG_2W_P6 is
|
generic(
|
generic(
|
DXE : std_logic := '1';
|
DXE : std_logic := '1';
|
SIMULATION_ONLY : std_logic := '0'
|
SIMULATION_ONLY : std_logic := '0'
|
);
|
);
|
port(
|
port(
|
CLK_i : in std_logic;
|
CLK_i : in std_logic;
|
ID_INSTR_i : in DEC_INSTR_T;
|
ID_INSTR_i : in DEC_INSTR_T;
|
ID_V_i : in std_logic;
|
ID_V_i : in std_logic;
|
IX1_INSTR0_i : in DEC_INSTR_T;
|
IX1_INSTR0_i : in DEC_INSTR_T;
|
IX1_INSTR1_i : in DEC_INSTR_T;
|
IX1_INSTR1_i : in DEC_INSTR_T;
|
IX1_V_i : in std_logic_vector(2-1 downto 0);
|
IX1_V_i : in std_logic_vector(2-1 downto 0);
|
IX1_FWDE_i : in std_logic_vector(2-1 downto 0);
|
IX1_FWDE_i : in std_logic_vector(2-1 downto 0);
|
IX2_INSTR0_i : in DEC_INSTR_T;
|
IX2_INSTR0_i : in DEC_INSTR_T;
|
IX2_INSTR1_i : in DEC_INSTR_T;
|
IX2_INSTR1_i : in DEC_INSTR_T;
|
IX2_V_i : in std_logic_vector(2-1 downto 0);
|
IX2_V_i : in std_logic_vector(2-1 downto 0);
|
IX2_FWDE_i : in std_logic_vector(2-1 downto 0);
|
IX2_FWDE_i : in std_logic_vector(2-1 downto 0);
|
IX3_INSTR0_i : in DEC_INSTR_T;
|
IX3_INSTR0_i : in DEC_INSTR_T;
|
IX3_INSTR1_i : in DEC_INSTR_T;
|
IX3_INSTR1_i : in DEC_INSTR_T;
|
IX3_V_i : in std_logic_vector(2-1 downto 0);
|
IX3_V_i : in std_logic_vector(2-1 downto 0);
|
IX3_FWDE_i : in std_logic_vector(2-1 downto 0);
|
IX3_FWDE_i : in std_logic_vector(2-1 downto 0);
|
|
|
OPA_V_o : out std_logic;
|
OPA_V_o : out std_logic;
|
OPB_V_o : out std_logic;
|
OPB_V_o : out std_logic;
|
DSA_o : out std_logic;
|
DSA_o : out std_logic;
|
DSB_o : out std_logic;
|
DSB_o : out std_logic;
|
PSTALL_o : out std_logic
|
PSTALL_o : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_SHFTU is
|
component RV01_SHFTU is
|
port(
|
port(
|
CTRL_i : in SHF_CTRL;
|
CTRL_i : in SHF_CTRL;
|
SI_i : in SDWORD_T;
|
SI_i : in SDWORD_T;
|
SHFT_i : in unsigned(5-1 downto 0);
|
SHFT_i : in unsigned(5-1 downto 0);
|
SU_i : in std_logic;
|
SU_i : in std_logic;
|
|
|
SO_o : out SDWORD_T
|
SO_o : out SDWORD_T
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_CPU_INIT is
|
component RV01_CPU_INIT is
|
port(
|
port(
|
CLK_i : in std_logic;
|
CLK_i : in std_logic;
|
RST_i : in std_logic;
|
RST_i : in std_logic;
|
STRT_i : in std_logic;
|
STRT_i : in std_logic;
|
RSM_i : in std_logic;
|
RSM_i : in std_logic;
|
BHT_INIT_END_i : in std_logic;
|
BHT_INIT_END_i : in std_logic;
|
|
|
INIT_STRT_o : out std_logic;
|
INIT_STRT_o : out std_logic;
|
STRT_o : out std_logic
|
STRT_o : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_DIMSLOG is
|
component RV01_DIMSLOG is
|
generic(
|
generic(
|
IMEM_LOWM : std_logic := '1';
|
IMEM_LOWM : std_logic := '1';
|
IMEM_SIZE : natural := 1024*32;
|
IMEM_SIZE : natural := 1024*32;
|
DMEM_SIZE : natural := 1024*16
|
DMEM_SIZE : natural := 1024*16
|
);
|
);
|
port(
|
port(
|
IX1_OPA0_i : in SDWORD_T;
|
IX1_OPA0_i : in SDWORD_T;
|
IX1_OPA1_i : in SDWORD_T;
|
IX1_OPA1_i : in SDWORD_T;
|
IX1_IMM0_i : in SDWORD_T;
|
IX1_IMM0_i : in SDWORD_T;
|
IX1_IMM1_i : in SDWORD_T;
|
IX1_IMM1_i : in SDWORD_T;
|
IX1_DADR0_i : in ADR_T;
|
IX1_DADR0_i : in ADR_T;
|
IX1_DADR1_i : in ADR_T;
|
IX1_DADR1_i : in ADR_T;
|
IX3_DADR0_i : in ADR_T;
|
IX3_DADR0_i : in ADR_T;
|
|
|
IX1_DIMS_o : out std_logic_vector(NW-1 downto 0);
|
IX1_DIMS_o : out std_logic_vector(NW-1 downto 0);
|
IX3_DIMS_o : out std_logic
|
IX3_DIMS_o : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_DBGU is
|
component RV01_DBGU is
|
generic(
|
generic(
|
NW : natural := 2
|
NW : natural := 2
|
);
|
);
|
port(
|
port(
|
CLK_i : in std_logic;
|
CLK_i : in std_logic;
|
RST_i : in std_logic;
|
RST_i : in std_logic;
|
HPC_i : in ADR_T;
|
HPC_i : in ADR_T;
|
MMODE_i : in std_logic;
|
MMODE_i : in std_logic;
|
NOPR_i : in std_logic;
|
NOPR_i : in std_logic;
|
-- Debug interface
|
-- Debug interface
|
HALT_i : in std_logic;
|
HALT_i : in std_logic;
|
-- Control port
|
-- Control port
|
CPRE_i : in std_logic;
|
CPRE_i : in std_logic;
|
CPWE_i : in std_logic;
|
CPWE_i : in std_logic;
|
CPADR_i : in std_logic_vector(17-1 downto 0);
|
CPADR_i : in std_logic_vector(17-1 downto 0);
|
CPD_i : in std_logic_vector(SDLEN-1 downto 0);
|
CPD_i : in std_logic_vector(SDLEN-1 downto 0);
|
|
|
RST_o : out std_logic;
|
RST_o : out std_logic;
|
HLTRQ_o : out std_logic;
|
HLTRQ_o : out std_logic;
|
RSM_o : out std_logic;
|
RSM_o : out std_logic;
|
DPC_o : out ADR_T;
|
DPC_o : out ADR_T;
|
DMODE_o : out std_logic;
|
DMODE_o : out std_logic;
|
DIE_o : out std_logic;
|
DIE_o : out std_logic;
|
HALTD_o : out std_logic;
|
HALTD_o : out std_logic;
|
STOPTIME_o : out std_logic;
|
STOPTIME_o : out std_logic;
|
STOPCYCLE_o : out std_logic;
|
STOPCYCLE_o : out std_logic;
|
SI_o : out std_logic_vector(SDLEN-1 downto 0);
|
SI_o : out std_logic_vector(SDLEN-1 downto 0);
|
HOBRK_o : out std_logic;
|
HOBRK_o : out std_logic;
|
STEP_o : out std_logic;
|
STEP_o : out std_logic;
|
FRCSI_o : out std_logic;
|
FRCSI_o : out std_logic;
|
-- Control port
|
-- Control port
|
CPQ_o : out std_logic_vector(SDLEN-1 downto 0)
|
CPQ_o : out std_logic_vector(SDLEN-1 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_HLTU is
|
component RV01_HLTU is
|
generic(
|
generic(
|
PXE : std_logic := '1';
|
PXE : std_logic := '1';
|
NW : natural := 2
|
NW : natural := 2
|
);
|
);
|
port(
|
port(
|
CLK_i : in std_logic;
|
CLK_i : in std_logic;
|
RST_i : in std_logic;
|
RST_i : in std_logic;
|
IX1_V_i : in std_logic_vector(NW-1 downto 0);
|
IX1_V_i : in std_logic_vector(NW-1 downto 0);
|
IX2_V_i : in std_logic_vector(NW-1 downto 0);
|
IX2_V_i : in std_logic_vector(NW-1 downto 0);
|
NOPR_i : in std_logic; -- no pending read (in sbuf) flag
|
NOPR_i : in std_logic; -- no pending read (in sbuf) flag
|
MMODE_i : in std_logic; -- machine mode flag
|
MMODE_i : in std_logic; -- machine mode flag
|
HALT_i : in std_logic; -- halt flag
|
HALT_i : in std_logic; -- halt flag
|
HPC_i : in ADR_T; -- halt PC
|
HPC_i : in ADR_T; -- halt PC
|
-- CSR interface
|
-- CSR interface
|
CS_OP_i : in CS_OP_T;
|
CS_OP_i : in CS_OP_T;
|
RS1_i : in RID_T;
|
RS1_i : in RID_T;
|
ADR_i : in signed(12-1 downto 0);
|
ADR_i : in signed(12-1 downto 0);
|
WE_i : in std_logic;
|
WE_i : in std_logic;
|
CSRD_i : in SDWORD_T;
|
CSRD_i : in SDWORD_T;
|
-- Control port
|
-- Control port
|
CPRE_i : in std_logic;
|
CPRE_i : in std_logic;
|
CPWE_i : in std_logic;
|
CPWE_i : in std_logic;
|
CPADR_i : in std_logic_vector(17-1 downto 0);
|
CPADR_i : in std_logic_vector(17-1 downto 0);
|
CPD_i : in std_logic_vector(SDLEN-1 downto 0);
|
CPD_i : in std_logic_vector(SDLEN-1 downto 0);
|
|
|
HMODE_o : out std_logic; -- halt mode flag
|
HMODE_o : out std_logic; -- halt mode flag
|
STRT_o : out std_logic; -- start flag
|
STRT_o : out std_logic; -- start flag
|
STRTPC_o : out ADR_T; -- start PC
|
STRTPC_o : out ADR_T; -- start PC
|
RSM_o : out std_logic; -- resume flag
|
RSM_o : out std_logic; -- resume flag
|
HLTURQ_o : out std_logic; -- halt request flag
|
HLTURQ_o : out std_logic; -- halt request flag
|
HLTOBRK_o : out std_logic; -- halt-on-break enable
|
HLTOBRK_o : out std_logic; -- halt-on-break enable
|
HLTOADR_o : out std_logic_vector(NW-1 downto 0); -- halt-on-address enable
|
HLTOADR_o : out std_logic_vector(NW-1 downto 0); -- halt-on-address enable
|
HLTADR_o : out ADR_T; -- halt address
|
HLTADR_o : out ADR_T; -- halt address
|
-- CSR interface
|
-- CSR interface
|
CSRQ_o : out SDWORD_T;
|
CSRQ_o : out SDWORD_T;
|
HCSR_o : out std_logic;
|
HCSR_o : out std_logic;
|
ILLG_o : out std_logic;
|
ILLG_o : out std_logic;
|
-- Control port
|
-- Control port
|
HCP_o : out std_logic;
|
HCP_o : out std_logic;
|
CPQ_o : out std_logic_vector(SDLEN-1 downto 0)
|
CPQ_o : out std_logic_vector(SDLEN-1 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_RESMUX_IX1 is
|
component RV01_RESMUX_IX1 is
|
generic(
|
generic(
|
PXE : std_logic := '1';
|
PXE : std_logic := '1';
|
DXE : std_logic := '1';
|
DXE : std_logic := '1';
|
NW : natural := 2
|
NW : natural := 2
|
);
|
);
|
port(
|
port(
|
OPA0_V_i : in std_logic;
|
OPA0_V_i : in std_logic;
|
OPA1_V_i : in std_logic;
|
OPA1_V_i : in std_logic;
|
OPA0_i : in SDWORD_T;
|
OPA0_i : in SDWORD_T;
|
OPA1_i : in SDWORD_T;
|
OPA1_i : in SDWORD_T;
|
OPB0_V_i : in std_logic;
|
OPB0_V_i : in std_logic;
|
OPB1_V_i : in std_logic;
|
OPB1_V_i : in std_logic;
|
OPB0_i : in SDWORD_T;
|
OPB0_i : in SDWORD_T;
|
OPB1_i : in SDWORD_T;
|
OPB1_i : in SDWORD_T;
|
SHF_RES0_i : in SDWORD_T;
|
SHF_RES0_i : in SDWORD_T;
|
SHF_RES1_i : in SDWORD_T;
|
SHF_RES1_i : in SDWORD_T;
|
PA0_ALU_RES_i : in SDWORD_T;
|
PA0_ALU_RES_i : in SDWORD_T;
|
PA1_ALU_RES_i : in SDWORD_T;
|
PA1_ALU_RES_i : in SDWORD_T;
|
DIV_V_i : in std_logic;
|
DIV_V_i : in std_logic;
|
DIV_RES_i : in SDWORD_T;
|
DIV_RES_i : in SDWORD_T;
|
PASEL0_i : in std_logic_vector(4-1 downto 0);
|
PASEL0_i : in std_logic_vector(4-1 downto 0);
|
PASEL1_i : in std_logic_vector(4-1 downto 0);
|
PASEL1_i : in std_logic_vector(4-1 downto 0);
|
FWDE_i : in std_logic_vector(NW-1 downto 0);
|
FWDE_i : in std_logic_vector(NW-1 downto 0);
|
DSA0_i : in std_logic;
|
DSA0_i : in std_logic;
|
DSB0_i : in std_logic;
|
DSB0_i : in std_logic;
|
DSA1_i : in std_logic;
|
DSA1_i : in std_logic;
|
DSB1_i : in std_logic;
|
DSB1_i : in std_logic;
|
INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
|
INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
|
IX3_DRD0_i : in SDWORD_T;
|
IX3_DRD0_i : in SDWORD_T;
|
IX3_DRD1_i : in SDWORD_T;
|
IX3_DRD1_i : in SDWORD_T;
|
IX3_V_i : in std_logic_vector(NW-1 downto 0);
|
IX3_V_i : in std_logic_vector(NW-1 downto 0);
|
IX3_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
|
IX3_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
|
|
|
FWDX_o : out std_logic_vector(NW-1 downto 0);
|
FWDX_o : out std_logic_vector(NW-1 downto 0);
|
PA0_RES_o : out SDWORD_T;
|
PA0_RES_o : out SDWORD_T;
|
PA1_RES_o : out SDWORD_T;
|
PA1_RES_o : out SDWORD_T;
|
OPA0_V_o : out std_logic;
|
OPA0_V_o : out std_logic;
|
OPA1_V_o : out std_logic;
|
OPA1_V_o : out std_logic;
|
OPA0_o : out SDWORD_T;
|
OPA0_o : out SDWORD_T;
|
OPA1_o : out SDWORD_T;
|
OPA1_o : out SDWORD_T;
|
OPB0_V_o : out std_logic;
|
OPB0_V_o : out std_logic;
|
OPB1_V_o : out std_logic;
|
OPB1_V_o : out std_logic;
|
OPB0_o : out SDWORD_T;
|
OPB0_o : out SDWORD_T;
|
OPB1_o : out SDWORD_T;
|
OPB1_o : out SDWORD_T;
|
DRD0_V_o : out std_logic;
|
DRD0_V_o : out std_logic;
|
DRD1_V_o : out std_logic;
|
DRD1_V_o : out std_logic;
|
DRD0_o : out SDWORD_T;
|
DRD0_o : out SDWORD_T;
|
DRD1_o : out SDWORD_T
|
DRD1_o : out SDWORD_T
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_RESMUX_IX2 is
|
component RV01_RESMUX_IX2 is
|
generic(
|
generic(
|
PXE : std_logic := '1';
|
PXE : std_logic := '1';
|
DXE : std_logic := '1';
|
DXE : std_logic := '1';
|
NW : natural := 2
|
NW : natural := 2
|
);
|
);
|
port(
|
port(
|
OPA0_V_i : in std_logic;
|
OPA0_V_i : in std_logic;
|
OPA1_V_i : in std_logic;
|
OPA1_V_i : in std_logic;
|
OPA0_i : in SDWORD_T;
|
OPA0_i : in SDWORD_T;
|
OPA1_i : in SDWORD_T;
|
OPA1_i : in SDWORD_T;
|
OPB0_V_i : in std_logic;
|
OPB0_V_i : in std_logic;
|
OPB1_V_i : in std_logic;
|
OPB1_V_i : in std_logic;
|
OPB0_i : in SDWORD_T;
|
OPB0_i : in SDWORD_T;
|
OPB1_i : in SDWORD_T;
|
OPB1_i : in SDWORD_T;
|
DRD0_V_i : in std_logic;
|
DRD0_V_i : in std_logic;
|
DRD1_V_i : in std_logic;
|
DRD1_V_i : in std_logic;
|
DRD0_i : in SDWORD_T;
|
DRD0_i : in SDWORD_T;
|
DRD1_i : in SDWORD_T;
|
DRD1_i : in SDWORD_T;
|
DDAT0_i : in std_logic_vector(SDLEN-1 downto 0);
|
DDAT0_i : in std_logic_vector(SDLEN-1 downto 0);
|
DDAT1_i : in std_logic_vector(SDLEN-1 downto 0);
|
DDAT1_i : in std_logic_vector(SDLEN-1 downto 0);
|
PA0_ALU_RES_i : in SDWORD_T;
|
PA0_ALU_RES_i : in SDWORD_T;
|
PA1_ALU_RES_i : in SDWORD_T;
|
PA1_ALU_RES_i : in SDWORD_T;
|
PB0_RES_i : in SDWORD_T;
|
PB0_RES_i : in SDWORD_T;
|
PC1P4_i : in unsigned(SDLEN-1 downto 0);
|
PC1P4_i : in unsigned(SDLEN-1 downto 0);
|
PASEL0_i : in std_logic_vector(4-1 downto 0);
|
PASEL0_i : in std_logic_vector(4-1 downto 0);
|
PASEL1_i : in std_logic_vector(4-1 downto 0);
|
PASEL1_i : in std_logic_vector(4-1 downto 0);
|
FWDE_i : in std_logic_vector(NW-1 downto 0);
|
FWDE_i : in std_logic_vector(NW-1 downto 0);
|
INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
|
INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
|
IX3_DRD0_i : in SDWORD_T;
|
IX3_DRD0_i : in SDWORD_T;
|
IX3_DRD1_i : in SDWORD_T;
|
IX3_DRD1_i : in SDWORD_T;
|
IX3_V_i : in std_logic_vector(NW-1 downto 0);
|
IX3_V_i : in std_logic_vector(NW-1 downto 0);
|
IX3_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
|
IX3_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
|
|
|
FWDX_o : out std_logic_vector(NW-1 downto 0);
|
FWDX_o : out std_logic_vector(NW-1 downto 0);
|
PA0_RES_o : out SDWORD_T;
|
PA0_RES_o : out SDWORD_T;
|
PA1_RES_o : out SDWORD_T;
|
PA1_RES_o : out SDWORD_T;
|
OPA0_V_o : out std_logic;
|
OPA0_V_o : out std_logic;
|
OPA1_V_o : out std_logic;
|
OPA1_V_o : out std_logic;
|
OPA0_o : out SDWORD_T;
|
OPA0_o : out SDWORD_T;
|
OPA1_o : out SDWORD_T;
|
OPA1_o : out SDWORD_T;
|
OPB0_V_o : out std_logic;
|
OPB0_V_o : out std_logic;
|
OPB1_V_o : out std_logic;
|
OPB1_V_o : out std_logic;
|
OPB0_o : out SDWORD_T;
|
OPB0_o : out SDWORD_T;
|
OPB1_o : out SDWORD_T;
|
OPB1_o : out SDWORD_T;
|
DRD0_o : out SDWORD_T;
|
DRD0_o : out SDWORD_T;
|
DRD1_o : out SDWORD_T
|
DRD1_o : out SDWORD_T
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_RESMUX_IX3 is
|
component RV01_RESMUX_IX3 is
|
generic(
|
generic(
|
PXE : std_logic := '1';
|
PXE : std_logic := '1';
|
DXE : std_logic := '1';
|
DXE : std_logic := '1';
|
NW : natural := 2
|
NW : natural := 2
|
);
|
);
|
port(
|
port(
|
DRD0_i : in SDWORD_T;
|
DRD0_i : in SDWORD_T;
|
DRD1_i : in SDWORD_T;
|
DRD1_i : in SDWORD_T;
|
PA0_ALU_RES_i : in SDWORD_T;
|
PA0_ALU_RES_i : in SDWORD_T;
|
PA1_ALU_RES_i : in SDWORD_T;
|
PA1_ALU_RES_i : in SDWORD_T;
|
LDAT0_i : in SDWORD_T;
|
LDAT0_i : in SDWORD_T;
|
LDAT1_i : in SDWORD_T;
|
LDAT1_i : in SDWORD_T;
|
LDAT_V_i : in std_logic_vector(NW-1 downto 0);
|
LDAT_V_i : in std_logic_vector(NW-1 downto 0);
|
PASEL0_i : in std_logic_vector(4-1 downto 0);
|
PASEL0_i : in std_logic_vector(4-1 downto 0);
|
PASEL1_i : in std_logic_vector(4-1 downto 0);
|
PASEL1_i : in std_logic_vector(4-1 downto 0);
|
FWDE_i : in std_logic_vector(NW-1 downto 0);
|
FWDE_i : in std_logic_vector(NW-1 downto 0);
|
RES_SRC0_i : in RES_SRC_T;
|
RES_SRC0_i : in RES_SRC_T;
|
CSRU_RES_i : in SDWORD_T;
|
CSRU_RES_i : in SDWORD_T;
|
|
|
DRD0_o : out SDWORD_T;
|
DRD0_o : out SDWORD_T;
|
DRD1_o : out SDWORD_T
|
DRD1_o : out SDWORD_T
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_CDCOMUX is
|
component RV01_CDCOMUX is
|
generic(
|
generic(
|
DMP : std_logic := '0'
|
DMP : std_logic := '0'
|
);
|
);
|
port(
|
port(
|
CLK_i : in std_logic;
|
CLK_i : in std_logic;
|
HCSR_i : in std_logic;
|
HCSR_i : in std_logic;
|
HCSRQ_i : in SDWORD_T;
|
HCSRQ_i : in SDWORD_T;
|
CSRQ_i : in SDWORD_T;
|
CSRQ_i : in SDWORD_T;
|
HILLG_i : in std_logic;
|
HILLG_i : in std_logic;
|
ILLG_i : in std_logic;
|
ILLG_i : in std_logic;
|
CP_ADR_MSB_i : in std_logic;
|
CP_ADR_MSB_i : in std_logic;
|
HCP_i : in std_logic;
|
HCP_i : in std_logic;
|
HCPQ_i : in std_logic_vector(SDLEN-1 downto 0);
|
HCPQ_i : in std_logic_vector(SDLEN-1 downto 0);
|
CPQ_i : in std_logic_vector(SDLEN-1 downto 0);
|
CPQ_i : in std_logic_vector(SDLEN-1 downto 0);
|
DCPQ_i : in std_logic_vector(SDLEN-1 downto 0);
|
DCPQ_i : in std_logic_vector(SDLEN-1 downto 0);
|
STRT_i : in std_logic;
|
STRT_i : in std_logic;
|
DRSM_i : in std_logic;
|
DRSM_i : in std_logic;
|
DPC_i : in ADR_T;
|
DPC_i : in ADR_T;
|
STRTPC_i : in ADR_T;
|
STRTPC_i : in ADR_T;
|
|
|
ILLG_o : out std_logic;
|
ILLG_o : out std_logic;
|
CSRU_RES_o : out SDWORD_T;
|
CSRU_RES_o : out SDWORD_T;
|
CP_Q_o : out std_logic_vector(SDLEN-1 downto 0);
|
CP_Q_o : out std_logic_vector(SDLEN-1 downto 0);
|
STRT_o : out std_logic;
|
STRT_o : out std_logic;
|
STRTPC_o : out ADR_T
|
STRTPC_o : out ADR_T
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_MISCLOG_IX3 is
|
component RV01_MISCLOG_IX3 is
|
generic(
|
generic(
|
PXE : std_logic := '0';
|
PXE : std_logic := '0';
|
NW : natural := 2
|
NW : natural := 2
|
);
|
);
|
port(
|
port(
|
IX1_V0_i : in std_logic;
|
IX1_V0_i : in std_logic;
|
IX1_WCSR0_i : in std_logic;
|
IX1_WCSR0_i : in std_logic;
|
V_i : in std_logic_vector(NW-1 downto 0);
|
V_i : in std_logic_vector(NW-1 downto 0);
|
DWE_i : in std_logic_vector(NW-1 downto 0);
|
DWE_i : in std_logic_vector(NW-1 downto 0);
|
KPRD_i : in std_logic_vector(NW-1 downto 0);
|
KPRD_i : in std_logic_vector(NW-1 downto 0);
|
WRD0_i : in std_logic;
|
WRD0_i : in std_logic;
|
WRD1_i : in std_logic;
|
WRD1_i : in std_logic;
|
HALT_i : in std_logic_vector(NW-1 downto 0);
|
HALT_i : in std_logic_vector(NW-1 downto 0);
|
CLRP_i : in std_logic;
|
CLRP_i : in std_logic;
|
CLRD_i : in std_logic;
|
CLRD_i : in std_logic;
|
HIS_i : in std_logic;
|
HIS_i : in std_logic;
|
PC0_i : in ADR_T;
|
PC0_i : in ADR_T;
|
PC1_i : in ADR_T;
|
PC1_i : in ADR_T;
|
|
|
CP_WE_o : out std_logic;
|
CP_WE_o : out std_logic;
|
SBRE_o : out std_logic_vector(NW-1 downto 0);
|
SBRE_o : out std_logic_vector(NW-1 downto 0);
|
STL_o : out std_logic_vector(NW-1 downto 0);
|
STL_o : out std_logic_vector(NW-1 downto 0);
|
WE_o : out std_logic_vector(NW-1 downto 0);
|
WE_o : out std_logic_vector(NW-1 downto 0);
|
HALT_o : out std_logic;
|
HALT_o : out std_logic;
|
CLRP_o : out std_logic;
|
CLRP_o : out std_logic;
|
CLRD_o : out std_logic;
|
CLRD_o : out std_logic;
|
HPC_o : out ADR_T
|
HPC_o : out ADR_T
|
);
|
);
|
end component;
|
end component;
|
|
|
signal ZERO : std_logic := '0';
|
signal ZERO : std_logic := '0';
|
signal ONE : std_logic := '1';
|
signal ONE : std_logic := '1';
|
|
|
signal INIT_STRT : std_logic;
|
signal INIT_STRT : std_logic;
|
signal BHT_INIT_END : std_logic;
|
signal BHT_INIT_END : std_logic;
|
signal STRT : std_logic;
|
signal STRT : std_logic;
|
signal IRST : std_logic;
|
signal IRST : std_logic;
|
|
|
signal IF1_V,IF1_V_q : std_logic_vector(NW-1 downto 0);
|
signal IF1_V,IF1_V_q : std_logic_vector(NW-1 downto 0);
|
signal IF2_V_q : std_logic_vector(NW-1 downto 0);
|
signal IF2_V_q : std_logic_vector(NW-1 downto 0);
|
signal IF1_PC : ADR_VEC_T(NW-1 downto 0);
|
signal IF1_PC : ADR_VEC_T(NW-1 downto 0);
|
signal IF1_PC_q : ADR_VEC_T(NW-1 downto 0);
|
signal IF1_PC_q : ADR_VEC_T(NW-1 downto 0);
|
signal IF1_IADR_MIS : std_logic;
|
signal IF1_IADR_MIS : std_logic;
|
signal IF1_IADR_MIS_q : std_logic_vector(NW-1 downto 0);
|
signal IF1_IADR_MIS_q : std_logic_vector(NW-1 downto 0);
|
|
|
signal IF2_DEC_INSTR : DEC_INSTR_VEC_T(NW-1 downto 0);
|
signal IF2_DEC_INSTR : DEC_INSTR_VEC_T(NW-1 downto 0);
|
signal IF2_DEC_INSTR_q : DEC_INSTR_VEC_T(NW-1 downto 0);
|
signal IF2_DEC_INSTR_q : DEC_INSTR_VEC_T(NW-1 downto 0);
|
signal IF2_OPA_PC : std_logic_vector(NW-1 downto 0);
|
signal IF2_OPA_PC : std_logic_vector(NW-1 downto 0);
|
signal IF2_OPA_PC_q : std_logic_vector(NW-1 downto 0);
|
signal IF2_OPA_PC_q : std_logic_vector(NW-1 downto 0);
|
signal IF2_OPB_IMM : std_logic_vector(NW-1 downto 0);
|
signal IF2_OPB_IMM : std_logic_vector(NW-1 downto 0);
|
signal IF2_OPB_IMM_q : std_logic_vector(NW-1 downto 0);
|
signal IF2_OPB_IMM_q : std_logic_vector(NW-1 downto 0);
|
signal IF2_PC_q : ADR_VEC_T(NW-1 downto 0);
|
signal IF2_PC_q : ADR_VEC_T(NW-1 downto 0);
|
signal IF2_INSTR0,IF2_INSTR1 : std_logic_vector(ILEN-1 downto 0);
|
signal IF2_INSTR0,IF2_INSTR1 : std_logic_vector(ILEN-1 downto 0);
|
signal IF2_V : std_logic_vector(NW-1 downto 0);
|
signal IF2_V : std_logic_vector(NW-1 downto 0);
|
signal IF2_KLL1 : std_logic;
|
signal IF2_KLL1 : std_logic;
|
signal IF2_V_KILL : std_logic;
|
signal IF2_V_KILL : std_logic;
|
signal IF2_PBX : std_logic;
|
signal IF2_PBX : std_logic;
|
signal IF2_PBTA : ADR_T;
|
signal IF2_PBTA : ADR_T;
|
signal IF2_BPVD0 : std_logic_vector(3-1 downto 0);
|
signal IF2_BPVD0 : std_logic_vector(3-1 downto 0);
|
signal IF2_BPVD1 : std_logic_vector(3-1 downto 0);
|
signal IF2_BPVD1 : std_logic_vector(3-1 downto 0);
|
signal IF2_BPVD0_q : std_logic_vector(3-1 downto 0);
|
signal IF2_BPVD0_q : std_logic_vector(3-1 downto 0);
|
signal IF2_BPVD1_q : std_logic_vector(3-1 downto 0);
|
signal IF2_BPVD1_q : std_logic_vector(3-1 downto 0);
|
signal IF2_JRKLL1 : std_logic;
|
signal IF2_JRKLL1 : std_logic;
|
signal IF2_PJRX : std_logic;
|
signal IF2_PJRX : std_logic;
|
signal IF2_PJRTA : ADR_T;
|
signal IF2_PJRTA : ADR_T;
|
|
|
signal ID_INSTR0,ID_INSTR1 : DEC_INSTR_T;
|
signal ID_INSTR0,ID_INSTR1 : DEC_INSTR_T;
|
signal ID_INSTR_q : DEC_INSTR_VEC_T(NW-1 downto 0);
|
signal ID_INSTR_q : DEC_INSTR_VEC_T(NW-1 downto 0);
|
signal ID_V,ID_V_q : std_logic_vector(NW-1 downto 0);
|
signal ID_V,ID_V_q : std_logic_vector(NW-1 downto 0);
|
signal ID_ISSUE : std_logic_vector(NW-1 downto 0);
|
signal ID_ISSUE : std_logic_vector(NW-1 downto 0);
|
signal ID_PC_q : ADR_VEC_T(NW-1 downto 0);
|
signal ID_PC_q : ADR_VEC_T(NW-1 downto 0);
|
signal ID_OPA0,ID_OPA0_q : SDWORD_T;
|
signal ID_OPA0,ID_OPA0_q : SDWORD_T;
|
signal ID_OPB0,ID_OPB0_q : SDWORD_T;
|
signal ID_OPB0,ID_OPB0_q : SDWORD_T;
|
signal ID_OPA1,ID_OPA1_q : SDWORD_T;
|
signal ID_OPA1,ID_OPA1_q : SDWORD_T;
|
signal ID_OPB1,ID_OPB1_q : SDWORD_T;
|
signal ID_OPB1,ID_OPB1_q : SDWORD_T;
|
signal ID_PSTALL : std_logic;
|
signal ID_PSTALL : std_logic;
|
signal ID_PS : std_logic_vector(NW-1 downto 0);
|
signal ID_PS : std_logic_vector(NW-1 downto 0);
|
signal ID_PXE1 : std_logic;
|
signal ID_PXE1 : std_logic;
|
signal ID_JLRA : ADR_VEC_T(NW-1 downto 0);
|
signal ID_JLRA : ADR_VEC_T(NW-1 downto 0);
|
signal ID_FWDE : std_logic_vector(NW-1 downto 0);
|
signal ID_FWDE : std_logic_vector(NW-1 downto 0);
|
signal ID_FWDE_q : std_logic_vector(NW-1 downto 0);
|
signal ID_FWDE_q : std_logic_vector(NW-1 downto 0);
|
signal ID_FWDX_q : std_logic_vector(NW-1 downto 0);
|
signal ID_FWDX_q : std_logic_vector(NW-1 downto 0);
|
signal ID_PASEL0,ID_PASEL1 : std_logic_vector(4-1 downto 0);
|
signal ID_PASEL0,ID_PASEL1 : std_logic_vector(4-1 downto 0);
|
signal ID_PASEL0_q,ID_PASEL1_q : std_logic_vector(4-1 downto 0);
|
signal ID_PASEL0_q,ID_PASEL1_q : std_logic_vector(4-1 downto 0);
|
signal ID_OPA_PC_q : std_logic_vector(NW-1 downto 0);
|
signal ID_OPA_PC_q : std_logic_vector(NW-1 downto 0);
|
signal ID_DIV_BSY : std_logic;
|
signal ID_DIV_BSY : std_logic;
|
signal ID_BPVD0_q : std_logic_vector(3-1 downto 0);
|
signal ID_BPVD0_q : std_logic_vector(3-1 downto 0);
|
signal ID_BPVD1_q : std_logic_vector(3-1 downto 0);
|
signal ID_BPVD1_q : std_logic_vector(3-1 downto 0);
|
signal ID_OPA0_V : std_logic;
|
signal ID_OPA0_V : std_logic;
|
signal ID_OPB0_V : std_logic;
|
signal ID_OPB0_V : std_logic;
|
signal ID_OPA1_V : std_logic;
|
signal ID_OPA1_V : std_logic;
|
signal ID_OPB1_V : std_logic;
|
signal ID_OPB1_V : std_logic;
|
signal ID_OPA0_V_q : std_logic;
|
signal ID_OPA0_V_q : std_logic;
|
signal ID_OPB0_V_q : std_logic;
|
signal ID_OPB0_V_q : std_logic;
|
signal ID_OPA1_V_q : std_logic;
|
signal ID_OPA1_V_q : std_logic;
|
signal ID_OPB1_V_q : std_logic;
|
signal ID_OPB1_V_q : std_logic;
|
signal ID_DSA0,ID_DSA0_q : std_logic;
|
signal ID_DSA0,ID_DSA0_q : std_logic;
|
signal ID_DSB0,ID_DSB0_q : std_logic;
|
signal ID_DSB0,ID_DSB0_q : std_logic;
|
signal ID_DSA1,ID_DSA1_q : std_logic;
|
signal ID_DSA1,ID_DSA1_q : std_logic;
|
signal ID_DSB1,ID_DSB1_q : std_logic;
|
signal ID_DSB1,ID_DSB1_q : std_logic;
|
|
|
signal IX1_INSTR : DEC_INSTR_VEC_T(NW-1 downto 0);
|
signal IX1_INSTR : DEC_INSTR_VEC_T(NW-1 downto 0);
|
signal IX1_INSTR_q : DEC_INSTR_VEC_T(NW-1 downto 0);
|
signal IX1_INSTR_q : DEC_INSTR_VEC_T(NW-1 downto 0);
|
signal IX1_SRST : std_logic;
|
signal IX1_SRST : std_logic;
|
signal IX1_BJX : std_logic;
|
signal IX1_BJX : std_logic;
|
signal IX1_BJTA : ADR_T;
|
signal IX1_BJTA : ADR_T;
|
signal IX1_BJX0 : std_logic;
|
signal IX1_BJX0 : std_logic;
|
signal IX1_BJTA0 : ADR_T;
|
signal IX1_BJTA0 : ADR_T;
|
signal IX1_BJX1 : std_logic;
|
signal IX1_BJX1 : std_logic;
|
signal IX1_BJTA1 : ADR_T;
|
signal IX1_BJTA1 : ADR_T;
|
signal IX1_BJX0_q : std_logic;
|
signal IX1_BJX0_q : std_logic;
|
signal IX1_BJTA0_q : ADR_T;
|
signal IX1_BJTA0_q : ADR_T;
|
signal IX1_BJX1_q : std_logic;
|
signal IX1_BJX1_q : std_logic;
|
signal IX1_BJTA1_q : ADR_T;
|
signal IX1_BJTA1_q : ADR_T;
|
signal IX1_DWE : std_logic_vector(NW-1 downto 0);
|
signal IX1_DWE : std_logic_vector(NW-1 downto 0);
|
signal IX1_PDWE : std_logic_vector(NW-1 downto 0);
|
signal IX1_PDWE : std_logic_vector(NW-1 downto 0);
|
signal IX1_DDATO0,IX1_DDATO1 : std_logic_vector(SDLEN-1 downto 0);
|
signal IX1_DDATO0,IX1_DDATO1 : std_logic_vector(SDLEN-1 downto 0);
|
signal IX1_DADR0,IX1_DADR1 : ADR_T;
|
signal IX1_DADR0,IX1_DADR1 : ADR_T;
|
signal IX1_DADR0_q,IX1_DADR1_q : ADR_T;
|
signal IX1_DADR0_q,IX1_DADR1_q : ADR_T;
|
signal IX1_V,IX1_V_q : std_logic_vector(NW-1 downto 0);
|
signal IX1_V,IX1_V_q : std_logic_vector(NW-1 downto 0);
|
signal IX1_FWDE_q : std_logic_vector(NW-1 downto 0);
|
signal IX1_FWDE_q : std_logic_vector(NW-1 downto 0);
|
signal IX1_FWDX_q : std_logic_vector(NW-1 downto 0);
|
signal IX1_FWDX_q : std_logic_vector(NW-1 downto 0);
|
signal IX1_PA0_RES : SDWORD_T;
|
signal IX1_PA0_RES : SDWORD_T;
|
signal IX1_PA1_RES : SDWORD_T;
|
signal IX1_PA1_RES : SDWORD_T;
|
signal IX1_DBE0,IX1_DBE1 : std_logic_vector(4-1 downto 0);
|
signal IX1_DBE0,IX1_DBE1 : std_logic_vector(4-1 downto 0);
|
signal IX1_PC0_q,IX1_PC1_q : ADR_T;
|
signal IX1_PC0_q,IX1_PC1_q : ADR_T;
|
signal IX1_S2LAC : std_logic_vector(2-1 downto 0);
|
signal IX1_S2LAC : std_logic_vector(2-1 downto 0);
|
signal IX1_DIV_STRT,IX1_DIV_QS : std_logic;
|
signal IX1_DIV_STRT,IX1_DIV_QS : std_logic;
|
signal IX1_PC0P4,IX1_PC0P4_q : ADR_T;
|
signal IX1_PC0P4,IX1_PC0P4_q : ADR_T;
|
signal IX1_PC1P4,IX1_PC1P4_q : ADR_T;
|
signal IX1_PC1P4,IX1_PC1P4_q : ADR_T;
|
signal IX1_MALGN : std_logic_vector(NW-1 downto 0);
|
signal IX1_MALGN : std_logic_vector(NW-1 downto 0);
|
signal IX1_SBF : std_logic;
|
signal IX1_SBF : std_logic;
|
signal IX1_DWE_q : std_logic_vector(2-1 downto 0);
|
signal IX1_DWE_q : std_logic_vector(2-1 downto 0);
|
signal IX1_DIV_RES : SDWORD_T;
|
signal IX1_DIV_RES : SDWORD_T;
|
signal IX1_DIV_V : std_logic;
|
signal IX1_DIV_V : std_logic;
|
signal IX1_DIV_CLRV : std_logic;
|
signal IX1_DIV_CLRV : std_logic;
|
signal IX1_DRD0,IX1_DRD1 : SDWORD_T;
|
signal IX1_DRD0,IX1_DRD1 : SDWORD_T;
|
signal IX1_DRD0_q,IX1_DRD1_q : SDWORD_T;
|
signal IX1_DRD0_q,IX1_DRD1_q : SDWORD_T;
|
signal IX1_DRD0_V,IX1_DRD1_V : std_logic;
|
signal IX1_DRD0_V,IX1_DRD1_V : std_logic;
|
signal IX1_DRD0_V_q,IX1_DRD1_V_q : std_logic;
|
signal IX1_DRD0_V_q,IX1_DRD1_V_q : std_logic;
|
signal IX1_NOPR : std_logic;
|
signal IX1_NOPR : std_logic;
|
signal IX1_CP_WE : std_logic;
|
signal IX1_CP_WE : std_logic;
|
signal IX1_BHT_TA : ADR_VEC_T(NW-1 downto 0);
|
signal IX1_BHT_TA : ADR_VEC_T(NW-1 downto 0);
|
signal IX1_BHT_CNT0 : std_logic_vector(2-1 downto 0);
|
signal IX1_BHT_CNT0 : std_logic_vector(2-1 downto 0);
|
signal IX1_BHT_CNT1 : std_logic_vector(2-1 downto 0);
|
signal IX1_BHT_CNT1 : std_logic_vector(2-1 downto 0);
|
signal IX1_BHT_PWE : std_logic;
|
signal IX1_BHT_PWE : std_logic;
|
signal IX1_BHT_WE : std_logic_vector(2-1 downto 0);
|
signal IX1_BHT_WE : std_logic_vector(2-1 downto 0);
|
signal IX1_PDADR0,IX1_PDADR1 : ADR_T;
|
signal IX1_PDADR0,IX1_PDADR1 : ADR_T;
|
signal IX1_PDIADR0,IX1_PDIADR1 : ADR_T;
|
signal IX1_PDIADR0,IX1_PDIADR1 : ADR_T;
|
signal IX1_DIMS : std_logic_vector(NW-1 downto 0);
|
signal IX1_DIMS : std_logic_vector(NW-1 downto 0);
|
signal IX1_MPJRX : std_logic_vector(NW-1 downto 0);
|
signal IX1_MPJRX : std_logic_vector(NW-1 downto 0);
|
signal IX1_OPA0_V : std_logic;
|
signal IX1_OPA0_V : std_logic;
|
signal IX1_OPB0_V : std_logic;
|
signal IX1_OPB0_V : std_logic;
|
signal IX1_OPA1_V : std_logic;
|
signal IX1_OPA1_V : std_logic;
|
signal IX1_OPB1_V : std_logic;
|
signal IX1_OPB1_V : std_logic;
|
signal IX1_OPA0_V_q : std_logic;
|
signal IX1_OPA0_V_q : std_logic;
|
signal IX1_OPB0_V_q : std_logic;
|
signal IX1_OPB0_V_q : std_logic;
|
signal IX1_OPA1_V_q : std_logic;
|
signal IX1_OPA1_V_q : std_logic;
|
signal IX1_OPB1_V_q : std_logic;
|
signal IX1_OPB1_V_q : std_logic;
|
signal IX1_OPA0 : SDWORD_T;
|
signal IX1_OPA0 : SDWORD_T;
|
signal IX1_OPB0 : SDWORD_T;
|
signal IX1_OPB0 : SDWORD_T;
|
signal IX1_OPA1 : SDWORD_T;
|
signal IX1_OPA1 : SDWORD_T;
|
signal IX1_OPB1 : SDWORD_T;
|
signal IX1_OPB1 : SDWORD_T;
|
signal IX1_OPA0_q : SDWORD_T;
|
signal IX1_OPA0_q : SDWORD_T;
|
signal IX1_OPB0_q : SDWORD_T;
|
signal IX1_OPB0_q : SDWORD_T;
|
signal IX1_OPA1_q : SDWORD_T;
|
signal IX1_OPA1_q : SDWORD_T;
|
signal IX1_OPB1_q : SDWORD_T;
|
signal IX1_OPB1_q : SDWORD_T;
|
signal IX1_PASEL0_q : std_logic_vector(4-1 downto 0);
|
signal IX1_PASEL0_q : std_logic_vector(4-1 downto 0);
|
signal IX1_PASEL1_q : std_logic_vector(4-1 downto 0);
|
signal IX1_PASEL1_q : std_logic_vector(4-1 downto 0);
|
signal IX1_FWDX : std_logic_vector(NW-1 downto 0);
|
signal IX1_FWDX : std_logic_vector(NW-1 downto 0);
|
signal IX1_SHFT0,IX1_SHFT1 : unsigned(5-1 downto 0);
|
signal IX1_SHFT0,IX1_SHFT1 : unsigned(5-1 downto 0);
|
signal IX1_SHF_CTRL0,IX1_SHF_CTRL1 : SHF_CTRL;
|
signal IX1_SHF_CTRL0,IX1_SHF_CTRL1 : SHF_CTRL;
|
signal IX1_SHF_RES0,IX1_SHF_RES1 : SDWORD_T;
|
signal IX1_SHF_RES0,IX1_SHF_RES1 : SDWORD_T;
|
signal IX1_PA0_ALU_RES : SDWORD_T;
|
signal IX1_PA0_ALU_RES : SDWORD_T;
|
signal IX1_PA1_ALU_RES : SDWORD_T;
|
signal IX1_PA1_ALU_RES : SDWORD_T;
|
signal IX1_B2BAC : std_logic;
|
signal IX1_B2BAC : std_logic;
|
signal IX1_SHF0_V : std_logic;
|
signal IX1_SHF0_V : std_logic;
|
signal IX1_SHF1_V : std_logic;
|
signal IX1_SHF1_V : std_logic;
|
signal IX1_KTS : std_logic;
|
signal IX1_KTS : std_logic;
|
signal IX1_KTS_q : std_logic;
|
signal IX1_KTS_q : std_logic;
|
signal IX1_PSLP : std_logic;
|
signal IX1_PSLP : std_logic;
|
|
|
signal IX2_DRD0,IX2_DRD1 : SDWORD_T;
|
signal IX2_DRD0,IX2_DRD1 : SDWORD_T;
|
signal IX2_PA0_RES : SDWORD_T;
|
signal IX2_PA0_RES : SDWORD_T;
|
signal IX2_PA1_RES : SDWORD_T;
|
signal IX2_PA1_RES : SDWORD_T;
|
signal IX2_PB0_RES : SDWORD_T;
|
signal IX2_PB0_RES : SDWORD_T;
|
signal IX2_PB1_RES : SDWORD_T;
|
signal IX2_PB1_RES : SDWORD_T;
|
signal IX2_INSTR : DEC_INSTR_VEC_T(NW-1 downto 0);
|
signal IX2_INSTR : DEC_INSTR_VEC_T(NW-1 downto 0);
|
signal IX2_INSTR_q : DEC_INSTR_VEC_T(NW-1 downto 0);
|
signal IX2_INSTR_q : DEC_INSTR_VEC_T(NW-1 downto 0);
|
signal IX2_DRD0_q,IX2_DRD1_q : SDWORD_T;
|
signal IX2_DRD0_q,IX2_DRD1_q : SDWORD_T;
|
signal IX2_DADR0_q,IX2_DADR1_q : ADR_T;
|
signal IX2_DADR0_q,IX2_DADR1_q : ADR_T;
|
signal IX2_V,IX2_V_q : std_logic_vector(NW-1 downto 0);
|
signal IX2_V,IX2_V_q : std_logic_vector(NW-1 downto 0);
|
signal IX2_V_BJX : std_logic_vector(NW-1 downto 0);
|
signal IX2_V_BJX : std_logic_vector(NW-1 downto 0);
|
signal IX2_EV,IX2_EV_q : std_logic_vector(NW-1 downto 0);
|
signal IX2_EV,IX2_EV_q : std_logic_vector(NW-1 downto 0);
|
signal IX2_FWDE_q : std_logic_vector(NW-1 downto 0);
|
signal IX2_FWDE_q : std_logic_vector(NW-1 downto 0);
|
signal IX2_FWDX : std_logic_vector(NW-1 downto 0);
|
signal IX2_FWDX : std_logic_vector(NW-1 downto 0);
|
signal IX2_FWDX_q : std_logic_vector(NW-1 downto 0);
|
signal IX2_FWDX_q : std_logic_vector(NW-1 downto 0);
|
signal IX2_CSRU_RES,IX2_CSRU_RES_q : SDWORD_T;
|
signal IX2_CSRU_RES,IX2_CSRU_RES_q : SDWORD_T;
|
signal IX2_PC0_q,IX2_PC1_q : ADR_T;
|
signal IX2_PC0_q,IX2_PC1_q : ADR_T;
|
signal IX2_ILLG : std_logic;
|
signal IX2_ILLG : std_logic;
|
signal IX2_LSADR0_q,IX2_LSADR1_q : ADR_T;
|
signal IX2_LSADR0_q,IX2_LSADR1_q : ADR_T;
|
signal IX2_DWE_q : std_logic_vector(NW-1 downto 0);
|
signal IX2_DWE_q : std_logic_vector(NW-1 downto 0);
|
signal IX2_MALGN_q : std_logic_vector(NW-1 downto 0);
|
signal IX2_MALGN_q : std_logic_vector(NW-1 downto 0);
|
signal IX2_EERTA,IX2_EERTA_q : ADR_T;
|
signal IX2_EERTA,IX2_EERTA_q : ADR_T;
|
signal IX2_OPA0_V : std_logic;
|
signal IX2_OPA0_V : std_logic;
|
signal IX2_OPB0_V : std_logic;
|
signal IX2_OPB0_V : std_logic;
|
signal IX2_OPA1_V : std_logic;
|
signal IX2_OPA1_V : std_logic;
|
signal IX2_OPB1_V : std_logic;
|
signal IX2_OPB1_V : std_logic;
|
signal IX2_OPA0 : SDWORD_T;
|
signal IX2_OPA0 : SDWORD_T;
|
signal IX2_OPB0 : SDWORD_T;
|
signal IX2_OPB0 : SDWORD_T;
|
signal IX2_OPA1 : SDWORD_T;
|
signal IX2_OPA1 : SDWORD_T;
|
signal IX2_OPB1 : SDWORD_T;
|
signal IX2_OPB1 : SDWORD_T;
|
signal IX2_OPA0_q : SDWORD_T;
|
signal IX2_OPA0_q : SDWORD_T;
|
signal IX2_OPB0_q : SDWORD_T;
|
signal IX2_OPB0_q : SDWORD_T;
|
signal IX2_OPA1_q : SDWORD_T;
|
signal IX2_OPA1_q : SDWORD_T;
|
signal IX2_OPB1_q : SDWORD_T;
|
signal IX2_OPB1_q : SDWORD_T;
|
signal IX2_PASEL0_q : std_logic_vector(4-1 downto 0);
|
signal IX2_PASEL0_q : std_logic_vector(4-1 downto 0);
|
signal IX2_PASEL1_q : std_logic_vector(4-1 downto 0);
|
signal IX2_PASEL1_q : std_logic_vector(4-1 downto 0);
|
signal IX2_PA0_RES_X : SDWORD_T;
|
signal IX2_PA0_RES_X : SDWORD_T;
|
signal IX2_PA1_RES_X : SDWORD_T;
|
signal IX2_PA1_RES_X : SDWORD_T;
|
signal IX2_ERR0_q : std_logic;
|
signal IX2_ERR0_q : std_logic;
|
signal IX2_ERR1_q : std_logic;
|
signal IX2_ERR1_q : std_logic;
|
signal IX2_PA0_ALU_RES : SDWORD_T;
|
signal IX2_PA0_ALU_RES : SDWORD_T;
|
signal IX2_PA1_ALU_RES : SDWORD_T;
|
signal IX2_PA1_ALU_RES : SDWORD_T;
|
signal IX2_NOLD0_RES : SDWORD_T;
|
signal IX2_NOLD0_RES : SDWORD_T;
|
signal IX2_NOLD1_RES : SDWORD_T;
|
signal IX2_NOLD1_RES : SDWORD_T;
|
signal IX2_PC0P4_q,IX2_PC1P4_q : ADR_T;
|
signal IX2_PC0P4_q,IX2_PC1P4_q : ADR_T;
|
signal IX2_SBRK0,IX2_HOBRK0 : std_logic;
|
signal IX2_SBRK0,IX2_HOBRK0 : std_logic;
|
signal IX2_HOADR,IX2_HALT,IX2_HALT_q : std_logic_vector(NW-1 downto 0);
|
signal IX2_HOADR,IX2_HALT,IX2_HALT_q : std_logic_vector(NW-1 downto 0);
|
signal IX2_DRSM : std_logic_vector(NW-1 downto 0);
|
signal IX2_DRSM : std_logic_vector(NW-1 downto 0);
|
signal IX2_HIS,IX2_HIS_q : std_logic;
|
signal IX2_HIS,IX2_HIS_q : std_logic;
|
signal IX2_DHIS,IX2_DHIS_q : std_logic;
|
signal IX2_DHIS,IX2_DHIS_q : std_logic;
|
signal IX2_STEP : std_logic;
|
signal IX2_STEP : std_logic;
|
signal IX2_BJX : std_logic;
|
signal IX2_BJX : std_logic;
|
signal IX2_BJTA : ADR_T;
|
signal IX2_BJTA : ADR_T;
|
|
|
signal IX3_DRD0,IX3_DRD1 : SDWORD_T;
|
signal IX3_DRD0,IX3_DRD1 : SDWORD_T;
|
signal IX3_DRD0_X,IX3_DRD1_X : SDWORD_T;
|
signal IX3_DRD0_X,IX3_DRD1_X : SDWORD_T;
|
signal IX3_LDAT0_V : std_logic;
|
signal IX3_LDAT0_V : std_logic;
|
signal IX3_LDAT0 : SDWORD_T;
|
signal IX3_LDAT0 : SDWORD_T;
|
signal IX3_LDAT1_V : std_logic;
|
signal IX3_LDAT1_V : std_logic;
|
signal IX3_LDAT1 : SDWORD_T;
|
signal IX3_LDAT1 : SDWORD_T;
|
signal IX3_EXCP : std_logic;
|
signal IX3_EXCP : std_logic;
|
signal IX3_EPC : ADR_T;
|
signal IX3_EPC : ADR_T;
|
signal IX3_ECAUSE : std_logic_vector(5-1 downto 0);
|
signal IX3_ECAUSE : std_logic_vector(5-1 downto 0);
|
signal IX3_EDADR : ADR_T;
|
signal IX3_EDADR : ADR_T;
|
signal IX3_ERET : std_logic;
|
signal IX3_ERET : std_logic;
|
signal IX3_HALT : std_logic;
|
signal IX3_HALT : std_logic;
|
signal IX3_STL : std_logic_vector(NW-1 downto 0);
|
signal IX3_STL : std_logic_vector(NW-1 downto 0);
|
signal IX3_SBRE : std_logic_vector(NW-1 downto 0);
|
signal IX3_SBRE : std_logic_vector(NW-1 downto 0);
|
signal IX3_DWE : std_logic;
|
signal IX3_DWE : std_logic;
|
signal IX3_SDATO : std_logic_vector(SDLEN-1 downto 0);
|
signal IX3_SDATO : std_logic_vector(SDLEN-1 downto 0);
|
signal IX3_DBE : std_logic_vector(4-1 downto 0);
|
signal IX3_DBE : std_logic_vector(4-1 downto 0);
|
signal IX3_DADR0 : ADR_T;
|
signal IX3_DADR0 : ADR_T;
|
signal IX3_LS_OP : LS_OP_T;
|
signal IX3_LS_OP : LS_OP_T;
|
signal IX3_RFTCH : std_logic;
|
signal IX3_RFTCH : std_logic;
|
signal IX3_EERX : std_logic;
|
signal IX3_EERX : std_logic;
|
signal IX3_CLRP : std_logic;
|
signal IX3_CLRP : std_logic;
|
signal IX3_CLRB : std_logic;
|
signal IX3_CLRB : std_logic;
|
signal IX3_CLRD : std_logic;
|
signal IX3_CLRD : std_logic;
|
signal IX3_KPRD : std_logic_vector(NW-1 downto 0);
|
signal IX3_KPRD : std_logic_vector(NW-1 downto 0);
|
signal IX3_WE : std_logic_vector(NW-1 downto 0);
|
signal IX3_WE : std_logic_vector(NW-1 downto 0);
|
signal IX3_PA0_ALU_RES : SDWORD_T;
|
signal IX3_PA0_ALU_RES : SDWORD_T;
|
signal IX3_PA1_ALU_RES : SDWORD_T;
|
signal IX3_PA1_ALU_RES : SDWORD_T;
|
signal IX3_PDADR0 : ADR_T;
|
signal IX3_PDADR0 : ADR_T;
|
signal IX3_PDIADR0 : ADR_T;
|
signal IX3_PDIADR0 : ADR_T;
|
signal IX3_DIMS : std_logic;
|
signal IX3_DIMS : std_logic;
|
signal IX3_HPC : ADR_T;
|
signal IX3_HPC : ADR_T;
|
signal IX3_CLRP_NOHLT : std_logic;
|
signal IX3_CLRP_NOHLT : std_logic;
|
signal IX3_CLRD_NOHLT : std_logic;
|
signal IX3_CLRD_NOHLT : std_logic;
|
|
|
signal WB_SFT_INT : std_logic;
|
signal WB_SFT_INT : std_logic;
|
signal WB_TMR_INT : std_logic;
|
signal WB_TMR_INT : std_logic;
|
signal WB_RDA0,WB_RDB0 : std_logic_vector(SDLEN-1 downto 0);
|
signal WB_RDA0,WB_RDB0 : std_logic_vector(SDLEN-1 downto 0);
|
signal WB_RDA1,WB_RDB1 : std_logic_vector(SDLEN-1 downto 0);
|
signal WB_RDA1,WB_RDB1 : std_logic_vector(SDLEN-1 downto 0);
|
signal WB_PXE : std_logic;
|
signal WB_PXE : std_logic;
|
signal WB_EXCP,WB_EIS : std_logic;
|
signal WB_EXCP,WB_EIS : std_logic;
|
signal WB_ETVA : ADR_T;
|
signal WB_ETVA : ADR_T;
|
signal WB_MSTATUS : SDWORD_T;
|
signal WB_MSTATUS : SDWORD_T;
|
signal WB_MEPC : ADR_T;
|
signal WB_MEPC : ADR_T;
|
signal WB_MBASE : ADR_T;
|
signal WB_MBASE : ADR_T;
|
signal WB_MBOUND : ADR_T;
|
signal WB_MBOUND : ADR_T;
|
signal WB_MIBASE : ADR_T;
|
signal WB_MIBASE : ADR_T;
|
signal WB_MIBOUND : ADR_T;
|
signal WB_MIBOUND : ADR_T;
|
signal WB_MDBASE : ADR_T;
|
signal WB_MDBASE : ADR_T;
|
signal WB_MDBOUND : ADR_T;
|
signal WB_MDBOUND : ADR_T;
|
signal WB_FFLAGS : std_logic_vector(5-1 downto 0);
|
signal WB_FFLAGS : std_logic_vector(5-1 downto 0);
|
signal WB_FRM : std_logic_vector(3-1 downto 0);
|
signal WB_FRM : std_logic_vector(3-1 downto 0);
|
signal WB_DHLTRQ : std_logic;
|
signal WB_DHLTRQ : std_logic;
|
signal WB_DRSM : std_logic;
|
signal WB_DRSM : std_logic;
|
signal WB_DPC : ADR_T;
|
signal WB_DPC : ADR_T;
|
signal WB_DMODE : std_logic;
|
signal WB_DMODE : std_logic;
|
signal WB_DIE : std_logic;
|
signal WB_DIE : std_logic;
|
signal WB_CHK_ENB : std_logic;
|
signal WB_CHK_ENB : std_logic;
|
signal WB_STRT : std_logic;
|
signal WB_STRT : std_logic;
|
signal WB_STRTPC : ADR_T;
|
signal WB_STRTPC : ADR_T;
|
signal WB_RSM : std_logic;
|
signal WB_RSM : std_logic;
|
signal WB_HLTRQ : std_logic;
|
signal WB_HLTRQ : std_logic;
|
signal WB_HLTURQ : std_logic;
|
signal WB_HLTURQ : std_logic;
|
signal WB_HLTOBRK : std_logic;
|
signal WB_HLTOBRK : std_logic;
|
signal WB_HLTOADR : std_logic_vector(NW-1 downto 0);
|
signal WB_HLTOADR : std_logic_vector(NW-1 downto 0);
|
signal WB_HLTADR : ADR_T;
|
signal WB_HLTADR : ADR_T;
|
signal WB_IE : std_logic;
|
signal WB_IE : std_logic;
|
signal WB_DRST : std_logic;
|
signal WB_DRST : std_logic;
|
signal WB_HALTD : std_logic;
|
signal WB_HALTD : std_logic;
|
signal WB_STOPTIME : std_logic;
|
signal WB_STOPTIME : std_logic;
|
signal WB_STOPCYCLE : std_logic;
|
signal WB_STOPCYCLE : std_logic;
|
signal WB_DHOBRK : std_logic;
|
signal WB_DHOBRK : std_logic;
|
signal WB_DHOADR : std_logic;
|
signal WB_DHOADR : std_logic;
|
signal WB_DHADR : ADR_T;
|
signal WB_DHADR : ADR_T;
|
signal WB_CPQ,WB_DCPQ : std_logic_vector(SDLEN-1 downto 0);
|
signal WB_CPQ,WB_DCPQ : std_logic_vector(SDLEN-1 downto 0);
|
signal WB_MMODE : std_logic;
|
signal WB_MMODE : std_logic;
|
signal WB_DSI : std_logic_vector(SDLEN-1 downto 0);
|
signal WB_DSI : std_logic_vector(SDLEN-1 downto 0);
|
signal WB_XSTRT : std_logic;
|
signal WB_XSTRT : std_logic;
|
signal WB_XSTRTPC : ADR_T;
|
signal WB_XSTRTPC : ADR_T;
|
signal WB_DSTEP : std_logic;
|
signal WB_DSTEP : std_logic;
|
signal WB_DFRCSI,IF1_DFRCSI_q : std_logic;
|
signal WB_DFRCSI,IF1_DFRCSI_q : std_logic;
|
signal WB_HCSRQ : SDWORD_T;
|
signal WB_HCSRQ : SDWORD_T;
|
signal WB_HCSR : std_logic;
|
signal WB_HCSR : std_logic;
|
signal WB_HILLG : std_logic;
|
signal WB_HILLG : std_logic;
|
signal WB_HCPQ : std_logic_vector(SDLEN-1 downto 0);
|
signal WB_HCPQ : std_logic_vector(SDLEN-1 downto 0);
|
signal WB_CSRQ : SDWORD_T;
|
signal WB_CSRQ : SDWORD_T;
|
signal WB_ILLG : std_logic;
|
signal WB_ILLG : std_logic;
|
signal WB_HCP : std_logic;
|
signal WB_HCP : std_logic;
|
|
|
-- debug-only modules
|
-- debug-only modules
|
|
|
component RV01_ST_CHECKER is
|
component RV01_ST_CHECKER is
|
generic(
|
generic(
|
ST_FILENAME : string := "NONE"
|
ST_FILENAME : string := "NONE"
|
);
|
);
|
port(
|
port(
|
CLK_i : in std_logic;
|
CLK_i : in std_logic;
|
ENB_i : in std_logic;
|
ENB_i : in std_logic;
|
LS_OP_i : in LS_OP_T;
|
LS_OP_i : in LS_OP_T;
|
DWE_i : in std_logic;
|
DWE_i : in std_logic;
|
BE_i : in std_logic_vector(4-1 downto 0);
|
BE_i : in std_logic_vector(4-1 downto 0);
|
DADR_i : in unsigned(ALEN-1 downto 0);
|
DADR_i : in unsigned(ALEN-1 downto 0);
|
DDATO_i : in std_logic_vector(SDLEN-1 downto 0)
|
DDATO_i : in std_logic_vector(SDLEN-1 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_WB_CHECKER is
|
component RV01_WB_CHECKER is
|
generic(
|
generic(
|
WB_FILENAME : string := "NONE"
|
WB_FILENAME : string := "NONE"
|
);
|
);
|
port(
|
port(
|
CLK_i : in std_logic;
|
CLK_i : in std_logic;
|
ENB_i : in std_logic;
|
ENB_i : in std_logic;
|
WE0_i : in std_logic;
|
WE0_i : in std_logic;
|
WE1_i : in std_logic;
|
WE1_i : in std_logic;
|
IX_INSTR0_i : in DEC_INSTR_T;
|
IX_INSTR0_i : in DEC_INSTR_T;
|
IX_INSTR1_i : in DEC_INSTR_T;
|
IX_INSTR1_i : in DEC_INSTR_T;
|
IX_DRD0_i : in SDWORD_T;
|
IX_DRD0_i : in SDWORD_T;
|
IX_DRD1_i : in SDWORD_T
|
IX_DRD1_i : in SDWORD_T
|
);
|
);
|
end component;
|
end component;
|
|
|
component RV01_STATS is
|
component RV01_STATS is
|
port(
|
port(
|
CLK_i : in std_logic;
|
CLK_i : in std_logic;
|
RST_i : in std_logic;
|
RST_i : in std_logic;
|
ID_V_i : in std_logic_vector(2-1 downto 0);
|
ID_V_i : in std_logic_vector(2-1 downto 0);
|
ID_PS_i : in std_logic_vector(2-1 downto 0);
|
ID_PS_i : in std_logic_vector(2-1 downto 0);
|
ID_PXE1_i : std_logic;
|
ID_PXE1_i : std_logic;
|
IX2_V_i : in std_logic_vector(2-1 downto 0);
|
IX2_V_i : in std_logic_vector(2-1 downto 0);
|
STRT_i : in std_logic;
|
STRT_i : in std_logic;
|
HALT_i : in std_logic
|
HALT_i : in std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
begin
|
begin
|
|
|
----------------------------------------------------
|
----------------------------------------------------
|
-- Notes:
|
-- Notes:
|
----------------------------------------------------
|
----------------------------------------------------
|
|
|
-- *** Pipeline organisation ***
|
-- *** Pipeline organisation ***
|
-- RV0101 employs the following 7-stage pipeline:
|
-- RV0101 employs the following 7-stage pipeline:
|
-- 1) Instruction Fetch (IF1)
|
-- 1) Instruction Fetch (IF1)
|
-- 2) Instruction Fetch (IF2)
|
-- 2) Instruction Fetch (IF2)
|
-- 3) Instruction Decode (ID)
|
-- 3) Instruction Decode (ID)
|
-- 4) Instruction Execute (IX1)
|
-- 4) Instruction Execute (IX1)
|
-- 5) Instruction Execute (IX2)
|
-- 5) Instruction Execute (IX2)
|
-- 6) Instruction Execute (IX3)
|
-- 6) Instruction Execute (IX3)
|
-- 7) Write Back (WB)
|
-- 7) Write Back (WB)
|
|
|
-- *** Branch & Jump processing ***
|
-- *** Branch & Jump processing ***
|
-- When branch prediction is not enabled, branches and
|
-- When branch prediction is not enabled, branches and
|
-- jumps are processed in IX1 stage and there's a fixed
|
-- jumps are processed in IX1 stage and there's a fixed
|
-- branch penalty of 2 cycles.
|
-- branch penalty of 2 cycles.
|
-- When branch prediction is enabled, branches and jal
|
-- When branch prediction is enabled, branches and jal
|
-- instructions are predicted in IF2 stage using a branch
|
-- instructions are predicted in IF2 stage using a branch
|
-- history table (jalr instructions are not predicted
|
-- history table (jalr instructions are not predicted
|
-- at all). Prediction are verified in IX1 stage, so
|
-- at all). Prediction are verified in IX1 stage, so
|
-- penalty for mis-predicted branches is of 2 cycles.
|
-- penalty for mis-predicted branches is of 2 cycles.
|
|
|
----------------------------------------------------
|
----------------------------------------------------
|
-- Reset
|
-- Reset
|
----------------------------------------------------
|
----------------------------------------------------
|
|
|
IRST <= RST_i or WB_DRST;
|
IRST <= RST_i or WB_DRST;
|
|
|
----------------------------------------------------
|
----------------------------------------------------
|
-- CPU initialization logic
|
-- CPU initialization logic
|
----------------------------------------------------
|
----------------------------------------------------
|
|
|
GINIT_1 : if(BRANCH_PREDICTION_ENABLED = '1') generate
|
GINIT_1 : if(BRANCH_PREDICTION_ENABLED = '1') generate
|
|
|
-- Branch prediction is enabled: initialize BHT RAM
|
-- Branch prediction is enabled: initialize BHT RAM
|
-- before starting the CPU.
|
-- before starting the CPU.
|
|
|
U_INIT: RV01_CPU_INIT
|
U_INIT: RV01_CPU_INIT
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
RST_i => IRST,
|
RST_i => IRST,
|
STRT_i => WB_XSTRT,
|
STRT_i => WB_XSTRT,
|
RSM_i => ZERO,
|
RSM_i => ZERO,
|
BHT_INIT_END_i => BHT_INIT_END,
|
BHT_INIT_END_i => BHT_INIT_END,
|
|
|
INIT_STRT_o => INIT_STRT,
|
INIT_STRT_o => INIT_STRT,
|
STRT_o => STRT
|
STRT_o => STRT
|
);
|
);
|
|
|
end generate;
|
end generate;
|
|
|
GINIT_0 : if(BRANCH_PREDICTION_ENABLED = '0') generate
|
GINIT_0 : if(BRANCH_PREDICTION_ENABLED = '0') generate
|
|
|
-- Branch prediction is disabled: start the CPU
|
-- Branch prediction is disabled: start the CPU
|
-- immediately.
|
-- immediately.
|
|
|
INIT_STRT <= '0';
|
INIT_STRT <= '0';
|
STRT <= WB_XSTRT;
|
STRT <= WB_XSTRT;
|
|
|
end generate;
|
end generate;
|
|
|
----------------------------------------------------
|
----------------------------------------------------
|
-- IF1 Stage:
|
-- IF1 Stage:
|
----------------------------------------------------
|
----------------------------------------------------
|
|
|
-- Instruction Fetch Logic
|
-- Instruction Fetch Logic
|
|
|
GPX_IF1_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
GPX_IF1_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
|
|
U_FTCH : RV01_FTCHLOG_2W
|
U_FTCH : RV01_FTCHLOG_2W
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
RST_i => IRST,
|
RST_i => IRST,
|
STRT_i => STRT,
|
STRT_i => STRT,
|
STRTPC_i => WB_XSTRTPC,
|
STRTPC_i => WB_XSTRTPC,
|
HALT_i => IX3_HALT,
|
HALT_i => IX3_HALT,
|
BJX_i => IX2_BJX,
|
BJX_i => IX2_BJX,
|
BJTA_i => IX2_BJTA,
|
BJTA_i => IX2_BJTA,
|
PBX_i => IF2_PBX,
|
PBX_i => IF2_PBX,
|
PBTA_i => IF2_PBTA,
|
PBTA_i => IF2_PBTA,
|
--KLL1_i => IF2_KLL1,
|
--KLL1_i => IF2_KLL1,
|
KLL1_i => IF2_JRKLL1,
|
KLL1_i => IF2_JRKLL1,
|
PJRX_i => IF2_PJRX,
|
PJRX_i => IF2_PJRX,
|
PJRTA_i => IF2_PJRTA,
|
PJRTA_i => IF2_PJRTA,
|
EXCP_i => IX3_EXCP,
|
EXCP_i => IX3_EXCP,
|
ERET_i => IX3_ERET,
|
ERET_i => IX3_ERET,
|
RFTCH_i => IX3_RFTCH,
|
RFTCH_i => IX3_RFTCH,
|
ETVA_i => IX2_EERTA_q,
|
ETVA_i => IX2_EERTA_q,
|
PSTALL_i => ID_PSTALL,
|
PSTALL_i => ID_PSTALL,
|
DHALT_i => IX3_HALT,
|
DHALT_i => IX3_HALT,
|
|
|
IFV_o => IF1_V,
|
IFV_o => IF1_V,
|
IADR0_o => IF1_PC(0),
|
IADR0_o => IF1_PC(0),
|
IADR1_o => IF1_PC(1),
|
IADR1_o => IF1_PC(1),
|
IADR_MIS_o => IF1_IADR_MIS
|
IADR_MIS_o => IF1_IADR_MIS
|
);
|
);
|
|
|
end generate;
|
end generate;
|
|
|
GPX_IF1_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
|
GPX_IF1_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
|
|
|
U_FTCH : RV01_FTCHLOG_1W
|
U_FTCH : RV01_FTCHLOG_1W
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
RST_i => IRST,
|
RST_i => IRST,
|
STRT_i => STRT,
|
STRT_i => STRT,
|
HALT_i => IX3_HALT,
|
HALT_i => IX3_HALT,
|
STRTPC_i => WB_XSTRTPC,
|
STRTPC_i => WB_XSTRTPC,
|
BJX_i => IX2_BJX,
|
BJX_i => IX2_BJX,
|
BJTA_i => IX2_BJTA,
|
BJTA_i => IX2_BJTA,
|
PBX_i => IF2_PBX,
|
PBX_i => IF2_PBX,
|
PBTA_i => IF2_PBTA,
|
PBTA_i => IF2_PBTA,
|
--KLL1_i => IF2_KLL1,
|
--KLL1_i => IF2_KLL1,
|
KLL1_i => IF2_JRKLL1,
|
KLL1_i => IF2_JRKLL1,
|
PJRX_i => IF2_PJRX,
|
PJRX_i => IF2_PJRX,
|
PJRTA_i => IF2_PJRTA,
|
PJRTA_i => IF2_PJRTA,
|
EXCP_i => IX3_EXCP,
|
EXCP_i => IX3_EXCP,
|
ERET_i => IX3_ERET,
|
ERET_i => IX3_ERET,
|
RFTCH_i => IX3_RFTCH,
|
RFTCH_i => IX3_RFTCH,
|
ETVA_i => IX2_EERTA_q,
|
ETVA_i => IX2_EERTA_q,
|
PSTALL_i => ID_PSTALL,
|
PSTALL_i => ID_PSTALL,
|
DHALT_i => IX3_HALT,
|
DHALT_i => IX3_HALT,
|
|
|
IFV_o => IF1_V(0),
|
IFV_o => IF1_V(0),
|
IADR0_o => IF1_PC(0),
|
IADR0_o => IF1_PC(0),
|
IADR_MIS_o => IF1_IADR_MIS
|
IADR_MIS_o => IF1_IADR_MIS
|
);
|
);
|
|
|
IF1_V(1) <= '0';
|
IF1_V(1) <= '0';
|
IF1_PC(1) <= (others => '0');
|
IF1_PC(1) <= (others => '0');
|
|
|
end generate;
|
end generate;
|
|
|
-- CPU Halt flag
|
-- CPU Halt flag
|
HALT_o <= WB_HALTD;
|
HALT_o <= WB_HALTD;
|
|
|
-- Instruction address virtual to physical translation
|
-- Instruction address virtual to physical translation
|
IADR_o <= IF1_PC(0);
|
IADR_o <= IF1_PC(0);
|
|
|
-- Pipeline Registers
|
-- Pipeline Registers
|
|
|
process(CLK_i)
|
process(CLK_i)
|
begin
|
begin
|
if(CLK_i = '1' and CLK_i'event) then
|
if(CLK_i = '1' and CLK_i'event) then
|
|
|
if(IRST = '1') then
|
if(IRST = '1') then
|
IF1_V_q <= "00";
|
IF1_V_q <= "00";
|
elsif(IX3_HALT = '1') then
|
elsif(IX3_HALT = '1') then
|
IF1_V_q <= "00";
|
IF1_V_q <= "00";
|
elsif(ID_PSTALL = '0') then
|
elsif(ID_PSTALL = '0') then
|
if(WB_DFRCSI = '1') then
|
if(WB_DFRCSI = '1') then
|
IF1_V_q <= "01";
|
IF1_V_q <= "01";
|
else
|
else
|
IF1_V_q <= IF1_V;
|
IF1_V_q <= IF1_V;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
if(IRST = '1') then
|
if(IRST = '1') then
|
IF1_DFRCSI_q <= '0';
|
IF1_DFRCSI_q <= '0';
|
else
|
else
|
IF1_DFRCSI_q <= WB_DFRCSI;
|
IF1_DFRCSI_q <= WB_DFRCSI;
|
end if;
|
end if;
|
|
|
IF1_PC_q(0) <= IF1_PC(0);
|
IF1_PC_q(0) <= IF1_PC(0);
|
IF1_PC_q(1) <= IF1_PC(1);
|
IF1_PC_q(1) <= IF1_PC(1);
|
IF1_IADR_MIS_q <= (IF1_IADR_MIS & IF1_IADR_MIS);
|
IF1_IADR_MIS_q <= (IF1_IADR_MIS & IF1_IADR_MIS);
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- Exception processing: fetch logic detects address
|
-- Exception processing: fetch logic detects address
|
-- misalignments and records them into IF_ADR_MIS_q
|
-- misalignments and records them into IF_ADR_MIS_q
|
-- (each instruction of the pair get its own copy of
|
-- (each instruction of the pair get its own copy of
|
-- the flag, in case instruction #0 is invalid).
|
-- the flag, in case instruction #0 is invalid).
|
|
|
GBPE_0 : if(BRANCH_PREDICTION_ENABLED = '0') generate
|
GBPE_0 : if(BRANCH_PREDICTION_ENABLED = '0') generate
|
|
|
BHT_INIT_END <= '1';
|
BHT_INIT_END <= '1';
|
IF2_PBX <= '0';
|
IF2_PBX <= '0';
|
IF2_KLL1 <= '0';
|
IF2_KLL1 <= '0';
|
IF2_PBTA <= (others => '0');
|
IF2_PBTA <= (others => '0');
|
IF2_BPVD0 <= (others => '0');
|
IF2_BPVD0 <= (others => '0');
|
IF2_BPVD1 <= (others => '0');
|
IF2_BPVD1 <= (others => '0');
|
|
|
end generate;
|
end generate;
|
|
|
GBPE_1 : if(BRANCH_PREDICTION_ENABLED = '1') generate
|
GBPE_1 : if(BRANCH_PREDICTION_ENABLED = '1') generate
|
|
|
-- Branches (and jal's) prediction unit
|
-- Branches (and jal's) prediction unit
|
|
|
U_BPU : RV01_BPU
|
U_BPU : RV01_BPU
|
generic map(
|
generic map(
|
BHT_SIZE => BHT_SIZE,
|
BHT_SIZE => BHT_SIZE,
|
PXE => PARALLEL_EXECUTION_ENABLED,
|
PXE => PARALLEL_EXECUTION_ENABLED,
|
NW => NW
|
NW => NW
|
)
|
)
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
RST_i => IRST,
|
RST_i => IRST,
|
INIT_STRT_i => INIT_STRT,
|
INIT_STRT_i => INIT_STRT,
|
IF_V_i => IF1_V,
|
IF_V_i => IF1_V,
|
IF_PC_i => IF1_PC,
|
IF_PC_i => IF1_PC,
|
IF2_V_i => IF2_V,
|
IF2_V_i => IF2_V,
|
IF2_PC_i => IF1_PC_q,
|
IF2_PC_i => IF1_PC_q,
|
BHT_BTA_i => IX1_BHT_TA,
|
BHT_BTA_i => IX1_BHT_TA,
|
BHT_PC_i => ID_PC_q,
|
BHT_PC_i => ID_PC_q,
|
BHT_CNT0_i => IX1_BHT_CNT0,
|
BHT_CNT0_i => IX1_BHT_CNT0,
|
BHT_CNT1_i => IX1_BHT_CNT1,
|
BHT_CNT1_i => IX1_BHT_CNT1,
|
BHT_WE_i => IX1_BHT_WE,
|
BHT_WE_i => IX1_BHT_WE,
|
|
|
INIT_END_o => BHT_INIT_END,
|
INIT_END_o => BHT_INIT_END,
|
PBX_o => IF2_PBX,
|
PBX_o => IF2_PBX,
|
KLL1_o => IF2_KLL1,
|
KLL1_o => IF2_KLL1,
|
PBTA_o => IF2_PBTA,
|
PBTA_o => IF2_PBTA,
|
BPVD0_o => IF2_BPVD0,
|
BPVD0_o => IF2_BPVD0,
|
BPVD1_o => IF2_BPVD1
|
BPVD1_o => IF2_BPVD1
|
);
|
);
|
|
|
end generate;
|
end generate;
|
|
|
GJRPE_1 : if(JALR_PREDICTION_ENABLED = '1') generate
|
GJRPE_1 : if(JALR_PREDICTION_ENABLED = '1') generate
|
|
|
U_JRPU : RV01_JRPU
|
U_JRPU : RV01_JRPU
|
generic map(
|
generic map(
|
RAS_DEPTH => 4,
|
RAS_DEPTH => 4,
|
JRVQ_DEPTH => 2,
|
JRVQ_DEPTH => 2,
|
PXE => PARALLEL_EXECUTION_ENABLED,
|
PXE => PARALLEL_EXECUTION_ENABLED,
|
NW => NW
|
NW => NW
|
)
|
)
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
RST_i => IRST,
|
RST_i => IRST,
|
CLR_i => IX3_CLRP,
|
CLR_i => IX3_CLRP,
|
KLL1_i => IF2_KLL1,
|
KLL1_i => IF2_KLL1,
|
FSTLL_i => ID_PSTALL,
|
FSTLL_i => ID_PSTALL,
|
BJX_i => IX2_BJX,
|
BJX_i => IX2_BJX,
|
INSTR_i => INSTR_i,
|
INSTR_i => INSTR_i,
|
IF2_V_i => IF1_V_q,
|
IF2_V_i => IF1_V_q,
|
IF2_INSTR_i => IF2_DEC_INSTR,
|
IF2_INSTR_i => IF2_DEC_INSTR,
|
IF2_PC_i => IF1_PC_q,
|
IF2_PC_i => IF1_PC_q,
|
IX1_V_i => ID_V_q,
|
IX1_V_i => ID_V_q,
|
IX1_INSTR_i => ID_INSTR_q,
|
IX1_INSTR_i => ID_INSTR_q,
|
IX1_OPA0_i => ID_OPA0_q,
|
IX1_OPA0_i => ID_OPA0_q,
|
IX1_OPA1_i => ID_OPA1_q,
|
IX1_OPA1_i => ID_OPA1_q,
|
IX1_PCP4_i(0) => IX1_PC0P4,
|
IX1_PCP4_i(0) => IX1_PC0P4,
|
IX1_PCP4_i(1) => IX1_PC1P4,
|
IX1_PCP4_i(1) => IX1_PC1P4,
|
IX3_V_i => IX2_V_q,
|
IX3_V_i => IX2_V_q,
|
IX3_INSTR_i => IX2_INSTR_q,
|
IX3_INSTR_i => IX2_INSTR_q,
|
IX3_PCP4_i(0) => IX2_PC0P4_q,
|
IX3_PCP4_i(0) => IX2_PC0P4_q,
|
IX3_PCP4_i(1) => IX2_PC1P4_q,
|
IX3_PCP4_i(1) => IX2_PC1P4_q,
|
|
|
KLL1_o => IF2_JRKLL1,
|
KLL1_o => IF2_JRKLL1,
|
PJRX_o => IF2_PJRX,
|
PJRX_o => IF2_PJRX,
|
PJRTA_o => IF2_PJRTA,
|
PJRTA_o => IF2_PJRTA,
|
MPJRX_o => IX1_MPJRX
|
MPJRX_o => IX1_MPJRX
|
);
|
);
|
|
|
end generate;
|
end generate;
|
|
|
GJRPE_0 : if(JALR_PREDICTION_ENABLED = '0') generate
|
GJRPE_0 : if(JALR_PREDICTION_ENABLED = '0') generate
|
IF2_JRKLL1 <= '0';
|
IF2_JRKLL1 <= '0';
|
IF2_PJRX <= '0';
|
IF2_PJRX <= '0';
|
IF2_PJRTA <= (others => '0');
|
IF2_PJRTA <= (others => '0');
|
IX1_MPJRX <= "00";
|
IX1_MPJRX <= "00";
|
end generate;
|
end generate;
|
|
|
----------------------------------------------------
|
----------------------------------------------------
|
-- IF2 Stage
|
-- IF2 Stage
|
----------------------------------------------------
|
----------------------------------------------------
|
|
|
-- Split instruction memory output into two individual instructions
|
-- Split instruction memory output into two individual instructions
|
|
|
-- Note: slot #0 instrucion is forced to content of debug unit
|
-- Note: slot #0 instrucion is forced to content of debug unit
|
-- Stuff Instruction register when IF1_DFRCSI_q = '1'.
|
-- Stuff Instruction register when IF1_DFRCSI_q = '1'.
|
|
|
IF2_INSTR0 <=
|
IF2_INSTR0 <=
|
INSTR_i(ILEN*1-1 downto ILEN*0) when IF1_DFRCSI_q = '0' else WB_DSI;
|
INSTR_i(ILEN*1-1 downto ILEN*0) when IF1_DFRCSI_q = '0' else WB_DSI;
|
|
|
IF2_INSTR1 <=
|
IF2_INSTR1 <=
|
INSTR_i(ILEN*2-1 downto ILEN*1);
|
INSTR_i(ILEN*2-1 downto ILEN*1);
|
|
|
-- Pre-decode individual instructions
|
-- Pre-decode individual instructions
|
|
|
U_IDEC0 : RV01_IDEC
|
U_IDEC0 : RV01_IDEC
|
port map(
|
port map(
|
INSTR_i => IF2_INSTR0,
|
INSTR_i => IF2_INSTR0,
|
IADR_MIS_i => IF1_IADR_MIS_q(0),
|
IADR_MIS_i => IF1_IADR_MIS_q(0),
|
IADR_ERR_i => IADR_ERR_i,
|
IADR_ERR_i => IADR_ERR_i,
|
|
|
OPA_PC_o => IF2_OPA_PC(0),
|
OPA_PC_o => IF2_OPA_PC(0),
|
OPB_IMM_o => IF2_OPB_IMM(0),
|
OPB_IMM_o => IF2_OPB_IMM(0),
|
DEC_INSTR_o => IF2_DEC_INSTR(0)
|
DEC_INSTR_o => IF2_DEC_INSTR(0)
|
);
|
);
|
|
|
GPX_IF2_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
GPX_IF2_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
|
|
U_IDEC1 : RV01_IDEC
|
U_IDEC1 : RV01_IDEC
|
port map(
|
port map(
|
INSTR_i => IF2_INSTR1,
|
INSTR_i => IF2_INSTR1,
|
IADR_MIS_i => IF1_IADR_MIS_q(1),
|
IADR_MIS_i => IF1_IADR_MIS_q(1),
|
IADR_ERR_i => IADR_ERR_i,
|
IADR_ERR_i => IADR_ERR_i,
|
|
|
OPA_PC_o => IF2_OPA_PC(1),
|
OPA_PC_o => IF2_OPA_PC(1),
|
OPB_IMM_o => IF2_OPB_IMM(1),
|
OPB_IMM_o => IF2_OPB_IMM(1),
|
DEC_INSTR_o => IF2_DEC_INSTR(1)
|
DEC_INSTR_o => IF2_DEC_INSTR(1)
|
);
|
);
|
|
|
end generate;
|
end generate;
|
|
|
GPX_IF2_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
|
GPX_IF2_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
|
|
|
IF2_OPA_PC(1) <= '0';
|
IF2_OPA_PC(1) <= '0';
|
IF2_OPB_IMM(1) <= '0';
|
IF2_OPB_IMM(1) <= '0';
|
IF2_DEC_INSTR(1) <= DEC_NIL;
|
IF2_DEC_INSTR(1) <= DEC_NIL;
|
|
|
end generate;
|
end generate;
|
|
|
-- Exception processing: instruction address errors
|
-- Exception processing: instruction address errors
|
-- are reported by memory sub-system using IADR_ERR_i.
|
-- are reported by memory sub-system using IADR_ERR_i.
|
-- Illegal instructions are detected by decoding logic.
|
-- Illegal instructions are detected by decoding logic.
|
-- All type of exception raised up to this point are
|
-- All type of exception raised up to this point are
|
-- recorded by IF2_DEC_INSTR*.[EXCP,EIS,ECAUSE].
|
-- recorded by IF2_DEC_INSTR*.[EXCP,EIS,ECAUSE].
|
|
|
-- IF2 instruction valid bits (slot #1 instructions gets
|
-- IF2 instruction valid bits (slot #1 instructions gets
|
-- invalidated if slot #0 one is a predicted taken
|
-- invalidated if slot #0 one is a predicted taken
|
-- branch/jal or a jalr).
|
-- branch/jal or a jalr).
|
|
|
IF2_V(0) <= IF1_V_q(0);
|
IF2_V(0) <= IF1_V_q(0);
|
IF2_V(1) <= IF1_V_q(1) and not(IF2_KLL1) and not(IF2_JRKLL1);
|
IF2_V(1) <= IF1_V_q(1) and not(IF2_KLL1) and not(IF2_JRKLL1);
|
|
|
-- IFQ valid bits "kill" flag (instructions in the
|
-- IFQ valid bits "kill" flag (instructions in the
|
-- queue must be invalidated when a branch/jump is
|
-- queue must be invalidated when a branch/jump is
|
-- executed, an exception is raised or an instruction
|
-- executed, an exception is raised or an instruction
|
-- is re-fetched).
|
-- is re-fetched).
|
|
|
-- Instruction queue (includes pipeline registers
|
-- Instruction queue (includes pipeline registers
|
-- between IF2 and ID stages).
|
-- between IF2 and ID stages).
|
|
|
IF2_V_KILL <= IX2_BJX or IX3_CLRP;
|
IF2_V_KILL <= IX2_BJX or IX3_CLRP;
|
|
|
U_IFQ : RV01_IFQ
|
U_IFQ : RV01_IFQ
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
RST_i => IRST,
|
RST_i => IRST,
|
ID_HALT_i => IX3_HALT,
|
ID_HALT_i => IX3_HALT,
|
IX_BJX_i => IF2_V_KILL,
|
IX_BJX_i => IF2_V_KILL,
|
ID_ISSUE_i => ID_ISSUE,
|
ID_ISSUE_i => ID_ISSUE,
|
IF_V_i => IF2_V,
|
IF_V_i => IF2_V,
|
IF_PC0_i => IF1_PC_q(0),
|
IF_PC0_i => IF1_PC_q(0),
|
IF_PC1_i => IF1_PC_q(1),
|
IF_PC1_i => IF1_PC_q(1),
|
IF_INSTR0_i => IF2_INSTR0,
|
IF_INSTR0_i => IF2_INSTR0,
|
IF_INSTR1_i => IF2_INSTR1,
|
IF_INSTR1_i => IF2_INSTR1,
|
IF_DEC_INSTR0_i => IF2_DEC_INSTR(0),
|
IF_DEC_INSTR0_i => IF2_DEC_INSTR(0),
|
IF_DEC_INSTR1_i => IF2_DEC_INSTR(1),
|
IF_DEC_INSTR1_i => IF2_DEC_INSTR(1),
|
IF_OPA_PC0_i => IF2_OPA_PC(0),
|
IF_OPA_PC0_i => IF2_OPA_PC(0),
|
IF_OPA_PC1_i => IF2_OPA_PC(1),
|
IF_OPA_PC1_i => IF2_OPA_PC(1),
|
IF_OPB_IMM0_i => IF2_OPB_IMM(0),
|
IF_OPB_IMM0_i => IF2_OPB_IMM(0),
|
IF_OPB_IMM1_i => IF2_OPB_IMM(1),
|
IF_OPB_IMM1_i => IF2_OPB_IMM(1),
|
IF_BPVD0_i => IF2_BPVD0,
|
IF_BPVD0_i => IF2_BPVD0,
|
IF_BPVD1_i => IF2_BPVD1,
|
IF_BPVD1_i => IF2_BPVD1,
|
|
|
PSTALL_o => ID_PSTALL,
|
PSTALL_o => ID_PSTALL,
|
ID_V_o => IF2_V_q,
|
ID_V_o => IF2_V_q,
|
ID_PC0_o => IF2_PC_q(0),
|
ID_PC0_o => IF2_PC_q(0),
|
ID_PC1_o => IF2_PC_q(1),
|
ID_PC1_o => IF2_PC_q(1),
|
ID_INSTR0_o => open,
|
ID_INSTR0_o => open,
|
ID_INSTR1_o => open,
|
ID_INSTR1_o => open,
|
ID_DEC_INSTR0_o => IF2_DEC_INSTR_q(0),
|
ID_DEC_INSTR0_o => IF2_DEC_INSTR_q(0),
|
ID_DEC_INSTR1_o => IF2_DEC_INSTR_q(1),
|
ID_DEC_INSTR1_o => IF2_DEC_INSTR_q(1),
|
ID_OPA_PC0_o => IF2_OPA_PC_q(0),
|
ID_OPA_PC0_o => IF2_OPA_PC_q(0),
|
ID_OPA_PC1_o => IF2_OPA_PC_q(1),
|
ID_OPA_PC1_o => IF2_OPA_PC_q(1),
|
ID_OPB_IMM0_o => IF2_OPB_IMM_q(0),
|
ID_OPB_IMM0_o => IF2_OPB_IMM_q(0),
|
ID_OPB_IMM1_o => IF2_OPB_IMM_q(1),
|
ID_OPB_IMM1_o => IF2_OPB_IMM_q(1),
|
ID_BPVD0_o => IF2_BPVD0_q,
|
ID_BPVD0_o => IF2_BPVD0_q,
|
ID_BPVD1_o => IF2_BPVD1_q
|
ID_BPVD1_o => IF2_BPVD1_q
|
);
|
);
|
|
|
----------------------------------------------------
|
----------------------------------------------------
|
-- ID Stage
|
-- ID Stage
|
----------------------------------------------------
|
----------------------------------------------------
|
|
|
-- Pipeline stall logic
|
-- Pipeline stall logic
|
|
|
U_PSTL0 : RV01_PSTLLOG_2W_P6
|
U_PSTL0 : RV01_PSTLLOG_2W_P6
|
generic map(
|
generic map(
|
DXE => DELAYED_EXECUTION_ENABLED,
|
DXE => DELAYED_EXECUTION_ENABLED,
|
SIMULATION_ONLY => SIMULATION_ONLY
|
SIMULATION_ONLY => SIMULATION_ONLY
|
)
|
)
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
ID_INSTR_i => IF2_DEC_INSTR_q(0),
|
ID_INSTR_i => IF2_DEC_INSTR_q(0),
|
ID_V_i => IF2_V_q(0),
|
ID_V_i => IF2_V_q(0),
|
IX1_INSTR0_i => ID_INSTR_q(0),
|
IX1_INSTR0_i => ID_INSTR_q(0),
|
IX1_INSTR1_i => ID_INSTR_q(1),
|
IX1_INSTR1_i => ID_INSTR_q(1),
|
IX1_V_i => ID_V_q,
|
IX1_V_i => ID_V_q,
|
IX1_FWDE_i => ID_FWDX_q,
|
IX1_FWDE_i => ID_FWDX_q,
|
IX2_INSTR0_i => IX1_INSTR_q(0),
|
IX2_INSTR0_i => IX1_INSTR_q(0),
|
IX2_INSTR1_i => IX1_INSTR_q(1),
|
IX2_INSTR1_i => IX1_INSTR_q(1),
|
IX2_V_i => IX1_V_q,
|
IX2_V_i => IX1_V_q,
|
IX2_FWDE_i => IX1_FWDX_q,
|
IX2_FWDE_i => IX1_FWDX_q,
|
IX3_INSTR0_i => IX2_INSTR_q(0),
|
IX3_INSTR0_i => IX2_INSTR_q(0),
|
IX3_INSTR1_i => IX2_INSTR_q(1),
|
IX3_INSTR1_i => IX2_INSTR_q(1),
|
IX3_V_i => IX2_V_q,
|
IX3_V_i => IX2_V_q,
|
IX3_FWDE_i => IX2_FWDX_q,
|
IX3_FWDE_i => IX2_FWDX_q,
|
|
|
OPA_V_o => ID_OPA0_V,
|
OPA_V_o => ID_OPA0_V,
|
OPB_V_o => ID_OPB0_V,
|
OPB_V_o => ID_OPB0_V,
|
DSA_o => ID_DSA0,
|
DSA_o => ID_DSA0,
|
DSB_o => ID_DSB0,
|
DSB_o => ID_DSB0,
|
PSTALL_o => ID_PS(0)
|
PSTALL_o => ID_PS(0)
|
);
|
);
|
|
|
GPX_ID_0_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
GPX_ID_0_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
|
|
U_PSTL1 : RV01_PSTLLOG_2W_P6
|
U_PSTL1 : RV01_PSTLLOG_2W_P6
|
generic map(
|
generic map(
|
DXE => DELAYED_EXECUTION_ENABLED,
|
DXE => DELAYED_EXECUTION_ENABLED,
|
SIMULATION_ONLY => SIMULATION_ONLY
|
SIMULATION_ONLY => SIMULATION_ONLY
|
)
|
)
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
ID_INSTR_i => IF2_DEC_INSTR_q(1),
|
ID_INSTR_i => IF2_DEC_INSTR_q(1),
|
ID_V_i => IF2_V_q(1),
|
ID_V_i => IF2_V_q(1),
|
IX1_INSTR0_i => ID_INSTR_q(0),
|
IX1_INSTR0_i => ID_INSTR_q(0),
|
IX1_INSTR1_i => ID_INSTR_q(1),
|
IX1_INSTR1_i => ID_INSTR_q(1),
|
IX1_V_i => ID_V_q,
|
IX1_V_i => ID_V_q,
|
IX1_FWDE_i => ID_FWDX_q,
|
IX1_FWDE_i => ID_FWDX_q,
|
IX2_INSTR0_i => IX1_INSTR_q(0),
|
IX2_INSTR0_i => IX1_INSTR_q(0),
|
IX2_INSTR1_i => IX1_INSTR_q(1),
|
IX2_INSTR1_i => IX1_INSTR_q(1),
|
IX2_V_i => IX1_V_q,
|
IX2_V_i => IX1_V_q,
|
IX2_FWDE_i => IX1_FWDX_q,
|
IX2_FWDE_i => IX1_FWDX_q,
|
IX3_INSTR0_i => IX2_INSTR_q(0),
|
IX3_INSTR0_i => IX2_INSTR_q(0),
|
IX3_INSTR1_i => IX2_INSTR_q(1),
|
IX3_INSTR1_i => IX2_INSTR_q(1),
|
IX3_V_i => IX2_V_q,
|
IX3_V_i => IX2_V_q,
|
IX3_FWDE_i => IX2_FWDX_q,
|
IX3_FWDE_i => IX2_FWDX_q,
|
|
|
OPA_V_o => ID_OPA1_V,
|
OPA_V_o => ID_OPA1_V,
|
OPB_V_o => ID_OPB1_V,
|
OPB_V_o => ID_OPB1_V,
|
DSA_o => ID_DSA1,
|
DSA_o => ID_DSA1,
|
DSB_o => ID_DSB1,
|
DSB_o => ID_DSB1,
|
PSTALL_o => ID_PS(1)
|
PSTALL_o => ID_PS(1)
|
);
|
);
|
|
|
end generate;
|
end generate;
|
|
|
GPX_ID_0_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
|
GPX_ID_0_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
|
|
|
ID_OPA1_V <= '0';
|
ID_OPA1_V <= '0';
|
ID_OPB1_V <= '0';
|
ID_OPB1_V <= '0';
|
ID_DSA1 <= '0';
|
ID_DSA1 <= '0';
|
ID_DSB1 <= '0';
|
ID_DSB1 <= '0';
|
ID_PS(1) <= '0';
|
ID_PS(1) <= '0';
|
|
|
end generate;
|
end generate;
|
|
|
-- Parallel eXecution logic
|
-- Parallel eXecution logic
|
|
|
GPX_ID_1_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
GPX_ID_1_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
|
|
U_PXLOG : RV01_PXLOG
|
U_PXLOG : RV01_PXLOG
|
port map(
|
port map(
|
ID_INSTR0_i => IF2_DEC_INSTR_q(0),
|
ID_INSTR0_i => IF2_DEC_INSTR_q(0),
|
ID_INSTR1_i => IF2_DEC_INSTR_q(1),
|
ID_INSTR1_i => IF2_DEC_INSTR_q(1),
|
ID_V_i => IF2_V_q(2-1 downto 0),
|
ID_V_i => IF2_V_q(2-1 downto 0),
|
ID_FWDE_i => ID_FWDE,
|
ID_FWDE_i => ID_FWDE,
|
|
|
PXE1_o => ID_PXE1
|
PXE1_o => ID_PXE1
|
);
|
);
|
|
|
end generate;
|
end generate;
|
|
|
GPX_ID_1_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
|
GPX_ID_1_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
|
|
|
ID_PXE1 <= '0';
|
ID_PXE1 <= '0';
|
|
|
end generate;
|
end generate;
|
|
|
-- Instruction issue logic
|
-- Instruction issue logic
|
|
|
U_ISSLOG: RV01_ISSLOG
|
U_ISSLOG: RV01_ISSLOG
|
generic map(
|
generic map(
|
NW => NW
|
NW => NW
|
)
|
)
|
port map(
|
port map(
|
V_i => IF2_V_q,
|
V_i => IF2_V_q,
|
BJX_i => IX2_BJX,
|
BJX_i => IX2_BJX,
|
PC1_i => IF2_PC_q(1),
|
PC1_i => IF2_PC_q(1),
|
PS_i => ID_PS,
|
PS_i => ID_PS,
|
SBF_i => IX1_SBF,
|
SBF_i => IX1_SBF,
|
DIV_STRT_i => IX1_DIV_STRT,
|
DIV_STRT_i => IX1_DIV_STRT,
|
DIV_BSY_i => ID_DIV_BSY,
|
DIV_BSY_i => ID_DIV_BSY,
|
SEQX_i => IF2_DEC_INSTR_q(0).SEQX,
|
SEQX_i => IF2_DEC_INSTR_q(0).SEQX,
|
PXE_i => WB_PXE,
|
PXE_i => WB_PXE,
|
PXE1_i => ID_PXE1,
|
PXE1_i => ID_PXE1,
|
STEP_i => IX2_STEP,
|
STEP_i => IX2_STEP,
|
PSLP_i => IX1_PSLP,
|
PSLP_i => IX1_PSLP,
|
|
|
V_o => ID_V,
|
V_o => ID_V,
|
JLRA_o => ID_JLRA,
|
JLRA_o => ID_JLRA,
|
ISSUE_o => ID_ISSUE
|
ISSUE_o => ID_ISSUE
|
);
|
);
|
|
|
-- Instruction #0 Operand A forward logic
|
-- Instruction #0 Operand A forward logic
|
|
|
U_FWDLOGA0 : RV01_FWDLOG_2W_P6
|
U_FWDLOGA0 : RV01_FWDLOG_2W_P6
|
port map(
|
port map(
|
ID_RX_i => IF2_DEC_INSTR_q(0).RS1,
|
ID_RX_i => IF2_DEC_INSTR_q(0).RS1,
|
ID_RRX_i => IF2_DEC_INSTR_q(0).RRS1,
|
ID_RRX_i => IF2_DEC_INSTR_q(0).RRS1,
|
IX1_INSTR0_i => ID_INSTR_q(0),
|
IX1_INSTR0_i => ID_INSTR_q(0),
|
IX2_INSTR0_i => IX1_INSTR_q(0),
|
IX2_INSTR0_i => IX1_INSTR_q(0),
|
IX3_INSTR0_i => IX2_INSTR_q(0),
|
IX3_INSTR0_i => IX2_INSTR_q(0),
|
IX1_INSTR1_i => ID_INSTR_q(1),
|
IX1_INSTR1_i => ID_INSTR_q(1),
|
IX2_INSTR1_i => IX1_INSTR_q(1),
|
IX2_INSTR1_i => IX1_INSTR_q(1),
|
IX3_INSTR1_i => IX2_INSTR_q(1),
|
IX3_INSTR1_i => IX2_INSTR_q(1),
|
IX1_PA_RES0_i => IX1_PA0_RES,
|
IX1_PA_RES0_i => IX1_PA0_RES,
|
IX1_PA_RES1_i => IX1_PA1_RES,
|
IX1_PA_RES1_i => IX1_PA1_RES,
|
IX2_PA_RES0_i => IX2_PA0_RES,
|
IX2_PA_RES0_i => IX2_PA0_RES,
|
IX2_PA_RES1_i => IX2_PA1_RES,
|
IX2_PA_RES1_i => IX2_PA1_RES,
|
IX3_PA_RES0_i => IX3_DRD0,
|
IX3_PA_RES0_i => IX3_DRD0,
|
IX3_PA_RES1_i => IX3_DRD1,
|
IX3_PA_RES1_i => IX3_DRD1,
|
ID_OPX_NOFWD_i => to_signed(WB_RDA0),
|
ID_OPX_NOFWD_i => to_signed(WB_RDA0),
|
IX1_V_i => ID_V_q,
|
IX1_V_i => ID_V_q,
|
IX2_V_i => IX1_V_q,
|
IX2_V_i => IX1_V_q,
|
IX3_V_i => IX2_V_q,
|
IX3_V_i => IX2_V_q,
|
IX1_FWDE_i => ID_FWDX_q,
|
IX1_FWDE_i => ID_FWDX_q,
|
IX2_FWDE_i => IX1_FWDX_q,
|
IX2_FWDE_i => IX1_FWDX_q,
|
IX3_FWDE_i => IX2_FWDX_q,
|
IX3_FWDE_i => IX2_FWDX_q,
|
NOREGS_i => IF2_OPA_PC_q(0),
|
NOREGS_i => IF2_OPA_PC_q(0),
|
NOREGD_i => to_signed(ID_JLRA(0)),
|
NOREGD_i => to_signed(ID_JLRA(0)),
|
|
|
ID_OPX_o => ID_OPA0
|
ID_OPX_o => ID_OPA0
|
);
|
);
|
|
|
-- Instruction #1 Operand A forward logic
|
-- Instruction #1 Operand A forward logic
|
|
|
GPX_ID_2_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
GPX_ID_2_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
|
|
U_FWDLOGA1 : RV01_FWDLOG_2W_P6
|
U_FWDLOGA1 : RV01_FWDLOG_2W_P6
|
port map(
|
port map(
|
ID_RX_i => IF2_DEC_INSTR_q(1).RS1,
|
ID_RX_i => IF2_DEC_INSTR_q(1).RS1,
|
ID_RRX_i => IF2_DEC_INSTR_q(1).RRS1,
|
ID_RRX_i => IF2_DEC_INSTR_q(1).RRS1,
|
IX1_INSTR0_i => ID_INSTR_q(0),
|
IX1_INSTR0_i => ID_INSTR_q(0),
|
IX2_INSTR0_i => IX1_INSTR_q(0),
|
IX2_INSTR0_i => IX1_INSTR_q(0),
|
IX3_INSTR0_i => IX2_INSTR_q(0),
|
IX3_INSTR0_i => IX2_INSTR_q(0),
|
IX1_INSTR1_i => ID_INSTR_q(1),
|
IX1_INSTR1_i => ID_INSTR_q(1),
|
IX2_INSTR1_i => IX1_INSTR_q(1),
|
IX2_INSTR1_i => IX1_INSTR_q(1),
|
IX3_INSTR1_i => IX2_INSTR_q(1),
|
IX3_INSTR1_i => IX2_INSTR_q(1),
|
IX1_PA_RES0_i => IX1_PA0_RES,
|
IX1_PA_RES0_i => IX1_PA0_RES,
|
IX1_PA_RES1_i => IX1_PA1_RES,
|
IX1_PA_RES1_i => IX1_PA1_RES,
|
IX2_PA_RES0_i => IX2_PA0_RES,
|
IX2_PA_RES0_i => IX2_PA0_RES,
|
IX2_PA_RES1_i => IX2_PA1_RES,
|
IX2_PA_RES1_i => IX2_PA1_RES,
|
IX3_PA_RES0_i => IX3_DRD0,
|
IX3_PA_RES0_i => IX3_DRD0,
|
IX3_PA_RES1_i => IX3_DRD1,
|
IX3_PA_RES1_i => IX3_DRD1,
|
ID_OPX_NOFWD_i => to_signed(WB_RDA1),
|
ID_OPX_NOFWD_i => to_signed(WB_RDA1),
|
IX1_V_i => ID_V_q,
|
IX1_V_i => ID_V_q,
|
IX2_V_i => IX1_V_q,
|
IX2_V_i => IX1_V_q,
|
IX3_V_i => IX2_V_q,
|
IX3_V_i => IX2_V_q,
|
IX1_FWDE_i => ID_FWDX_q,
|
IX1_FWDE_i => ID_FWDX_q,
|
IX2_FWDE_i => IX1_FWDX_q,
|
IX2_FWDE_i => IX1_FWDX_q,
|
IX3_FWDE_i => IX2_FWDX_q,
|
IX3_FWDE_i => IX2_FWDX_q,
|
NOREGS_i => IF2_OPA_PC_q(1),
|
NOREGS_i => IF2_OPA_PC_q(1),
|
NOREGD_i => to_signed(ID_JLRA(1)),
|
NOREGD_i => to_signed(ID_JLRA(1)),
|
|
|
ID_OPX_o => ID_OPA1
|
ID_OPX_o => ID_OPA1
|
);
|
);
|
|
|
end generate;
|
end generate;
|
|
|
GPX_ID_2_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
|
GPX_ID_2_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
|
|
|
ID_OPA1 <= (others => '0');
|
ID_OPA1 <= (others => '0');
|
|
|
end generate;
|
end generate;
|
|
|
-- Instruction #0 Operand B forward logic
|
-- Instruction #0 Operand B forward logic
|
|
|
U_FWDLOGB0 : RV01_FWDLOG_2W_P6
|
U_FWDLOGB0 : RV01_FWDLOG_2W_P6
|
port map(
|
port map(
|
ID_RX_i => IF2_DEC_INSTR_q(0).RS2,
|
ID_RX_i => IF2_DEC_INSTR_q(0).RS2,
|
ID_RRX_i => IF2_DEC_INSTR_q(0).RRS2,
|
ID_RRX_i => IF2_DEC_INSTR_q(0).RRS2,
|
IX1_INSTR0_i => ID_INSTR_q(0),
|
IX1_INSTR0_i => ID_INSTR_q(0),
|
IX2_INSTR0_i => IX1_INSTR_q(0),
|
IX2_INSTR0_i => IX1_INSTR_q(0),
|
IX3_INSTR0_i => IX2_INSTR_q(0),
|
IX3_INSTR0_i => IX2_INSTR_q(0),
|
IX1_INSTR1_i => ID_INSTR_q(1),
|
IX1_INSTR1_i => ID_INSTR_q(1),
|
IX2_INSTR1_i => IX1_INSTR_q(1),
|
IX2_INSTR1_i => IX1_INSTR_q(1),
|
IX3_INSTR1_i => IX2_INSTR_q(1),
|
IX3_INSTR1_i => IX2_INSTR_q(1),
|
IX1_PA_RES0_i => IX1_PA0_RES,
|
IX1_PA_RES0_i => IX1_PA0_RES,
|
IX1_PA_RES1_i => IX1_PA1_RES,
|
IX1_PA_RES1_i => IX1_PA1_RES,
|
IX2_PA_RES0_i => IX2_PA0_RES,
|
IX2_PA_RES0_i => IX2_PA0_RES,
|
IX2_PA_RES1_i => IX2_PA1_RES,
|
IX2_PA_RES1_i => IX2_PA1_RES,
|
IX3_PA_RES0_i => IX3_DRD0,
|
IX3_PA_RES0_i => IX3_DRD0,
|
IX3_PA_RES1_i => IX3_DRD1,
|
IX3_PA_RES1_i => IX3_DRD1,
|
ID_OPX_NOFWD_i => to_signed(WB_RDB0),
|
ID_OPX_NOFWD_i => to_signed(WB_RDB0),
|
IX1_V_i => ID_V_q,
|
IX1_V_i => ID_V_q,
|
IX2_V_i => IX1_V_q,
|
IX2_V_i => IX1_V_q,
|
IX3_V_i => IX2_V_q,
|
IX3_V_i => IX2_V_q,
|
IX1_FWDE_i => ID_FWDX_q,
|
IX1_FWDE_i => ID_FWDX_q,
|
IX2_FWDE_i => IX1_FWDX_q,
|
IX2_FWDE_i => IX1_FWDX_q,
|
IX3_FWDE_i => IX2_FWDX_q,
|
IX3_FWDE_i => IX2_FWDX_q,
|
NOREGS_i => IF2_OPB_IMM_q(0),
|
NOREGS_i => IF2_OPB_IMM_q(0),
|
NOREGD_i => IF2_DEC_INSTR_q(0).IMM,
|
NOREGD_i => IF2_DEC_INSTR_q(0).IMM,
|
|
|
ID_OPX_o => ID_OPB0
|
ID_OPX_o => ID_OPB0
|
);
|
);
|
|
|
-- Instruction #1 Operand B forward logic
|
-- Instruction #1 Operand B forward logic
|
|
|
GPX_ID_3_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
GPX_ID_3_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
|
|
U_FWDLOGB1 : RV01_FWDLOG_2W_P6
|
U_FWDLOGB1 : RV01_FWDLOG_2W_P6
|
port map(
|
port map(
|
ID_RX_i => IF2_DEC_INSTR_q(1).RS2,
|
ID_RX_i => IF2_DEC_INSTR_q(1).RS2,
|
ID_RRX_i => IF2_DEC_INSTR_q(1).RRS2,
|
ID_RRX_i => IF2_DEC_INSTR_q(1).RRS2,
|
IX1_INSTR0_i => ID_INSTR_q(0),
|
IX1_INSTR0_i => ID_INSTR_q(0),
|
IX2_INSTR0_i => IX1_INSTR_q(0),
|
IX2_INSTR0_i => IX1_INSTR_q(0),
|
IX3_INSTR0_i => IX2_INSTR_q(0),
|
IX3_INSTR0_i => IX2_INSTR_q(0),
|
IX1_INSTR1_i => ID_INSTR_q(1),
|
IX1_INSTR1_i => ID_INSTR_q(1),
|
IX2_INSTR1_i => IX1_INSTR_q(1),
|
IX2_INSTR1_i => IX1_INSTR_q(1),
|
IX3_INSTR1_i => IX2_INSTR_q(1),
|
IX3_INSTR1_i => IX2_INSTR_q(1),
|
IX1_PA_RES0_i => IX1_PA0_RES,
|
IX1_PA_RES0_i => IX1_PA0_RES,
|
IX1_PA_RES1_i => IX1_PA1_RES,
|
IX1_PA_RES1_i => IX1_PA1_RES,
|
IX2_PA_RES0_i => IX2_PA0_RES,
|
IX2_PA_RES0_i => IX2_PA0_RES,
|
IX2_PA_RES1_i => IX2_PA1_RES,
|
IX2_PA_RES1_i => IX2_PA1_RES,
|
IX3_PA_RES0_i => IX3_DRD0,
|
IX3_PA_RES0_i => IX3_DRD0,
|
IX3_PA_RES1_i => IX3_DRD1,
|
IX3_PA_RES1_i => IX3_DRD1,
|
ID_OPX_NOFWD_i => to_signed(WB_RDB1),
|
ID_OPX_NOFWD_i => to_signed(WB_RDB1),
|
IX1_V_i => ID_V_q,
|
IX1_V_i => ID_V_q,
|
IX2_V_i => IX1_V_q,
|
IX2_V_i => IX1_V_q,
|
IX3_V_i => IX2_V_q,
|
IX3_V_i => IX2_V_q,
|
IX1_FWDE_i => ID_FWDX_q,
|
IX1_FWDE_i => ID_FWDX_q,
|
IX2_FWDE_i => IX1_FWDX_q,
|
IX2_FWDE_i => IX1_FWDX_q,
|
IX3_FWDE_i => IX2_FWDX_q,
|
IX3_FWDE_i => IX2_FWDX_q,
|
NOREGS_i => IF2_OPB_IMM_q(1),
|
NOREGS_i => IF2_OPB_IMM_q(1),
|
NOREGD_i => IF2_DEC_INSTR_q(1).IMM,
|
NOREGD_i => IF2_DEC_INSTR_q(1).IMM,
|
|
|
ID_OPX_o => ID_OPB1
|
ID_OPX_o => ID_OPB1
|
);
|
);
|
|
|
end generate;
|
end generate;
|
|
|
GPX_ID_3_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
|
GPX_ID_3_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
|
|
|
ID_OPB1 <= (others => '0');
|
ID_OPB1 <= (others => '0');
|
|
|
end generate;
|
end generate;
|
|
|
-- Pipeline-A (dedicated) pre-decoder
|
-- Pipeline-A (dedicated) pre-decoder
|
|
|
U_PADEC0 : RV01_PIPE_A_DEC
|
U_PADEC0 : RV01_PIPE_A_DEC
|
port map(
|
port map(
|
INSTR_i => IF2_DEC_INSTR_q(0),
|
INSTR_i => IF2_DEC_INSTR_q(0),
|
|
|
FWDE_o => ID_FWDE(0),
|
FWDE_o => ID_FWDE(0),
|
SEL_o => ID_PASEL0
|
SEL_o => ID_PASEL0
|
);
|
);
|
|
|
GPX_ID_4_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
GPX_ID_4_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
|
|
U_PADEC1 : RV01_PIPE_A_DEC
|
U_PADEC1 : RV01_PIPE_A_DEC
|
port map(
|
port map(
|
INSTR_i => IF2_DEC_INSTR_q(1),
|
INSTR_i => IF2_DEC_INSTR_q(1),
|
|
|
FWDE_o => ID_FWDE(1),
|
FWDE_o => ID_FWDE(1),
|
SEL_o => ID_PASEL1
|
SEL_o => ID_PASEL1
|
);
|
);
|
|
|
end generate;
|
end generate;
|
|
|
GPX_ID_4_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
|
GPX_ID_4_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
|
|
|
ID_FWDE(1) <= '0';
|
ID_FWDE(1) <= '0';
|
ID_PASEL1 <= (others => '0');
|
ID_PASEL1 <= (others => '0');
|
|
|
end generate;
|
end generate;
|
|
|
-- Pipeline Registers
|
-- Pipeline Registers
|
|
|
process(CLK_i)
|
process(CLK_i)
|
begin
|
begin
|
if(CLK_i = '1' and CLK_i'event) then
|
if(CLK_i = '1' and CLK_i'event) then
|
if(IRST = '1' or IX3_CLRP = '1') then
|
if(IRST = '1' or IX3_CLRP = '1') then
|
ID_V_q <= "00";
|
ID_V_q <= "00";
|
else
|
else
|
ID_V_q(0) <= ID_V(0);
|
ID_V_q(0) <= ID_V(0);
|
ID_V_q(1) <= ID_V(1) or (IX1_PSLP and not(IX2_BJX));
|
ID_V_q(1) <= ID_V(1) or (IX1_PSLP and not(IX2_BJX));
|
end if;
|
end if;
|
ID_PC_q(0) <= IF2_PC_q(0);
|
ID_PC_q(0) <= IF2_PC_q(0);
|
ID_INSTR_q(0) <= IF2_DEC_INSTR_q(0);
|
ID_INSTR_q(0) <= IF2_DEC_INSTR_q(0);
|
ID_OPA0_q <= ID_OPA0;
|
ID_OPA0_q <= ID_OPA0;
|
ID_OPB0_q <= ID_OPB0;
|
ID_OPB0_q <= ID_OPB0;
|
ID_FWDE_q(0) <= ID_FWDE(0);
|
ID_FWDE_q(0) <= ID_FWDE(0);
|
ID_FWDX_q(0) <= ID_FWDE(0) and ID_OPA0_V and ID_OPB0_V;
|
ID_FWDX_q(0) <= ID_FWDE(0) and ID_OPA0_V and ID_OPB0_V;
|
ID_PASEL0_q <= ID_PASEL0;
|
ID_PASEL0_q <= ID_PASEL0;
|
ID_BPVD0_q <= IF2_BPVD0_q;
|
ID_BPVD0_q <= IF2_BPVD0_q;
|
ID_OPA0_V_q <= ID_OPA0_V;
|
ID_OPA0_V_q <= ID_OPA0_V;
|
ID_OPB0_V_q <= ID_OPB0_V;
|
ID_OPB0_V_q <= ID_OPB0_V;
|
ID_DSA0_q <= ID_DSA0;
|
ID_DSA0_q <= ID_DSA0;
|
ID_DSB0_q <= ID_DSB0;
|
ID_DSB0_q <= ID_DSB0;
|
if(IX1_PSLP = '0') then
|
if(IX1_PSLP = '0') then
|
ID_PC_q(1) <= IF2_PC_q(1);
|
ID_PC_q(1) <= IF2_PC_q(1);
|
ID_INSTR_q(1) <= IF2_DEC_INSTR_q(1);
|
ID_INSTR_q(1) <= IF2_DEC_INSTR_q(1);
|
ID_OPA1_q <= ID_OPA1;
|
ID_OPA1_q <= ID_OPA1;
|
ID_OPB1_q <= ID_OPB1;
|
ID_OPB1_q <= ID_OPB1;
|
ID_FWDE_q(1) <= ID_FWDE(1);
|
ID_FWDE_q(1) <= ID_FWDE(1);
|
ID_FWDX_q(1) <= ID_FWDE(1) and ID_OPA1_V and ID_OPB1_V;
|
ID_FWDX_q(1) <= ID_FWDE(1) and ID_OPA1_V and ID_OPB1_V;
|
ID_PASEL1_q <= ID_PASEL1;
|
ID_PASEL1_q <= ID_PASEL1;
|
ID_BPVD1_q <= IF2_BPVD1_q;
|
ID_BPVD1_q <= IF2_BPVD1_q;
|
ID_OPA1_V_q <= ID_OPA1_V;
|
ID_OPA1_V_q <= ID_OPA1_V;
|
ID_OPB1_V_q <= ID_OPB1_V;
|
ID_OPB1_V_q <= ID_OPB1_V;
|
ID_DSA1_q <= ID_DSA1;
|
ID_DSA1_q <= ID_DSA1;
|
ID_DSB1_q <= ID_DSB1;
|
ID_DSB1_q <= ID_DSB1;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
----------------------------------------------------
|
----------------------------------------------------
|
-- IX1 Stage
|
-- IX1 Stage
|
----------------------------------------------------
|
----------------------------------------------------
|
|
|
-- Pipeline-A
|
-- Pipeline-A
|
|
|
-- Delayed Execution pipeline-A
|
-- Delayed Execution pipeline-A
|
|
|
U_PA0ALU_X1: RV01_PIPE_A_ALU
|
U_PA0ALU_X1: RV01_PIPE_A_ALU
|
port map(
|
port map(
|
SEL_i => ID_PASEL0_q,
|
SEL_i => ID_PASEL0_q,
|
SU_i => ID_INSTR_q(0).SU,
|
SU_i => ID_INSTR_q(0).SU,
|
OP_i => ID_INSTR_q(0).ALU_OP,
|
OP_i => ID_INSTR_q(0).ALU_OP,
|
OPA_i => ID_OPA0_q,
|
OPA_i => ID_OPA0_q,
|
OPB_i => ID_OPB0_q,
|
OPB_i => ID_OPB0_q,
|
|
|
RES_o => IX1_PA0_ALU_RES
|
RES_o => IX1_PA0_ALU_RES
|
);
|
);
|
|
|
GPX_X1_1_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
GPX_X1_1_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
|
|
U_PA1ALU_X1: RV01_PIPE_A_ALU
|
U_PA1ALU_X1: RV01_PIPE_A_ALU
|
port map(
|
port map(
|
SEL_i => ID_PASEL1_q,
|
SEL_i => ID_PASEL1_q,
|
SU_i => ID_INSTR_q(1).SU,
|
SU_i => ID_INSTR_q(1).SU,
|
OP_i => ID_INSTR_q(1).ALU_OP,
|
OP_i => ID_INSTR_q(1).ALU_OP,
|
OPA_i => ID_OPA1_q,
|
OPA_i => ID_OPA1_q,
|
OPB_i => ID_OPB1_q,
|
OPB_i => ID_OPB1_q,
|
|
|
RES_o => IX1_PA1_ALU_RES
|
RES_o => IX1_PA1_ALU_RES
|
);
|
);
|
|
|
end generate; -- GPX_X1_1_1
|
end generate; -- GPX_X1_1_1
|
|
|
IX1_SHFT0 <= to_unsigned(ID_OPB0_q(5-1 downto 0));
|
IX1_SHFT0 <= to_unsigned(ID_OPB0_q(5-1 downto 0));
|
|
|
process(ID_INSTR_q(0))
|
process(ID_INSTR_q(0))
|
begin
|
begin
|
case ID_INSTR_q(0).ALU_OP is
|
case ID_INSTR_q(0).ALU_OP is
|
when ALU_SHL =>
|
when ALU_SHL =>
|
IX1_SHF_CTRL0 <= SC_SHL;
|
IX1_SHF_CTRL0 <= SC_SHL;
|
when ALU_SHR =>
|
when ALU_SHR =>
|
IX1_SHF_CTRL0 <= SC_SHR;
|
IX1_SHF_CTRL0 <= SC_SHR;
|
when others =>
|
when others =>
|
IX1_SHF_CTRL0 <= SC_NIL;
|
IX1_SHF_CTRL0 <= SC_NIL;
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
U_SHF0 : RV01_SHFTU
|
U_SHF0 : RV01_SHFTU
|
port map(
|
port map(
|
CTRL_i => IX1_SHF_CTRL0,
|
CTRL_i => IX1_SHF_CTRL0,
|
SI_i => ID_OPA0_q,
|
SI_i => ID_OPA0_q,
|
SHFT_i => IX1_SHFT0,
|
SHFT_i => IX1_SHFT0,
|
SU_i => ID_INSTR_q(0).SU,
|
SU_i => ID_INSTR_q(0).SU,
|
|
|
SO_o => IX1_SHF_RES0
|
SO_o => IX1_SHF_RES0
|
);
|
);
|
|
|
GPX_X1_2_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
GPX_X1_2_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
|
|
IX1_SHFT1 <= to_unsigned(ID_OPB1_q(5-1 downto 0));
|
IX1_SHFT1 <= to_unsigned(ID_OPB1_q(5-1 downto 0));
|
|
|
process(ID_INSTR_q(1))
|
process(ID_INSTR_q(1))
|
begin
|
begin
|
case ID_INSTR_q(1).ALU_OP is
|
case ID_INSTR_q(1).ALU_OP is
|
when ALU_SHL =>
|
when ALU_SHL =>
|
IX1_SHF_CTRL1 <= SC_SHL;
|
IX1_SHF_CTRL1 <= SC_SHL;
|
when ALU_SHR =>
|
when ALU_SHR =>
|
IX1_SHF_CTRL1 <= SC_SHR;
|
IX1_SHF_CTRL1 <= SC_SHR;
|
when others =>
|
when others =>
|
IX1_SHF_CTRL1 <= SC_NIL;
|
IX1_SHF_CTRL1 <= SC_NIL;
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
U_SHF1 : RV01_SHFTU
|
U_SHF1 : RV01_SHFTU
|
port map(
|
port map(
|
CTRL_i => IX1_SHF_CTRL1,
|
CTRL_i => IX1_SHF_CTRL1,
|
SI_i => ID_OPA1_q,
|
SI_i => ID_OPA1_q,
|
SHFT_i => IX1_SHFT1,
|
SHFT_i => IX1_SHFT1,
|
SU_i => ID_INSTR_q(1).SU,
|
SU_i => ID_INSTR_q(1).SU,
|
|
|
SO_o => IX1_SHF_RES1
|
SO_o => IX1_SHF_RES1
|
);
|
);
|
|
|
end generate; -- GPX_X1_2_1
|
end generate; -- GPX_X1_2_1
|
|
|
GDX1_1 : if(DELAYED_EXECUTION_ENABLED = '1') generate
|
GDX1_1 : if(DELAYED_EXECUTION_ENABLED = '1') generate
|
|
|
-- DX Pipe registers (IX1->IX2)
|
-- DX Pipe registers (IX1->IX2)
|
|
|
process(CLK_i)
|
process(CLK_i)
|
begin
|
begin
|
if(CLK_i = '1' and CLK_i'event) then
|
if(CLK_i = '1' and CLK_i'event) then
|
if(IRST = '1') then
|
if(IRST = '1') then
|
IX1_OPA0_V_q <= '0';
|
IX1_OPA0_V_q <= '0';
|
IX1_OPB0_V_q <= '0';
|
IX1_OPB0_V_q <= '0';
|
IX1_OPA1_V_q <= '0';
|
IX1_OPA1_V_q <= '0';
|
IX1_OPB1_V_q <= '0';
|
IX1_OPB1_V_q <= '0';
|
else
|
else
|
IX1_OPA0_V_q <= IX1_OPA0_V and not(ID_DSA0_q);
|
IX1_OPA0_V_q <= IX1_OPA0_V and not(ID_DSA0_q);
|
IX1_OPB0_V_q <= IX1_OPB0_V and not(ID_DSB0_q);
|
IX1_OPB0_V_q <= IX1_OPB0_V and not(ID_DSB0_q);
|
IX1_OPA1_V_q <= IX1_OPA1_V and not(ID_DSA1_q);
|
IX1_OPA1_V_q <= IX1_OPA1_V and not(ID_DSA1_q);
|
IX1_OPB1_V_q <= IX1_OPB1_V and not(ID_DSB1_q);
|
IX1_OPB1_V_q <= IX1_OPB1_V and not(ID_DSB1_q);
|
end if;
|
end if;
|
IX1_OPA0_q <= IX1_OPA0;
|
IX1_OPA0_q <= IX1_OPA0;
|
IX1_OPB0_q <= IX1_OPB0;
|
IX1_OPB0_q <= IX1_OPB0;
|
IX1_OPA1_q <= IX1_OPA1;
|
IX1_OPA1_q <= IX1_OPA1;
|
IX1_OPB1_q <= IX1_OPB1;
|
IX1_OPB1_q <= IX1_OPB1;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end generate;
|
end generate;
|
|
|
process(CLK_i)
|
process(CLK_i)
|
begin
|
begin
|
if(CLK_i = '1' and CLK_i'event) then
|
if(CLK_i = '1' and CLK_i'event) then
|
IX1_PASEL0_q <= ID_PASEL0_q;
|
IX1_PASEL0_q <= ID_PASEL0_q;
|
IX1_PASEL1_q <= ID_PASEL1_q;
|
IX1_PASEL1_q <= ID_PASEL1_q;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
U_RMUX1 : RV01_RESMUX_IX1
|
U_RMUX1 : RV01_RESMUX_IX1
|
generic map(
|
generic map(
|
PXE => PARALLEL_EXECUTION_ENABLED,
|
PXE => PARALLEL_EXECUTION_ENABLED,
|
DXE => DELAYED_EXECUTION_ENABLED,
|
DXE => DELAYED_EXECUTION_ENABLED,
|
NW => NW
|
NW => NW
|
)
|
)
|
port map(
|
port map(
|
OPA0_V_i => ID_OPA0_V_q,
|
OPA0_V_i => ID_OPA0_V_q,
|
OPA1_V_i => ID_OPA1_V_q,
|
OPA1_V_i => ID_OPA1_V_q,
|
OPA0_i => ID_OPA0_q,
|
OPA0_i => ID_OPA0_q,
|
OPA1_i => ID_OPA1_q,
|
OPA1_i => ID_OPA1_q,
|
OPB0_V_i => ID_OPB0_V_q,
|
OPB0_V_i => ID_OPB0_V_q,
|
OPB1_V_i => ID_OPB1_V_q,
|
OPB1_V_i => ID_OPB1_V_q,
|
OPB0_i => ID_OPB0_q,
|
OPB0_i => ID_OPB0_q,
|
OPB1_i => ID_OPB1_q,
|
OPB1_i => ID_OPB1_q,
|
SHF_RES0_i => IX1_SHF_RES0,
|
SHF_RES0_i => IX1_SHF_RES0,
|
SHF_RES1_i => IX1_SHF_RES1,
|
SHF_RES1_i => IX1_SHF_RES1,
|
PA0_ALU_RES_i => IX1_PA0_ALU_RES,
|
PA0_ALU_RES_i => IX1_PA0_ALU_RES,
|
PA1_ALU_RES_i => IX1_PA1_ALU_RES,
|
PA1_ALU_RES_i => IX1_PA1_ALU_RES,
|
DIV_V_i => IX1_DIV_V,
|
DIV_V_i => IX1_DIV_V,
|
DIV_RES_i => IX1_DIV_RES,
|
DIV_RES_i => IX1_DIV_RES,
|
PASEL0_i => ID_PASEL0_q,
|
PASEL0_i => ID_PASEL0_q,
|
PASEL1_i => ID_PASEL1_q,
|
PASEL1_i => ID_PASEL1_q,
|
FWDE_i => ID_FWDE_q,
|
FWDE_i => ID_FWDE_q,
|
DSA0_i => ID_DSA0_q,
|
DSA0_i => ID_DSA0_q,
|
DSB0_i => ID_DSB0_q,
|
DSB0_i => ID_DSB0_q,
|
DSA1_i => ID_DSA1_q,
|
DSA1_i => ID_DSA1_q,
|
DSB1_i => ID_DSB1_q,
|
DSB1_i => ID_DSB1_q,
|
INSTR_i => ID_INSTR_q,
|
INSTR_i => ID_INSTR_q,
|
IX3_DRD0_i => IX3_DRD0,
|
IX3_DRD0_i => IX3_DRD0,
|
IX3_DRD1_i => IX3_DRD1,
|
IX3_DRD1_i => IX3_DRD1,
|
IX3_V_i => IX2_V_q,
|
IX3_V_i => IX2_V_q,
|
IX3_INSTR_i => IX2_INSTR_q,
|
IX3_INSTR_i => IX2_INSTR_q,
|
|
|
FWDX_o => IX1_FWDX,
|
FWDX_o => IX1_FWDX,
|
PA0_RES_o => IX1_PA0_RES,
|
PA0_RES_o => IX1_PA0_RES,
|
PA1_RES_o => IX1_PA1_RES,
|
PA1_RES_o => IX1_PA1_RES,
|
OPA0_V_o => IX1_OPA0_V,
|
OPA0_V_o => IX1_OPA0_V,
|
OPA1_V_o => IX1_OPA1_V,
|
OPA1_V_o => IX1_OPA1_V,
|
OPA0_o => IX1_OPA0,
|
OPA0_o => IX1_OPA0,
|
OPA1_o => IX1_OPA1,
|
OPA1_o => IX1_OPA1,
|
OPB0_V_o => IX1_OPB0_V,
|
OPB0_V_o => IX1_OPB0_V,
|
OPB1_V_o => IX1_OPB1_V,
|
OPB1_V_o => IX1_OPB1_V,
|
OPB0_o => IX1_OPB0,
|
OPB0_o => IX1_OPB0,
|
OPB1_o => IX1_OPB1,
|
OPB1_o => IX1_OPB1,
|
DRD0_V_o => IX1_DRD0_V,
|
DRD0_V_o => IX1_DRD0_V,
|
DRD1_V_o => IX1_DRD1_V,
|
DRD1_V_o => IX1_DRD1_V,
|
DRD0_o => IX1_DRD0,
|
DRD0_o => IX1_DRD0,
|
DRD1_o => IX1_DRD1
|
DRD1_o => IX1_DRD1
|
);
|
);
|
|
|
-- Pipeline-B
|
-- Pipeline-B
|
|
|
IX1_PC0P4 <= ID_PC_q(0) + 4;
|
IX1_PC0P4 <= ID_PC_q(0) + 4;
|
IX1_PC1P4 <= ID_PC_q(1) + 4;
|
IX1_PC1P4 <= ID_PC_q(1) + 4;
|
|
|
U_PIPEB : RV01_PIPE_B
|
U_PIPEB : RV01_PIPE_B
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
OP_i => ID_INSTR_q(0).ALU_OP,
|
OP_i => ID_INSTR_q(0).ALU_OP,
|
SU_i => ID_INSTR_q(0).SU,
|
SU_i => ID_INSTR_q(0).SU,
|
PC0_i => ID_PC_q(0),
|
PC0_i => ID_PC_q(0),
|
PC1_i => IX1_PC0P4_q,
|
PC1_i => IX1_PC0P4_q,
|
OPA_i => ID_OPA0_q,
|
OPA_i => ID_OPA0_q,
|
OPB_i => ID_OPB0_q,
|
OPB_i => ID_OPB0_q,
|
|
|
RES_o => IX2_PB0_RES
|
RES_o => IX2_PB0_RES
|
);
|
);
|
|
|
GBJX0 : if BRANCH_PREDICTION_ENABLED = '0' generate
|
GBJX0 : if BRANCH_PREDICTION_ENABLED = '0' generate
|
|
|
-- Branch/Jump processing logic (pipe #0)
|
-- Branch/Jump processing logic (pipe #0)
|
|
|
U_BJXLOG0 : RV01_BJXLOG
|
U_BJXLOG0 : RV01_BJXLOG
|
generic map(
|
generic map(
|
JRPE => JALR_PREDICTION_ENABLED
|
JRPE => JALR_PREDICTION_ENABLED
|
)
|
)
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
RST_i => IRST,
|
RST_i => IRST,
|
BJ_OP_i => ID_INSTR_q(0).BJ_OP,
|
BJ_OP_i => ID_INSTR_q(0).BJ_OP,
|
SU_i => ID_INSTR_q(0).SU,
|
SU_i => ID_INSTR_q(0).SU,
|
PC_i => ID_PC_q(0),
|
PC_i => ID_PC_q(0),
|
OPA_i => ID_OPA0_q,
|
OPA_i => ID_OPA0_q,
|
OPB_i => ID_OPB0_q,
|
OPB_i => ID_OPB0_q,
|
IMM_i => ID_INSTR_q(0).IMM,
|
IMM_i => ID_INSTR_q(0).IMM,
|
IV_i => ID_V_q(0),
|
IV_i => ID_V_q(0),
|
FSTLL_i => ID_PSTALL,
|
FSTLL_i => ID_PSTALL,
|
MPJRX_i => IX1_MPJRX(0),
|
MPJRX_i => IX1_MPJRX(0),
|
|
|
BJX_o => IX1_BJX0,
|
BJX_o => IX1_BJX0,
|
BJTA_o => IX1_BJTA0
|
BJTA_o => IX1_BJTA0
|
);
|
);
|
|
|
GPX_X1_6_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
GPX_X1_6_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
|
|
-- Branch/Jump processing logic (pipe #1)
|
-- Branch/Jump processing logic (pipe #1)
|
|
|
U_BJXLOG1 : RV01_BJXLOG
|
U_BJXLOG1 : RV01_BJXLOG
|
generic map(
|
generic map(
|
JRPE => JALR_PREDICTION_ENABLED
|
JRPE => JALR_PREDICTION_ENABLED
|
)
|
)
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
RST_i => IRST,
|
RST_i => IRST,
|
BJ_OP_i => ID_INSTR_q(1).BJ_OP,
|
BJ_OP_i => ID_INSTR_q(1).BJ_OP,
|
SU_i => ID_INSTR_q(1).SU,
|
SU_i => ID_INSTR_q(1).SU,
|
PC_i => ID_PC_q(1),
|
PC_i => ID_PC_q(1),
|
OPA_i => ID_OPA1_q,
|
OPA_i => ID_OPA1_q,
|
OPB_i => ID_OPB1_q,
|
OPB_i => ID_OPB1_q,
|
IMM_i => ID_INSTR_q(1).IMM,
|
IMM_i => ID_INSTR_q(1).IMM,
|
IV_i => ID_V_q(1),
|
IV_i => ID_V_q(1),
|
FSTLL_i => ID_PSTALL,
|
FSTLL_i => ID_PSTALL,
|
MPJRX_i => IX1_MPJRX(1),
|
MPJRX_i => IX1_MPJRX(1),
|
|
|
BJX_o => IX1_BJX1,
|
BJX_o => IX1_BJX1,
|
BJTA_o => IX1_BJTA1
|
BJTA_o => IX1_BJTA1
|
);
|
);
|
|
|
IX1_B2BAC <= '0';
|
IX1_B2BAC <= '0';
|
|
|
end generate; -- GPX_X1_6_1
|
end generate; -- GPX_X1_6_1
|
|
|
GPX_X1_6_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
|
GPX_X1_6_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
|
|
|
IX1_BJX1 <= '0';
|
IX1_BJX1 <= '0';
|
IX1_BJTA1 <= (others =>'0');
|
IX1_BJTA1 <= (others =>'0');
|
|
|
end generate; -- GPX_X1_6_0
|
end generate; -- GPX_X1_6_0
|
|
|
end generate;
|
end generate;
|
|
|
GBJX1 : if BRANCH_PREDICTION_ENABLED = '1' generate
|
GBJX1 : if BRANCH_PREDICTION_ENABLED = '1' generate
|
|
|
-- Branch/Jump processing logic (pipe #0)
|
-- Branch/Jump processing logic (pipe #0)
|
|
|
U_BJXLOG0 : RV01_BJXLOG_BV
|
U_BJXLOG0 : RV01_BJXLOG_BV
|
generic map(
|
generic map(
|
JRPE => JALR_PREDICTION_ENABLED
|
JRPE => JALR_PREDICTION_ENABLED
|
)
|
)
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
RST_i => IRST,
|
RST_i => IRST,
|
BJ_OP_i => ID_INSTR_q(0).BJ_OP,
|
BJ_OP_i => ID_INSTR_q(0).BJ_OP,
|
SU_i => ID_INSTR_q(0).SU,
|
SU_i => ID_INSTR_q(0).SU,
|
PC_i => ID_PC_q(0),
|
PC_i => ID_PC_q(0),
|
OPA_i => ID_OPA0_q,
|
OPA_i => ID_OPA0_q,
|
OPB_i => ID_OPB0_q,
|
OPB_i => ID_OPB0_q,
|
IMM_i => ID_INSTR_q(0).IMM,
|
IMM_i => ID_INSTR_q(0).IMM,
|
IV_i => ID_V_q(0),
|
IV_i => ID_V_q(0),
|
FSTLL_i => ID_PSTALL,
|
FSTLL_i => ID_PSTALL,
|
BPVD_i => ID_BPVD0_q,
|
BPVD_i => ID_BPVD0_q,
|
MPJRX_i => IX1_MPJRX(0),
|
MPJRX_i => IX1_MPJRX(0),
|
|
|
BJX_o => IX1_BJX0,
|
BJX_o => IX1_BJX0,
|
BJTA_o => IX1_BJTA0,
|
BJTA_o => IX1_BJTA0,
|
BHT_WE_o => IX1_BHT_WE(0),
|
BHT_WE_o => IX1_BHT_WE(0),
|
BHT_TA_o => IX1_BHT_TA(0),
|
BHT_TA_o => IX1_BHT_TA(0),
|
BHT_PC_o => open,
|
BHT_PC_o => open,
|
BHT_CNT_o => IX1_BHT_CNT0
|
BHT_CNT_o => IX1_BHT_CNT0
|
);
|
);
|
|
|
GPX_X1_6_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
GPX_X1_6_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
|
|
-- Branch/Jump processing logic (pipe #1)
|
-- Branch/Jump processing logic (pipe #1)
|
|
|
U_BJXLOG1 : RV01_BJXLOG_BV
|
U_BJXLOG1 : RV01_BJXLOG_BV
|
generic map(
|
generic map(
|
JRPE => JALR_PREDICTION_ENABLED
|
JRPE => JALR_PREDICTION_ENABLED
|
)
|
)
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
RST_i => IRST,
|
RST_i => IRST,
|
BJ_OP_i => ID_INSTR_q(1).BJ_OP,
|
BJ_OP_i => ID_INSTR_q(1).BJ_OP,
|
SU_i => ID_INSTR_q(1).SU,
|
SU_i => ID_INSTR_q(1).SU,
|
PC_i => ID_PC_q(1),
|
PC_i => ID_PC_q(1),
|
OPA_i => ID_OPA1_q,
|
OPA_i => ID_OPA1_q,
|
OPB_i => ID_OPB1_q,
|
OPB_i => ID_OPB1_q,
|
IMM_i => ID_INSTR_q(1).IMM,
|
IMM_i => ID_INSTR_q(1).IMM,
|
IV_i => ID_V_q(1),
|
IV_i => ID_V_q(1),
|
FSTLL_i => ID_PSTALL,
|
FSTLL_i => ID_PSTALL,
|
BPVD_i => ID_BPVD1_q,
|
BPVD_i => ID_BPVD1_q,
|
MPJRX_i => IX1_MPJRX(1),
|
MPJRX_i => IX1_MPJRX(1),
|
|
|
BJX_o => IX1_BJX1,
|
BJX_o => IX1_BJX1,
|
BJTA_o => IX1_BJTA1,
|
BJTA_o => IX1_BJTA1,
|
BHT_WE_o => IX1_BHT_PWE,
|
BHT_WE_o => IX1_BHT_PWE,
|
BHT_TA_o => IX1_BHT_TA(1),
|
BHT_TA_o => IX1_BHT_TA(1),
|
BHT_PC_o => open,
|
BHT_PC_o => open,
|
BHT_CNT_o => IX1_BHT_CNT1
|
BHT_CNT_o => IX1_BHT_CNT1
|
);
|
);
|
|
|
-- IX1 slot #1 BHT write-enable flag must be
|
-- IX1 slot #1 BHT write-enable flag must be
|
-- cleared if there's a jump or taken branch in slot #0,
|
-- cleared if there's a jump or taken branch in slot #0,
|
-- or a branch-2-branch address conflict causing slot #1 re-fetch.
|
-- or a branch-2-branch address conflict causing slot #1 re-fetch.
|
IX1_BHT_WE(1) <= IX1_BHT_PWE and not(IX1_BJX0) and not(IX1_B2BAC);
|
IX1_BHT_WE(1) <= IX1_BHT_PWE and not(IX1_BJX0) and not(IX1_B2BAC);
|
|
|
-- branch-2-branch address conflict flag (an even-even, or
|
-- branch-2-branch address conflict flag (an even-even, or
|
-- odd-odd, branch pair can't be handled by BHT update logic)
|
-- odd-odd, branch pair can't be handled by BHT update logic)
|
IX1_B2BAC <= (IX1_BHT_WE(0) and IX1_BHT_PWE) when
|
IX1_B2BAC <= (IX1_BHT_WE(0) and IX1_BHT_PWE) when
|
(ID_PC_q(0)(2) = ID_PC_q(1)(2)) else '0';
|
(ID_PC_q(0)(2) = ID_PC_q(1)(2)) else '0';
|
|
|
end generate; -- GPX_X1_6_1
|
end generate; -- GPX_X1_6_1
|
|
|
GPX_X1_6_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
|
GPX_X1_6_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
|
|
|
IX1_BJX1 <= '0';
|
IX1_BJX1 <= '0';
|
IX1_BJTA1 <= (others => '0');
|
IX1_BJTA1 <= (others => '0');
|
IX1_BHT_WE(1) <= '0';
|
IX1_BHT_WE(1) <= '0';
|
IX1_BHT_TA(1) <= (others => '0');
|
IX1_BHT_TA(1) <= (others => '0');
|
IX1_BHT_CNT1 <= (others => '0');
|
IX1_BHT_CNT1 <= (others => '0');
|
IX1_B2BAC <= '0';
|
IX1_B2BAC <= '0';
|
|
|
end generate; -- GPX_X1_6_0
|
end generate; -- GPX_X1_6_0
|
|
|
end generate;
|
end generate;
|
|
|
-- Branch/Jump eXecute flag
|
-- Branch/Jump eXecute flag
|
IX1_BJX <= IX1_BJX0 or IX1_BJX1;
|
IX1_BJX <= IX1_BJX0 or IX1_BJX1;
|
|
|
-- Branch/Jump target address mux (slot #0 takes
|
-- Branch/Jump target address mux (slot #0 takes
|
-- priority because it holds oldest instruction).
|
-- priority because it holds oldest instruction).
|
|
|
IX1_BJTA <= IX1_BJTA0 when (
|
IX1_BJTA <= IX1_BJTA0 when (
|
IX1_BJX0 = '1' or PARALLEL_EXECUTION_ENABLED = '0'
|
IX1_BJX0 = '1' or PARALLEL_EXECUTION_ENABLED = '0'
|
) else IX1_BJTA1;
|
) else IX1_BJTA1;
|
|
|
-- Instruction valid flags
|
-- Instruction valid flags
|
|
|
-- IX1 slot #0 valid flag is just a copy of ID one.
|
-- IX1 slot #0 valid flag is just a copy of ID one.
|
IX1_V(0) <= ID_V_q(0) and not(IX2_BJX);
|
IX1_V(0) <= ID_V_q(0) and not(IX2_BJX);
|
|
|
-- IX1 slot #1 valid flag must be cleared if there's
|
-- IX1 slot #1 valid flag must be cleared if there's
|
-- a jump or taken branch in slot #0.
|
-- a jump or taken branch in slot #0.
|
IX1_V(1) <= ID_V_q(1) and not(IX2_BJX);
|
IX1_V(1) <= ID_V_q(1) and not(IX2_BJX);
|
|
|
-- Load/Store logic
|
-- Load/Store logic
|
|
|
U_LSU0 : RV01_LSU
|
U_LSU0 : RV01_LSU
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
RST_i => IRST,
|
RST_i => IRST,
|
IV_i => ID_V_q(0),
|
IV_i => ID_V_q(0),
|
LS_OP_i => ID_INSTR_q(0).LS_OP,
|
LS_OP_i => ID_INSTR_q(0).LS_OP,
|
SU_i => ID_INSTR_q(0).SU,
|
SU_i => ID_INSTR_q(0).SU,
|
OPA_i => ID_OPA0_q,
|
OPA_i => ID_OPA0_q,
|
OPB_i => ID_OPB0_q,
|
OPB_i => ID_OPB0_q,
|
IMM_i => ID_INSTR_q(0).IMM,
|
IMM_i => ID_INSTR_q(0).IMM,
|
LDAT_i => DDAT0_i,
|
LDAT_i => DDAT0_i,
|
|
|
RE_o => DRE_o(0),
|
RE_o => DRE_o(0),
|
WE_o => IX1_PDWE(0),
|
WE_o => IX1_PDWE(0),
|
MALGN_o => IX1_MALGN(0),
|
MALGN_o => IX1_MALGN(0),
|
ADR_o => IX1_DADR0,
|
ADR_o => IX1_DADR0,
|
SBE_o => IX1_DBE0,
|
SBE_o => IX1_DBE0,
|
SDAT_o => IX1_DDATO0,
|
SDAT_o => IX1_DDATO0,
|
LDATV_o => IX3_LDAT0_V,
|
LDATV_o => IX3_LDAT0_V,
|
LDAT_o => IX3_LDAT0
|
LDAT_o => IX3_LDAT0
|
);
|
);
|
|
|
GPX_X1_7_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
GPX_X1_7_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
|
|
U_LSU1 : RV01_LSU
|
U_LSU1 : RV01_LSU
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
RST_i => IRST,
|
RST_i => IRST,
|
IV_i => ID_V_q(1),
|
IV_i => ID_V_q(1),
|
LS_OP_i => ID_INSTR_q(1).LS_OP,
|
LS_OP_i => ID_INSTR_q(1).LS_OP,
|
SU_i => ID_INSTR_q(1).SU,
|
SU_i => ID_INSTR_q(1).SU,
|
OPA_i => ID_OPA1_q,
|
OPA_i => ID_OPA1_q,
|
OPB_i => ID_OPB1_q,
|
OPB_i => ID_OPB1_q,
|
IMM_i => ID_INSTR_q(1).IMM,
|
IMM_i => ID_INSTR_q(1).IMM,
|
LDAT_i => DDAT1_i,
|
LDAT_i => DDAT1_i,
|
|
|
RE_o => DRE_o(1),
|
RE_o => DRE_o(1),
|
WE_o => IX1_PDWE(1),
|
WE_o => IX1_PDWE(1),
|
MALGN_o => IX1_MALGN(1),
|
MALGN_o => IX1_MALGN(1),
|
ADR_o => IX1_DADR1,
|
ADR_o => IX1_DADR1,
|
SBE_o => IX1_DBE1,
|
SBE_o => IX1_DBE1,
|
SDAT_o => IX1_DDATO1,
|
SDAT_o => IX1_DDATO1,
|
LDATV_o => IX3_LDAT1_V,
|
LDATV_o => IX3_LDAT1_V,
|
LDAT_o => IX3_LDAT1
|
LDAT_o => IX3_LDAT1
|
);
|
);
|
|
|
end generate; -- GPX_X1_7_1
|
end generate; -- GPX_X1_7_1
|
|
|
GPX_X1_7_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
|
GPX_X1_7_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
|
|
|
DRE_o(1) <= '0';
|
DRE_o(1) <= '0';
|
IX1_PDWE(1) <= '0';
|
IX1_PDWE(1) <= '0';
|
IX1_MALGN(1) <= '0';
|
IX1_MALGN(1) <= '0';
|
IX1_DADR1 <= (others => '0');
|
IX1_DADR1 <= (others => '0');
|
IX1_DBE1 <= (others => '0');
|
IX1_DBE1 <= (others => '0');
|
IX1_DDATO1 <= (others => '0');
|
IX1_DDATO1 <= (others => '0');
|
IX3_LDAT1_V <= '0';
|
IX3_LDAT1_V <= '0';
|
IX3_LDAT1 <= (others => '0');
|
IX3_LDAT1 <= (others => '0');
|
|
|
end generate; -- GPX_X1_7_0
|
end generate; -- GPX_X1_7_0
|
|
|
-- Slot #1 DWE must be cleared if there's
|
-- Slot #1 DWE must be cleared if there's
|
-- a jump or taken branch in slot #0.
|
-- a jump or taken branch in slot #0.
|
|
|
IX1_DWE(0) <= IX1_PDWE(0) and not(IX2_BJX);
|
IX1_DWE(0) <= IX1_PDWE(0) and not(IX2_BJX);
|
IX1_DWE(1) <= IX1_PDWE(1) and not(IX2_BJX);
|
IX1_DWE(1) <= IX1_PDWE(1) and not(IX2_BJX);
|
|
|
-- "Kill Top Store" flag (remove an invalidated
|
-- "Kill Top Store" flag (remove an invalidated
|
-- store from store buffer).
|
-- store from store buffer).
|
|
|
IX1_KTS <= IX1_PDWE(1) and IX1_BJX0 and not(IX2_BJX);
|
IX1_KTS <= IX1_PDWE(1) and IX1_BJX0 and not(IX2_BJX);
|
|
|
-- Data address virtual to address translation
|
-- Data address virtual to address translation
|
|
|
IX1_PDADR0 <= IX1_DADR0 - IMEM_SIZE*4;
|
IX1_PDADR0 <= IX1_DADR0 - IMEM_SIZE*4;
|
IX1_PDADR1 <= IX1_DADR1 - IMEM_SIZE*4;
|
IX1_PDADR1 <= IX1_DADR1 - IMEM_SIZE*4;
|
IX1_PDIADR0 <= IX1_DADR0;
|
IX1_PDIADR0 <= IX1_DADR0;
|
IX1_PDIADR1 <= IX1_DADR1;
|
IX1_PDIADR1 <= IX1_DADR1;
|
IX3_PDADR0 <= IX3_DADR0 - IMEM_SIZE*4;
|
IX3_PDADR0 <= IX3_DADR0 - IMEM_SIZE*4;
|
IX3_PDIADR0 <= IX3_DADR0;
|
IX3_PDIADR0 <= IX3_DADR0;
|
|
|
DADR0_o <= IX3_PDADR0 when(IX3_DWE = '1') else IX1_PDADR0;
|
DADR0_o <= IX3_PDADR0 when(IX3_DWE = '1') else IX1_PDADR0;
|
DADR1_o <= IX1_PDADR1;
|
DADR1_o <= IX1_PDADR1;
|
|
|
DIADR0_o <= IX3_PDIADR0 when(IX3_DWE = '1') else IX1_PDIADR0;
|
DIADR0_o <= IX3_PDIADR0 when(IX3_DWE = '1') else IX1_PDIADR0;
|
DIADR1_o <= IX1_PDIADR1;
|
DIADR1_o <= IX1_PDIADR1;
|
|
|
-- Data/Instructions memory selection logic
|
-- Data/Instructions memory selection logic
|
|
|
U_DIMSLOG : RV01_DIMSLOG
|
U_DIMSLOG : RV01_DIMSLOG
|
generic map(
|
generic map(
|
IMEM_LOWM => IMEM_LOWM,
|
IMEM_LOWM => IMEM_LOWM,
|
IMEM_SIZE => IMEM_SIZE,
|
IMEM_SIZE => IMEM_SIZE,
|
DMEM_SIZE => DMEM_SIZE
|
DMEM_SIZE => DMEM_SIZE
|
)
|
)
|
port map(
|
port map(
|
IX1_OPA0_i => ID_OPA0_q,
|
IX1_OPA0_i => ID_OPA0_q,
|
IX1_OPA1_i => ID_OPA1_q,
|
IX1_OPA1_i => ID_OPA1_q,
|
IX1_IMM0_i => ID_INSTR_q(0).IMM,
|
IX1_IMM0_i => ID_INSTR_q(0).IMM,
|
IX1_IMM1_i => ID_INSTR_q(1).IMM,
|
IX1_IMM1_i => ID_INSTR_q(1).IMM,
|
IX1_DADR0_i => IX1_DADR0,
|
IX1_DADR0_i => IX1_DADR0,
|
IX1_DADR1_i => IX1_DADR1,
|
IX1_DADR1_i => IX1_DADR1,
|
IX3_DADR0_i => IX3_DADR0,
|
IX3_DADR0_i => IX3_DADR0,
|
|
|
IX1_DIMS_o => IX1_DIMS,
|
IX1_DIMS_o => IX1_DIMS,
|
IX3_DIMS_o => IX3_DIMS
|
IX3_DIMS_o => IX3_DIMS
|
);
|
);
|
|
|
-- When a store is committed, its address and the related
|
-- When a store is committed, its address and the related
|
-- memory selection flag value must be forced on DADR0_o
|
-- memory selection flag value must be forced on DADR0_o
|
-- and DIMS_o(0).
|
-- and DIMS_o(0).
|
|
|
DIMS_o(0) <= IX3_DIMS when (IX3_DWE = '1') else IX1_DIMS(0);
|
DIMS_o(0) <= IX3_DIMS when (IX3_DWE = '1') else IX1_DIMS(0);
|
DIMS_o(1) <= IX1_DIMS(1) and PARALLEL_EXECUTION_ENABLED;
|
DIMS_o(1) <= IX1_DIMS(1) and PARALLEL_EXECUTION_ENABLED;
|
|
|
-- Memory interface signals
|
-- Memory interface signals
|
|
|
DBE_o <= IX3_DBE;
|
DBE_o <= IX3_DBE;
|
DWE0_o <= IX3_DWE;
|
DWE0_o <= IX3_DWE;
|
DDAT0_o <= IX3_SDATO;
|
DDAT0_o <= IX3_SDATO;
|
|
|
-- Store buffer
|
-- Store buffer
|
|
|
U_SBUF : RV01_SBUF_2W
|
U_SBUF : RV01_SBUF_2W
|
generic map(
|
generic map(
|
NW => NW,
|
NW => NW,
|
DEPTH => 16,
|
DEPTH => 16,
|
SIMULATION_ONLY => SIMULATION_ONLY
|
SIMULATION_ONLY => SIMULATION_ONLY
|
)
|
)
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
RST_i => IRST,
|
RST_i => IRST,
|
CLRB_i => IX3_CLRP,
|
CLRB_i => IX3_CLRP,
|
KTS_i => IX1_KTS_q,
|
KTS_i => IX1_KTS_q,
|
RE_i => IX3_SBRE,
|
RE_i => IX3_SBRE,
|
WE_i => IX1_DWE,
|
WE_i => IX1_DWE,
|
BE0_i => IX1_DBE0,
|
BE0_i => IX1_DBE0,
|
BE1_i => IX1_DBE1,
|
BE1_i => IX1_DBE1,
|
D0_i => IX1_DDATO0,
|
D0_i => IX1_DDATO0,
|
D1_i => IX1_DDATO1,
|
D1_i => IX1_DDATO1,
|
IX1_V_i => ID_V_q,
|
IX1_V_i => ID_V_q,
|
LS_OP0_i => ID_INSTR_q(0).LS_OP,
|
LS_OP0_i => ID_INSTR_q(0).LS_OP,
|
LS_OP1_i => ID_INSTR_q(1).LS_OP,
|
LS_OP1_i => ID_INSTR_q(1).LS_OP,
|
DADR0_i => IX1_DADR0,
|
DADR0_i => IX1_DADR0,
|
DADR1_i => IX1_DADR1,
|
DADR1_i => IX1_DADR1,
|
SADR0_i => IX2_DADR0_q,
|
SADR0_i => IX2_DADR0_q,
|
SADR1_i => IX2_DADR1_q,
|
SADR1_i => IX2_DADR1_q,
|
|
|
BF_o => IX1_SBF,
|
BF_o => IX1_SBF,
|
NOPR_o => IX1_NOPR,
|
NOPR_o => IX1_NOPR,
|
S2LAC_o => IX1_S2LAC,
|
S2LAC_o => IX1_S2LAC,
|
WE_o => IX3_DWE,
|
WE_o => IX3_DWE,
|
LS_OP_o => IX3_LS_OP,
|
LS_OP_o => IX3_LS_OP,
|
BE_o => IX3_DBE,
|
BE_o => IX3_DBE,
|
Q_o => IX3_SDATO,
|
Q_o => IX3_SDATO,
|
SADR_o => IX3_DADR0
|
SADR_o => IX3_DADR0
|
);
|
);
|
|
|
-- Divider support logic
|
-- Divider support logic
|
|
|
U_DIVLOG: RV01_DIVLOG
|
U_DIVLOG: RV01_DIVLOG
|
port map(
|
port map(
|
V_i => IX1_V(0), --ID_V_q(0),
|
V_i => IX1_V(0), --ID_V_q(0),
|
INSTR_i => ID_INSTR_q(0),
|
INSTR_i => ID_INSTR_q(0),
|
DIV_V_i => IX1_DIV_V,
|
DIV_V_i => IX1_DIV_V,
|
|
|
DIV_STRT_o => IX1_DIV_STRT,
|
DIV_STRT_o => IX1_DIV_STRT,
|
DIV_QS_o => IX1_DIV_QS,
|
DIV_QS_o => IX1_DIV_QS,
|
DIV_CLRV_o => IX1_DIV_CLRV
|
DIV_CLRV_o => IX1_DIV_CLRV
|
);
|
);
|
|
|
-- Divider unit
|
-- Divider unit
|
|
|
U_DIV : RV01_DIVIDER_R2
|
U_DIV : RV01_DIVIDER_R2
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
RST_i => IRST,
|
RST_i => IRST,
|
STRT_i => IX1_DIV_STRT,
|
STRT_i => IX1_DIV_STRT,
|
SU_i => ID_INSTR_q(0).SU,
|
SU_i => ID_INSTR_q(0).SU,
|
QS_i => IX1_DIV_QS,
|
QS_i => IX1_DIV_QS,
|
DD_i => ID_OPA0_q,
|
DD_i => ID_OPA0_q,
|
DR_i => ID_OPB0_q,
|
DR_i => ID_OPB0_q,
|
CLRD_i => IX3_CLRD,
|
CLRD_i => IX3_CLRD,
|
CLRV_i => IX1_DIV_CLRV,
|
CLRV_i => IX1_DIV_CLRV,
|
|
|
Q_o => IX1_DIV_RES,
|
Q_o => IX1_DIV_RES,
|
QV_o => IX1_DIV_V,
|
QV_o => IX1_DIV_V,
|
BSY_o => ID_DIV_BSY
|
BSY_o => ID_DIV_BSY
|
);
|
);
|
|
|
-- Exception processing
|
-- Exception processing
|
|
|
U_EXCPLX1 : RV01_EXCPLOG_IX1
|
U_EXCPLX1 : RV01_EXCPLOG_IX1
|
generic map(
|
generic map(
|
NW => NW
|
NW => NW
|
)
|
)
|
port map(
|
port map(
|
INSTR_i => ID_INSTR_q,
|
INSTR_i => ID_INSTR_q,
|
MALGN_i => IX1_MALGN,
|
MALGN_i => IX1_MALGN,
|
S2LAC_i => IX1_S2LAC,
|
S2LAC_i => IX1_S2LAC,
|
B2BAC_i => IX1_B2BAC,
|
B2BAC_i => IX1_B2BAC,
|
DIV_V_i => IX1_DIV_V,
|
DIV_V_i => IX1_DIV_V,
|
IDADR_CFLT_i => IDADR_CFLT_i,
|
IDADR_CFLT_i => IDADR_CFLT_i,
|
|
|
PSLP_o => IX1_PSLP,
|
PSLP_o => IX1_PSLP,
|
INSTR_o => IX1_INSTR
|
INSTR_o => IX1_INSTR
|
);
|
);
|
|
|
-- Pipeline Registers
|
-- Pipeline Registers
|
|
|
process(CLK_i)
|
process(CLK_i)
|
begin
|
begin
|
if(CLK_i = '1' and CLK_i'event) then
|
if(CLK_i = '1' and CLK_i'event) then
|
if(IRST = '1' or IX3_CLRP = '1') then
|
if(IRST = '1' or IX3_CLRP = '1') then
|
IX1_V_q <= "00";
|
IX1_V_q <= "00";
|
IX1_BJX0_q <= '0';
|
IX1_BJX0_q <= '0';
|
IX1_BJX1_q <= '0';
|
IX1_BJX1_q <= '0';
|
IX1_KTS_q <= '0';
|
IX1_KTS_q <= '0';
|
else
|
else
|
IX1_V_q(0) <= IX1_V(0);
|
IX1_V_q(0) <= IX1_V(0);
|
IX1_V_q(1) <= IX1_V(1) and not(IX1_PSLP);
|
IX1_V_q(1) <= IX1_V(1) and not(IX1_PSLP);
|
IX1_BJX0_q <= IX1_BJX0;
|
IX1_BJX0_q <= IX1_BJX0;
|
IX1_BJX1_q <= IX1_BJX1;
|
IX1_BJX1_q <= IX1_BJX1;
|
IX1_KTS_q <= IX1_KTS;
|
IX1_KTS_q <= IX1_KTS;
|
end if;
|
end if;
|
IX1_INSTR_q(0) <= IX1_INSTR(0);
|
IX1_INSTR_q(0) <= IX1_INSTR(0);
|
IX1_FWDE_q(0) <= ID_FWDE_q(0);
|
IX1_FWDE_q(0) <= ID_FWDE_q(0);
|
IX1_FWDX_q(0) <= IX1_FWDX(0);
|
IX1_FWDX_q(0) <= IX1_FWDX(0);
|
IX1_PC0P4_q <= IX1_PC0P4;
|
IX1_PC0P4_q <= IX1_PC0P4;
|
IX1_PC0_q <= ID_PC_q(0);
|
IX1_PC0_q <= ID_PC_q(0);
|
IX1_DADR0_q <= IX1_DADR0;
|
IX1_DADR0_q <= IX1_DADR0;
|
IX1_DWE_q <= IX1_DWE and not('0' & IX1_KTS);
|
IX1_DWE_q <= IX1_DWE and not('0' & IX1_KTS);
|
IX1_DRD0_q <= IX1_DRD0;
|
IX1_DRD0_q <= IX1_DRD0;
|
IX1_DRD0_V_q <= IX1_DRD0_V;
|
IX1_DRD0_V_q <= IX1_DRD0_V;
|
IX1_INSTR_q(1) <= IX1_INSTR(1);
|
IX1_INSTR_q(1) <= IX1_INSTR(1);
|
IX1_FWDE_q(1) <= ID_FWDE_q(1);
|
IX1_FWDE_q(1) <= ID_FWDE_q(1);
|
IX1_FWDX_q(1) <= IX1_FWDX(1);
|
IX1_FWDX_q(1) <= IX1_FWDX(1);
|
IX1_PC1P4_q <= IX1_PC1P4;
|
IX1_PC1P4_q <= IX1_PC1P4;
|
IX1_PC1_q <= ID_PC_q(1);
|
IX1_PC1_q <= ID_PC_q(1);
|
IX1_DADR1_q <= IX1_DADR1;
|
IX1_DADR1_q <= IX1_DADR1;
|
IX1_DRD1_q <= IX1_DRD1;
|
IX1_DRD1_q <= IX1_DRD1;
|
IX1_DRD1_V_q <= IX1_DRD1_V;
|
IX1_DRD1_V_q <= IX1_DRD1_V;
|
IX1_BJTA0_q <= IX1_BJTA0;
|
IX1_BJTA0_q <= IX1_BJTA0;
|
IX1_BJTA1_q <= IX1_BJTA1;
|
IX1_BJTA1_q <= IX1_BJTA1;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
----------------------------------------------------
|
----------------------------------------------------
|
-- Store Checker & Log File Generator
|
-- Store Checker & Log File Generator
|
----------------------------------------------------
|
----------------------------------------------------
|
|
|
-- synthesis translate_off
|
-- synthesis translate_off
|
|
|
G_ST : if(SIMULATION_ONLY = '1') generate
|
G_ST : if(SIMULATION_ONLY = '1') generate
|
|
|
U_STCHK : RV01_ST_CHECKER
|
U_STCHK : RV01_ST_CHECKER
|
generic map(
|
generic map(
|
ST_FILENAME => ST_FILENAME
|
ST_FILENAME => ST_FILENAME
|
)
|
)
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
ENB_i => CHK_ENB_i,
|
ENB_i => CHK_ENB_i,
|
LS_OP_i => IX3_LS_OP,
|
LS_OP_i => IX3_LS_OP,
|
DWE_i => IX3_DWE,
|
DWE_i => IX3_DWE,
|
BE_i => IX3_DBE,
|
BE_i => IX3_DBE,
|
DADR_i => IX3_DADR0,
|
DADR_i => IX3_DADR0,
|
DDATO_i => IX3_SDATO
|
DDATO_i => IX3_SDATO
|
);
|
);
|
|
|
end generate;
|
end generate;
|
|
|
-- synthesis translate_on
|
-- synthesis translate_on
|
|
|
----------------------------------------------------
|
----------------------------------------------------
|
-- IX2 Stage
|
-- IX2 Stage
|
----------------------------------------------------
|
----------------------------------------------------
|
|
|
-- In stage IX2 results from pipe #0 A and B
|
-- In stage IX2 results from pipe #0 A and B
|
-- sub-pipes get merged, making all result available
|
-- sub-pipes get merged, making all result available
|
-- for forwarding.
|
-- for forwarding.
|
|
|
-- FWDE(n) signal flags that instruction in slot #n
|
-- FWDE(n) signal flags that instruction in slot #n
|
-- belong to subset enabled to forward results, while
|
-- belong to subset enabled to forward results, while
|
-- FWDX(n) signal flags that instruction in slot #n
|
-- FWDX(n) signal flags that instruction in slot #n
|
-- has a result ready for forwarding (i.e. generated
|
-- has a result ready for forwarding (i.e. generated
|
-- from valid operands).
|
-- from valid operands).
|
|
|
-- pipe #0 carries also pipe-B instructions which
|
-- pipe #0 carries also pipe-B instructions which
|
-- have FWDE(0) set to zero, but are allowed to
|
-- have FWDE(0) set to zero, but are allowed to
|
-- forward results from IX3 stage.
|
-- forward results from IX3 stage.
|
|
|
-- Branch/Jump eXecute flag
|
-- Branch/Jump eXecute flag
|
IX2_BJX <=
|
IX2_BJX <=
|
(IX1_BJX0_q and IX1_V_q(0)) or
|
(IX1_BJX0_q and IX1_V_q(0)) or
|
(IX1_BJX1_q and IX1_V_q(1));
|
(IX1_BJX1_q and IX1_V_q(1));
|
|
|
-- Branch/Jump target address mux (slot #0 takes
|
-- Branch/Jump target address mux (slot #0 takes
|
-- priority because it holds oldest instruction).
|
-- priority because it holds oldest instruction).
|
|
|
IX2_BJTA <= IX1_BJTA0_q when (
|
IX2_BJTA <= IX1_BJTA0_q when (
|
(IX1_BJX0_q = '1' and IX1_V_q(0) = '1') or PARALLEL_EXECUTION_ENABLED = '0'
|
(IX1_BJX0_q = '1' and IX1_V_q(0) = '1') or PARALLEL_EXECUTION_ENABLED = '0'
|
) else IX1_BJTA1_q;
|
) else IX1_BJTA1_q;
|
|
|
GDX2_1 : if(DELAYED_EXECUTION_ENABLED = '1') generate
|
GDX2_1 : if(DELAYED_EXECUTION_ENABLED = '1') generate
|
|
|
U_PA0ALU_X2: RV01_PIPE_A_ALU
|
U_PA0ALU_X2: RV01_PIPE_A_ALU
|
port map(
|
port map(
|
SEL_i => IX1_PASEL0_q,
|
SEL_i => IX1_PASEL0_q,
|
SU_i => IX1_INSTR_q(0).SU,
|
SU_i => IX1_INSTR_q(0).SU,
|
OP_i => IX1_INSTR_q(0).ALU_OP,
|
OP_i => IX1_INSTR_q(0).ALU_OP,
|
OPA_i => IX1_OPA0_q,
|
OPA_i => IX1_OPA0_q,
|
OPB_i => IX1_OPB0_q,
|
OPB_i => IX1_OPB0_q,
|
|
|
RES_o => IX2_PA0_ALU_RES
|
RES_o => IX2_PA0_ALU_RES
|
);
|
);
|
|
|
GPX_X2_0_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
GPX_X2_0_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
|
|
U_PA1ALU_X2: RV01_PIPE_A_ALU
|
U_PA1ALU_X2: RV01_PIPE_A_ALU
|
port map(
|
port map(
|
SEL_i => IX1_PASEL1_q,
|
SEL_i => IX1_PASEL1_q,
|
SU_i => IX1_INSTR_q(1).SU,
|
SU_i => IX1_INSTR_q(1).SU,
|
OP_i => IX1_INSTR_q(1).ALU_OP,
|
OP_i => IX1_INSTR_q(1).ALU_OP,
|
OPA_i => IX1_OPA1_q,
|
OPA_i => IX1_OPA1_q,
|
OPB_i => IX1_OPB1_q,
|
OPB_i => IX1_OPB1_q,
|
|
|
RES_o => IX2_PA1_ALU_RES
|
RES_o => IX2_PA1_ALU_RES
|
);
|
);
|
|
|
end generate; -- GPX_X2_0_1
|
end generate; -- GPX_X2_0_1
|
|
|
process(CLK_i)
|
process(CLK_i)
|
begin
|
begin
|
if(CLK_i = '1' and CLK_i'event) then
|
if(CLK_i = '1' and CLK_i'event) then
|
IX2_OPA0_q <= IX2_OPA0;
|
IX2_OPA0_q <= IX2_OPA0;
|
IX2_OPB0_q <= IX2_OPB0;
|
IX2_OPB0_q <= IX2_OPB0;
|
IX2_OPA1_q <= IX2_OPA1;
|
IX2_OPA1_q <= IX2_OPA1;
|
IX2_OPB1_q <= IX2_OPB1;
|
IX2_OPB1_q <= IX2_OPB1;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end generate; -- GDX2_1
|
end generate; -- GDX2_1
|
|
|
U_RMX2 : RV01_RESMUX_IX2
|
U_RMX2 : RV01_RESMUX_IX2
|
generic map(
|
generic map(
|
PXE => PARALLEL_EXECUTION_ENABLED,
|
PXE => PARALLEL_EXECUTION_ENABLED,
|
DXE => DELAYED_EXECUTION_ENABLED,
|
DXE => DELAYED_EXECUTION_ENABLED,
|
NW => NW
|
NW => NW
|
)
|
)
|
port map(
|
port map(
|
OPA0_V_i => IX1_OPA0_V_q,
|
OPA0_V_i => IX1_OPA0_V_q,
|
OPA1_V_i => IX1_OPA1_V_q,
|
OPA1_V_i => IX1_OPA1_V_q,
|
OPA0_i => IX1_OPA0_q,
|
OPA0_i => IX1_OPA0_q,
|
OPA1_i => IX1_OPA1_q,
|
OPA1_i => IX1_OPA1_q,
|
OPB0_V_i => IX1_OPB0_V_q,
|
OPB0_V_i => IX1_OPB0_V_q,
|
OPB1_V_i => IX1_OPB1_V_q,
|
OPB1_V_i => IX1_OPB1_V_q,
|
OPB0_i => IX1_OPB0_q,
|
OPB0_i => IX1_OPB0_q,
|
OPB1_i => IX1_OPB1_q,
|
OPB1_i => IX1_OPB1_q,
|
DRD0_V_i => IX1_DRD0_V_q,
|
DRD0_V_i => IX1_DRD0_V_q,
|
DRD1_V_i => IX1_DRD1_V_q,
|
DRD1_V_i => IX1_DRD1_V_q,
|
DRD0_i => IX1_DRD0_q,
|
DRD0_i => IX1_DRD0_q,
|
DRD1_i => IX1_DRD1_q,
|
DRD1_i => IX1_DRD1_q,
|
DDAT0_i => DDAT0_i,
|
DDAT0_i => DDAT0_i,
|
DDAT1_i => DDAT1_i,
|
DDAT1_i => DDAT1_i,
|
PA0_ALU_RES_i => IX2_PA0_ALU_RES,
|
PA0_ALU_RES_i => IX2_PA0_ALU_RES,
|
PA1_ALU_RES_i => IX2_PA1_ALU_RES,
|
PA1_ALU_RES_i => IX2_PA1_ALU_RES,
|
PB0_RES_i => IX2_PB0_RES,
|
PB0_RES_i => IX2_PB0_RES,
|
PC1P4_i => IX1_PC1P4_q,
|
PC1P4_i => IX1_PC1P4_q,
|
PASEL0_i => IX1_PASEL0_q,
|
PASEL0_i => IX1_PASEL0_q,
|
PASEL1_i => IX1_PASEL1_q,
|
PASEL1_i => IX1_PASEL1_q,
|
FWDE_i => IX1_FWDE_q,
|
FWDE_i => IX1_FWDE_q,
|
INSTR_i => IX1_INSTR_q,
|
INSTR_i => IX1_INSTR_q,
|
IX3_DRD0_i => IX3_DRD0,
|
IX3_DRD0_i => IX3_DRD0,
|
IX3_DRD1_i => IX3_DRD1,
|
IX3_DRD1_i => IX3_DRD1,
|
IX3_V_i => IX2_V_q,
|
IX3_V_i => IX2_V_q,
|
IX3_INSTR_i => IX2_INSTR_q,
|
IX3_INSTR_i => IX2_INSTR_q,
|
|
|
FWDX_o => IX2_FWDX,
|
FWDX_o => IX2_FWDX,
|
PA0_RES_o => IX2_PA0_RES,
|
PA0_RES_o => IX2_PA0_RES,
|
PA1_RES_o => IX2_PA1_RES,
|
PA1_RES_o => IX2_PA1_RES,
|
OPA0_V_o => IX2_OPA0_V,
|
OPA0_V_o => IX2_OPA0_V,
|
OPA1_V_o => IX2_OPA1_V,
|
OPA1_V_o => IX2_OPA1_V,
|
OPA0_o => IX2_OPA0,
|
OPA0_o => IX2_OPA0,
|
OPA1_o => IX2_OPA1,
|
OPA1_o => IX2_OPA1,
|
OPB0_V_o => IX2_OPB0_V,
|
OPB0_V_o => IX2_OPB0_V,
|
OPB1_V_o => IX2_OPB1_V,
|
OPB1_V_o => IX2_OPB1_V,
|
OPB0_o => IX2_OPB0,
|
OPB0_o => IX2_OPB0,
|
OPB1_o => IX2_OPB1,
|
OPB1_o => IX2_OPB1,
|
DRD0_o => IX2_DRD0,
|
DRD0_o => IX2_DRD0,
|
DRD1_o => IX2_DRD1
|
DRD1_o => IX2_DRD1
|
);
|
);
|
|
|
-- Exception processing: data address errors are
|
-- Exception processing: data address errors are
|
-- detected by memory sub-system and reported
|
-- detected by memory sub-system and reported
|
-- using DADR*_ERR_i.
|
-- using DADR*_ERR_i.
|
|
|
IX2_V_BJX(0) <= IX1_V_q(0);
|
IX2_V_BJX(0) <= IX1_V_q(0);
|
IX2_V_BJX(1) <= IX1_V_q(1) and not(IX1_BJX0_q);
|
IX2_V_BJX(1) <= IX1_V_q(1) and not(IX1_BJX0_q);
|
|
|
U_EXCPLX2 : RV01_EXCPLOG_IX2
|
U_EXCPLX2 : RV01_EXCPLOG_IX2
|
generic map(
|
generic map(
|
NW => NW
|
NW => NW
|
)
|
)
|
port map(
|
port map(
|
V_i => IX2_V_BJX, --IX1_V_q,
|
V_i => IX2_V_BJX, --IX1_V_q,
|
INSTR_i => IX1_INSTR_q,
|
INSTR_i => IX1_INSTR_q,
|
PC0_i => IX1_PC0_q,
|
PC0_i => IX1_PC0_q,
|
PC1_i => IX1_PC1_q,
|
PC1_i => IX1_PC1_q,
|
DADR0_i => IX1_DADR0_q,
|
DADR0_i => IX1_DADR0_q,
|
DADR1_i => IX1_DADR1_q,
|
DADR1_i => IX1_DADR1_q,
|
HALT_i => IX2_HALT,
|
HALT_i => IX2_HALT,
|
RSM_i => WB_RSM,
|
RSM_i => WB_RSM,
|
DRSM_i => WB_DRSM,
|
DRSM_i => WB_DRSM,
|
EXT_INT_i => EXT_INT_i,
|
EXT_INT_i => EXT_INT_i,
|
SFT_INT_i => WB_SFT_INT,
|
SFT_INT_i => WB_SFT_INT,
|
TMR_INT_i => WB_TMR_INT,
|
TMR_INT_i => WB_TMR_INT,
|
ETVA_i => WB_ETVA,
|
ETVA_i => WB_ETVA,
|
MEPC_i => WB_MEPC,
|
MEPC_i => WB_MEPC,
|
DADR0_ERR_i => DADR0_ERR_i,
|
DADR0_ERR_i => DADR0_ERR_i,
|
DADR1_ERR_i => DADR1_ERR_i,
|
DADR1_ERR_i => DADR1_ERR_i,
|
CSR_ILLG_i => IX2_ILLG,
|
CSR_ILLG_i => IX2_ILLG,
|
IE_i => WB_IE,
|
IE_i => WB_IE,
|
STEP_i => IX2_STEP,
|
STEP_i => IX2_STEP,
|
|
|
V_o => IX2_V,
|
V_o => IX2_V,
|
EV_o => IX2_EV,
|
EV_o => IX2_EV,
|
INSTR_o => IX2_INSTR,
|
INSTR_o => IX2_INSTR,
|
EERTA_o => IX2_EERTA
|
EERTA_o => IX2_EERTA
|
);
|
);
|
|
|
GDM0_1 : if (DM_PRESENT = '1') generate
|
GDM0_1 : if (DM_PRESENT = '1') generate
|
|
|
-- Debug logic
|
-- Debug logic
|
|
|
UDBGLOGX2 : RV01_DBGLOG_IX2
|
UDBGLOGX2 : RV01_DBGLOG_IX2
|
generic map(
|
generic map(
|
NW => NW
|
NW => NW
|
)
|
)
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
RST_i => IRST,
|
RST_i => IRST,
|
V_i => IX1_V_q,
|
V_i => IX1_V_q,
|
IMNMC0_i => IX1_INSTR_q(0).IMNMC,
|
IMNMC0_i => IX1_INSTR_q(0).IMNMC,
|
RFTCH0_i => IX1_INSTR_q(0).RFTCH,
|
RFTCH0_i => IX1_INSTR_q(0).RFTCH,
|
STEP_i => WB_DSTEP,
|
STEP_i => WB_DSTEP,
|
HOBRK_i => WB_DHOBRK,
|
HOBRK_i => WB_DHOBRK,
|
HRQ_i => WB_DHLTRQ,
|
HRQ_i => WB_DHLTRQ,
|
|
|
STEP_o => IX2_STEP,
|
STEP_o => IX2_STEP,
|
HALT_o => IX2_HALT,
|
HALT_o => IX2_HALT,
|
HIS_o => IX2_HIS
|
HIS_o => IX2_HIS
|
);
|
);
|
|
|
end generate;
|
end generate;
|
|
|
GDM0_0 : if (DM_PRESENT = '0') generate
|
GDM0_0 : if (DM_PRESENT = '0') generate
|
|
|
-- Halting logic
|
-- Halting logic
|
|
|
UHLTLOGX2: RV01_HLTLOG_IX2
|
UHLTLOGX2: RV01_HLTLOG_IX2
|
generic map(
|
generic map(
|
NW => NW
|
NW => NW
|
)
|
)
|
port map(
|
port map(
|
V_i => IX1_V_q,
|
V_i => IX1_V_q,
|
IMNMC0_i => IX1_INSTR_q(0).IMNMC,
|
IMNMC0_i => IX1_INSTR_q(0).IMNMC,
|
PC0_i => IX1_PC0_q,
|
PC0_i => IX1_PC0_q,
|
PC1_i => IX1_PC1_q,
|
PC1_i => IX1_PC1_q,
|
HOBRK_i => WB_HLTOBRK,
|
HOBRK_i => WB_HLTOBRK,
|
HOADR_i => WB_HLTOADR,
|
HOADR_i => WB_HLTOADR,
|
HADR_i => WB_HLTADR,
|
HADR_i => WB_HLTADR,
|
HRQ_i => WB_HLTURQ,
|
HRQ_i => WB_HLTURQ,
|
|
|
HALT_o => IX2_HALT,
|
HALT_o => IX2_HALT,
|
HIS_o => IX2_HIS
|
HIS_o => IX2_HIS
|
);
|
);
|
|
|
IX2_STEP <= '0';
|
IX2_STEP <= '0';
|
|
|
end generate;
|
end generate;
|
|
|
-- Pipeline Registers
|
-- Pipeline Registers
|
|
|
process(CLK_i)
|
process(CLK_i)
|
begin
|
begin
|
if(CLK_i = '1' and CLK_i'event) then
|
if(CLK_i = '1' and CLK_i'event) then
|
if(IRST = '1') then
|
if(IRST = '1') then
|
IX2_V_q <= "00";
|
IX2_V_q <= "00";
|
IX2_EV_q <= "00";
|
IX2_EV_q <= "00";
|
else
|
else
|
if(IX3_STL(0) = '0') then
|
if(IX3_STL(0) = '0') then
|
IX2_V_q(0) <= IX2_V(0) and not(IX3_CLRP);
|
IX2_V_q(0) <= IX2_V(0) and not(IX3_CLRP);
|
IX2_EV_q(0) <= IX2_EV(0) and not(IX3_CLRP);
|
IX2_EV_q(0) <= IX2_EV(0) and not(IX3_CLRP);
|
end if;
|
end if;
|
if(IX3_STL(1) = '0') then
|
if(IX3_STL(1) = '0') then
|
IX2_V_q(1) <= IX2_V(1) and not(IX3_CLRP);
|
IX2_V_q(1) <= IX2_V(1) and not(IX3_CLRP);
|
IX2_EV_q(1) <= IX2_EV(1) and not(IX3_CLRP);
|
IX2_EV_q(1) <= IX2_EV(1) and not(IX3_CLRP);
|
end if;
|
end if;
|
end if;
|
end if;
|
if(IRST = '1') then
|
if(IRST = '1') then
|
IX2_DWE_q <= "00";
|
IX2_DWE_q <= "00";
|
IX2_HALT_q <= "00";
|
IX2_HALT_q <= "00";
|
elsif(IX3_STL(0) = '0') then
|
elsif(IX3_STL(0) = '0') then
|
IX2_INSTR_q(0) <= IX2_INSTR(0);
|
IX2_INSTR_q(0) <= IX2_INSTR(0);
|
IX2_PC0_q <= IX1_PC0_q;
|
IX2_PC0_q <= IX1_PC0_q;
|
IX2_FWDE_q(0) <= IX1_FWDE_q(0);
|
IX2_FWDE_q(0) <= IX1_FWDE_q(0);
|
IX2_FWDX_q(0) <= IX2_FWDX(0);
|
IX2_FWDX_q(0) <= IX2_FWDX(0);
|
IX2_DRD0_q <= IX2_DRD0;
|
IX2_DRD0_q <= IX2_DRD0;
|
IX2_DADR0_q <= IX1_DADR0_q;
|
IX2_DADR0_q <= IX1_DADR0_q;
|
IX2_CSRU_RES_q <= IX2_CSRU_RES;
|
IX2_CSRU_RES_q <= IX2_CSRU_RES;
|
IX2_DWE_q(0) <= IX1_DWE_q(0);
|
IX2_DWE_q(0) <= IX1_DWE_q(0);
|
IX2_HALT_q(0) <= IX2_HALT(0) and not(IX3_CLRP);
|
IX2_HALT_q(0) <= IX2_HALT(0) and not(IX3_CLRP);
|
IX2_PASEL1_q <= IX1_PASEL1_q;
|
IX2_PASEL1_q <= IX1_PASEL1_q;
|
end if;
|
end if;
|
if(IX3_STL(1) = '0') then
|
if(IX3_STL(1) = '0') then
|
IX2_INSTR_q(1) <= IX2_INSTR(1);
|
IX2_INSTR_q(1) <= IX2_INSTR(1);
|
IX2_PC1_q <= IX1_PC1_q;
|
IX2_PC1_q <= IX1_PC1_q;
|
IX2_FWDE_q(1) <= IX1_FWDE_q(1);
|
IX2_FWDE_q(1) <= IX1_FWDE_q(1);
|
IX2_FWDX_q(1) <= IX2_FWDX(1);
|
IX2_FWDX_q(1) <= IX2_FWDX(1);
|
IX2_DRD1_q <= IX2_DRD1;
|
IX2_DRD1_q <= IX2_DRD1;
|
IX2_DADR1_q <= IX1_DADR1_q;
|
IX2_DADR1_q <= IX1_DADR1_q;
|
IX2_DWE_q(1) <= IX1_DWE_q(1);
|
IX2_DWE_q(1) <= IX1_DWE_q(1);
|
IX2_HALT_q(1) <= IX2_HALT(1) and not(IX3_CLRP);
|
IX2_HALT_q(1) <= IX2_HALT(1) and not(IX3_CLRP);
|
IX2_PASEL0_q <= IX1_PASEL0_q;
|
IX2_PASEL0_q <= IX1_PASEL0_q;
|
end if;
|
end if;
|
if(IX3_STL = "00") then
|
if(IX3_STL = "00") then
|
IX2_EERTA_q <= IX2_EERTA;
|
IX2_EERTA_q <= IX2_EERTA;
|
end if;
|
end if;
|
IX2_HIS_q <= IX2_HIS;
|
IX2_HIS_q <= IX2_HIS;
|
IX2_PC0P4_q <= IX1_PC0P4_q;
|
IX2_PC0P4_q <= IX1_PC0P4_q;
|
IX2_PC1P4_q <= IX1_PC1P4_q;
|
IX2_PC1P4_q <= IX1_PC1P4_q;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
----------------------------------------------------
|
----------------------------------------------------
|
-- IX3 Stage
|
-- IX3 Stage
|
----------------------------------------------------
|
----------------------------------------------------
|
|
|
-- Stage IX3 is used to perform data alignment operations
|
-- Stage IX3 is used to perform data alignment operations
|
-- for LB* and LH* instructions and for exception
|
-- for LB* and LH* instructions and for exception
|
-- processing.
|
-- processing.
|
|
|
GDX3_1 : if(DELAYED_EXECUTION_ENABLED = '1') generate
|
GDX3_1 : if(DELAYED_EXECUTION_ENABLED = '1') generate
|
|
|
U_PA0ALU_X3: RV01_PIPE_A_ALU
|
U_PA0ALU_X3: RV01_PIPE_A_ALU
|
port map(
|
port map(
|
SEL_i => IX2_PASEL0_q,
|
SEL_i => IX2_PASEL0_q,
|
SU_i => IX2_INSTR_q(0).SU,
|
SU_i => IX2_INSTR_q(0).SU,
|
OP_i => IX2_INSTR_q(0).ALU_OP,
|
OP_i => IX2_INSTR_q(0).ALU_OP,
|
OPA_i => IX2_OPA0_q,
|
OPA_i => IX2_OPA0_q,
|
OPB_i => IX2_OPB0_q,
|
OPB_i => IX2_OPB0_q,
|
|
|
RES_o => IX3_PA0_ALU_RES
|
RES_o => IX3_PA0_ALU_RES
|
);
|
);
|
|
|
GPX_X3_0_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
GPX_X3_0_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
|
|
|
U_PA1ALU_X3: RV01_PIPE_A_ALU
|
U_PA1ALU_X3: RV01_PIPE_A_ALU
|
port map(
|
port map(
|
SEL_i => IX2_PASEL1_q,
|
SEL_i => IX2_PASEL1_q,
|
SU_i => IX2_INSTR_q(1).SU,
|
SU_i => IX2_INSTR_q(1).SU,
|
OP_i => IX2_INSTR_q(1).ALU_OP,
|
OP_i => IX2_INSTR_q(1).ALU_OP,
|
OPA_i => IX2_OPA1_q,
|
OPA_i => IX2_OPA1_q,
|
OPB_i => IX2_OPB1_q,
|
OPB_i => IX2_OPB1_q,
|
|
|
RES_o => IX3_PA1_ALU_RES
|
RES_o => IX3_PA1_ALU_RES
|
);
|
);
|
|
|
end generate; -- GPX_X3_0_1
|
end generate; -- GPX_X3_0_1
|
|
|
end generate;
|
end generate;
|
|
|
-- Result mux
|
-- Result mux
|
|
|
U_RMX3: RV01_RESMUX_IX3
|
U_RMX3: RV01_RESMUX_IX3
|
generic map(
|
generic map(
|
PXE => PARALLEL_EXECUTION_ENABLED,
|
PXE => PARALLEL_EXECUTION_ENABLED,
|
DXE => DELAYED_EXECUTION_ENABLED,
|
DXE => DELAYED_EXECUTION_ENABLED,
|
NW => NW
|
NW => NW
|
)
|
)
|
port map(
|
port map(
|
DRD0_i => IX2_DRD0_q,
|
DRD0_i => IX2_DRD0_q,
|
DRD1_i => IX2_DRD1_q,
|
DRD1_i => IX2_DRD1_q,
|
PA0_ALU_RES_i => IX3_PA0_ALU_RES,
|
PA0_ALU_RES_i => IX3_PA0_ALU_RES,
|
PA1_ALU_RES_i => IX3_PA1_ALU_RES,
|
PA1_ALU_RES_i => IX3_PA1_ALU_RES,
|
LDAT0_i => IX3_LDAT0,
|
LDAT0_i => IX3_LDAT0,
|
LDAT1_i => IX3_LDAT1,
|
LDAT1_i => IX3_LDAT1,
|
LDAT_V_i(0) => IX3_LDAT0_V,
|
LDAT_V_i(0) => IX3_LDAT0_V,
|
LDAT_V_i(1) => IX3_LDAT1_V,
|
LDAT_V_i(1) => IX3_LDAT1_V,
|
PASEL0_i => IX2_PASEL0_q,
|
PASEL0_i => IX2_PASEL0_q,
|
PASEL1_i => IX2_PASEL1_q,
|
PASEL1_i => IX2_PASEL1_q,
|
FWDE_i => IX2_FWDE_q,
|
FWDE_i => IX2_FWDE_q,
|
RES_SRC0_i => IX2_INSTR_q(0).RES_SRC,
|
RES_SRC0_i => IX2_INSTR_q(0).RES_SRC,
|
CSRU_RES_i => IX2_CSRU_RES_q,
|
CSRU_RES_i => IX2_CSRU_RES_q,
|
|
|
DRD0_o => IX3_DRD0,
|
DRD0_o => IX3_DRD0,
|
DRD1_o => IX3_DRD1
|
DRD1_o => IX3_DRD1
|
);
|
);
|
|
|
-- Exception logic
|
-- Exception logic
|
|
|
U_EXCPLX3 : RV01_EXCPLOG_IX3
|
U_EXCPLX3 : RV01_EXCPLOG_IX3
|
generic map(
|
generic map(
|
NW => NW
|
NW => NW
|
)
|
)
|
port map(
|
port map(
|
V_i => IX2_V_q,
|
V_i => IX2_V_q,
|
EV_i => IX2_EV_q,
|
EV_i => IX2_EV_q,
|
INSTR_i => IX2_INSTR_q,
|
INSTR_i => IX2_INSTR_q,
|
PC0_i => IX2_PC0_q,
|
PC0_i => IX2_PC0_q,
|
PC1_i => IX2_PC1_q,
|
PC1_i => IX2_PC1_q,
|
DADR0_i => IX2_DADR0_q,
|
DADR0_i => IX2_DADR0_q,
|
DADR1_i => IX2_DADR1_q,
|
DADR1_i => IX2_DADR1_q,
|
HALT_i => IX3_HALT,
|
HALT_i => IX3_HALT,
|
HIS_i => IX2_HIS_q,
|
HIS_i => IX2_HIS_q,
|
|
|
EXCP_o => IX3_EXCP,
|
EXCP_o => IX3_EXCP,
|
ERET_o => IX3_ERET,
|
ERET_o => IX3_ERET,
|
RFTCH_o => IX3_RFTCH,
|
RFTCH_o => IX3_RFTCH,
|
KPRD_o => IX3_KPRD,
|
KPRD_o => IX3_KPRD,
|
CLRP_o => IX3_CLRP_NOHLT,
|
CLRP_o => IX3_CLRP_NOHLT,
|
CLRB_o => IX3_CLRB,
|
CLRB_o => IX3_CLRB,
|
CLRD_o => IX3_CLRD_NOHLT,
|
CLRD_o => IX3_CLRD_NOHLT,
|
EPC_o => IX3_EPC,
|
EPC_o => IX3_EPC,
|
ECAUSE_o => IX3_ECAUSE,
|
ECAUSE_o => IX3_ECAUSE,
|
EDADR_o => IX3_EDADR
|
EDADR_o => IX3_EDADR
|
);
|
);
|
|
|
-- Miscellaneous logic
|
-- Miscellaneous logic
|
|
|
U_MLOGX3 : RV01_MISCLOG_IX3
|
U_MLOGX3 : RV01_MISCLOG_IX3
|
generic map(
|
generic map(
|
PXE => PARALLEL_EXECUTION_ENABLED,
|
PXE => PARALLEL_EXECUTION_ENABLED,
|
NW => NW
|
NW => NW
|
)
|
)
|
port map(
|
port map(
|
IX1_V0_i => ID_V_q(0),
|
IX1_V0_i => ID_V_q(0),
|
IX1_WCSR0_i => ID_INSTR_q(0).WCSR,
|
IX1_WCSR0_i => ID_INSTR_q(0).WCSR,
|
V_i => IX2_V_q ,
|
V_i => IX2_V_q ,
|
DWE_i => IX2_DWE_q,
|
DWE_i => IX2_DWE_q,
|
KPRD_i => IX3_KPRD,
|
KPRD_i => IX3_KPRD,
|
WRD0_i => IX2_INSTR_q(0).WRD,
|
WRD0_i => IX2_INSTR_q(0).WRD,
|
WRD1_i => IX2_INSTR_q(1).WRD,
|
WRD1_i => IX2_INSTR_q(1).WRD,
|
HALT_i => IX2_HALT_q,
|
HALT_i => IX2_HALT_q,
|
CLRP_i => IX3_CLRP_NOHLT,
|
CLRP_i => IX3_CLRP_NOHLT,
|
CLRD_i => IX3_CLRD_NOHLT,
|
CLRD_i => IX3_CLRD_NOHLT,
|
HIS_i => IX2_HIS_q,
|
HIS_i => IX2_HIS_q,
|
PC0_i => IX2_PC0_q,
|
PC0_i => IX2_PC0_q,
|
PC1_i => IX2_PC1_q,
|
PC1_i => IX2_PC1_q,
|
|
|
CP_WE_o => IX1_CP_WE,
|
CP_WE_o => IX1_CP_WE,
|
SBRE_o => IX3_SBRE,
|
SBRE_o => IX3_SBRE,
|
STL_o => IX3_STL,
|
STL_o => IX3_STL,
|
WE_o => IX3_WE,
|
WE_o => IX3_WE,
|
HALT_o => IX3_HALT,
|
HALT_o => IX3_HALT,
|
CLRP_o => IX3_CLRP,
|
CLRP_o => IX3_CLRP,
|
CLRD_o => IX3_CLRD,
|
CLRD_o => IX3_CLRD,
|
HPC_o => IX3_HPC
|
HPC_o => IX3_HPC
|
);
|
);
|
|
|
----------------------------------------------------
|
----------------------------------------------------
|
-- WB Stage
|
-- WB Stage
|
----------------------------------------------------
|
----------------------------------------------------
|
|
|
-- Register File
|
-- Register File
|
|
|
U_REGF : RV01_REGFILE_32X32_2W
|
U_REGF : RV01_REGFILE_32X32_2W
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
RA0_i => IF2_DEC_INSTR_q(0).RS1,
|
RA0_i => IF2_DEC_INSTR_q(0).RS1,
|
RA1_i => IF2_DEC_INSTR_q(0).RS2,
|
RA1_i => IF2_DEC_INSTR_q(0).RS2,
|
RA2_i => IF2_DEC_INSTR_q(1).RS1,
|
RA2_i => IF2_DEC_INSTR_q(1).RS1,
|
RA3_i => IF2_DEC_INSTR_q(1).RS2,
|
RA3_i => IF2_DEC_INSTR_q(1).RS2,
|
WA0_i => IX2_INSTR_q(0).RD,
|
WA0_i => IX2_INSTR_q(0).RD,
|
WA1_i => IX2_INSTR_q(1).RD,
|
WA1_i => IX2_INSTR_q(1).RD,
|
WE0_i => IX3_WE(0),
|
WE0_i => IX3_WE(0),
|
WE1_i => IX3_WE(1),
|
WE1_i => IX3_WE(1),
|
D0_i => to_std_logic_vector(IX3_DRD0),
|
D0_i => to_std_logic_vector(IX3_DRD0),
|
D1_i => to_std_logic_vector(IX3_DRD1),
|
D1_i => to_std_logic_vector(IX3_DRD1),
|
|
|
Q0_o => WB_RDA0,
|
Q0_o => WB_RDA0,
|
Q1_o => WB_RDB0,
|
Q1_o => WB_RDB0,
|
Q2_o => WB_RDA1,
|
Q2_o => WB_RDA1,
|
Q3_o => WB_RDB1
|
Q3_o => WB_RDB1
|
);
|
);
|
|
|
-- CSR's management Unit
|
-- CSR's management Unit
|
|
|
U_CSRU : RV01_CSRU
|
U_CSRU : RV01_CSRU
|
generic map(
|
generic map(
|
PXE => PARALLEL_EXECUTION_ENABLED,
|
PXE => PARALLEL_EXECUTION_ENABLED,
|
FPU_PRESENT => FPU_PRESENT,
|
FPU_PRESENT => FPU_PRESENT,
|
NW => NW
|
NW => NW
|
)
|
)
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
RST_i => IRST,
|
RST_i => IRST,
|
IX1_V0_i => ID_V_q(0),
|
IX1_V0_i => ID_V_q(0),
|
CS_OP_i => ID_INSTR_q(0).CS_OP,
|
CS_OP_i => ID_INSTR_q(0).CS_OP,
|
RS1_i => ID_INSTR_q(0).RS1,
|
RS1_i => ID_INSTR_q(0).RS1,
|
ADR_i => ID_INSTR_q(0).IMM(12-1 downto 0),
|
ADR_i => ID_INSTR_q(0).IMM(12-1 downto 0),
|
WE_i => IX1_CP_WE,
|
WE_i => IX1_CP_WE,
|
CSRD_i => ID_OPA0_q,
|
CSRD_i => ID_OPA0_q,
|
EXCP_i => IX3_EXCP,
|
EXCP_i => IX3_EXCP,
|
EPC_i => IX3_EPC,
|
EPC_i => IX3_EPC,
|
ECAUSE_i => IX3_ECAUSE,
|
ECAUSE_i => IX3_ECAUSE,
|
EBADR_i => IX3_EDADR,
|
EBADR_i => IX3_EDADR,
|
ERET_i => IX3_ERET,
|
ERET_i => IX3_ERET,
|
IX3_V_i => IX2_V_q,
|
IX3_V_i => IX2_V_q,
|
NOPR_i => IX1_NOPR,
|
NOPR_i => IX1_NOPR,
|
HALT_i => IX2_HALT(0),
|
HALT_i => IX2_HALT(0),
|
STOPCYCLE_i => WB_STOPCYCLE,
|
STOPCYCLE_i => WB_STOPCYCLE,
|
STOPTIME_i => WB_STOPTIME,
|
STOPTIME_i => WB_STOPTIME,
|
MFROMHOST_WE_i => MFROMHOST_WE_i,
|
MFROMHOST_WE_i => MFROMHOST_WE_i,
|
MFROMHOST_i => MFROMHOST_i,
|
MFROMHOST_i => MFROMHOST_i,
|
DMODE_i => WB_DMODE,
|
DMODE_i => WB_DMODE,
|
DIE_i => WB_DIE,
|
DIE_i => WB_DIE,
|
CPRE_i => CP_RE_i,
|
CPRE_i => CP_RE_i,
|
CPWE_i => CP_WE_i,
|
CPWE_i => CP_WE_i,
|
CPADR_i => CP_ADR_i,
|
CPADR_i => CP_ADR_i,
|
CPD_i => CP_D_i,
|
CPD_i => CP_D_i,
|
|
|
PXE_o => WB_PXE,
|
PXE_o => WB_PXE,
|
MSTATUS_o => WB_MSTATUS,
|
MSTATUS_o => WB_MSTATUS,
|
MEPC_o => WB_MEPC,
|
MEPC_o => WB_MEPC,
|
MBASE_o => WB_MBASE,
|
MBASE_o => WB_MBASE,
|
MBOUND_o => WB_MBOUND,
|
MBOUND_o => WB_MBOUND,
|
MIBASE_o => WB_MIBASE,
|
MIBASE_o => WB_MIBASE,
|
MIBOUND_o => WB_MIBOUND,
|
MIBOUND_o => WB_MIBOUND,
|
MDBASE_o => WB_MDBASE,
|
MDBASE_o => WB_MDBASE,
|
MDBOUND_o => WB_MDBOUND,
|
MDBOUND_o => WB_MDBOUND,
|
ETVA_o => WB_ETVA,
|
ETVA_o => WB_ETVA,
|
MTOHOST_o => MTOHOST_o,
|
MTOHOST_o => MTOHOST_o,
|
MTOHOST_OE_o => MTOHOST_OE_o,
|
MTOHOST_OE_o => MTOHOST_OE_o,
|
ILLG_o => WB_ILLG,
|
ILLG_o => WB_ILLG,
|
SFT_INT_o => WB_SFT_INT,
|
SFT_INT_o => WB_SFT_INT,
|
TMR_INT_o => WB_TMR_INT,
|
TMR_INT_o => WB_TMR_INT,
|
FFLAGS_o => WB_FFLAGS,
|
FFLAGS_o => WB_FFLAGS,
|
FRM_o => WB_FRM,
|
FRM_o => WB_FRM,
|
IE_o => WB_IE,
|
IE_o => WB_IE,
|
CSRQ_o => WB_CSRQ,
|
CSRQ_o => WB_CSRQ,
|
-- Control port
|
-- Control port
|
CPQ_o => WB_CPQ
|
CPQ_o => WB_CPQ
|
);
|
);
|
|
|
WB_MMODE <= '1' when (
|
WB_MMODE <= '1' when (
|
WB_MSTATUS(2 downto 1) = "11"
|
WB_MSTATUS(2 downto 1) = "11"
|
) else '0';
|
) else '0';
|
|
|
-- Debug module
|
-- Debug module
|
|
|
GDM1_1 : if(DM_PRESENT = '1') generate
|
GDM1_1 : if(DM_PRESENT = '1') generate
|
|
|
-- Debug module
|
-- Debug module
|
|
|
U_DBGU : RV01_DBGU
|
U_DBGU : RV01_DBGU
|
generic map(
|
generic map(
|
NW => 2
|
NW => 2
|
)
|
)
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
RST_i => RST_i, -- pay attention!
|
RST_i => RST_i, -- pay attention!
|
HPC_i => IX3_HPC, --IX3_DHPC,
|
HPC_i => IX3_HPC, --IX3_DHPC,
|
MMODE_i => WB_MMODE,
|
MMODE_i => WB_MMODE,
|
NOPR_i => IX1_NOPR,
|
NOPR_i => IX1_NOPR,
|
HALT_i => IX3_HALT, --IX3_DHALT,
|
HALT_i => IX3_HALT, --IX3_DHALT,
|
CPRE_i => CP_RE_i,
|
CPRE_i => CP_RE_i,
|
CPWE_i => CP_WE_i,
|
CPWE_i => CP_WE_i,
|
CPADR_i => CP_ADR_i,
|
CPADR_i => CP_ADR_i,
|
CPD_i => CP_D_i,
|
CPD_i => CP_D_i,
|
|
|
RST_o => WB_DRST,
|
RST_o => WB_DRST,
|
HLTRQ_o => WB_DHLTRQ,
|
HLTRQ_o => WB_DHLTRQ,
|
RSM_o => WB_DRSM,
|
RSM_o => WB_DRSM,
|
DPC_o => WB_DPC,
|
DPC_o => WB_DPC,
|
DMODE_o => WB_DMODE,
|
DMODE_o => WB_DMODE,
|
DIE_o => WB_DIE,
|
DIE_o => WB_DIE,
|
HALTD_o => WB_HALTD,
|
HALTD_o => WB_HALTD,
|
STOPTIME_o => WB_STOPTIME,
|
STOPTIME_o => WB_STOPTIME,
|
STOPCYCLE_o => WB_STOPCYCLE,
|
STOPCYCLE_o => WB_STOPCYCLE,
|
SI_o => WB_DSI,
|
SI_o => WB_DSI,
|
HOBRK_o => WB_DHOBRK,
|
HOBRK_o => WB_DHOBRK,
|
STEP_o => WB_DSTEP,
|
STEP_o => WB_DSTEP,
|
FRCSI_o => WB_DFRCSI,
|
FRCSI_o => WB_DFRCSI,
|
CPQ_o => WB_DCPQ
|
CPQ_o => WB_DCPQ
|
);
|
);
|
|
|
-- Halt module (disabled)
|
-- Halt module (disabled)
|
|
|
WB_HALTD <= '0';
|
WB_HALTD <= '0';
|
WB_STRT <= '0';
|
WB_STRT <= '0';
|
WB_STRTPC <= (others => '0');
|
WB_STRTPC <= (others => '0');
|
WB_RSM <= '0';
|
WB_RSM <= '0';
|
WB_HLTURQ <= '0';
|
WB_HLTURQ <= '0';
|
WB_HLTOBRK <= '0';
|
WB_HLTOBRK <= '0';
|
WB_HLTOADR<= (others => '0');
|
WB_HLTOADR<= (others => '0');
|
WB_HLTADR <= (others => '0');
|
WB_HLTADR <= (others => '0');
|
WB_HCSRQ <= (others => '0');
|
WB_HCSRQ <= (others => '0');
|
WB_HCSR <= '0';
|
WB_HCSR <= '0';
|
WB_HILLG <= '0';
|
WB_HILLG <= '0';
|
WB_HCP <= '0';
|
WB_HCP <= '0';
|
WB_HCPQ <= (others => '0');
|
WB_HCPQ <= (others => '0');
|
|
|
end generate;
|
end generate;
|
|
|
GDM1_0 : if(DM_PRESENT = '0') generate
|
GDM1_0 : if(DM_PRESENT = '0') generate
|
|
|
-- Debug module (disabled)
|
-- Debug module (disabled)
|
|
|
WB_DRST <= '0';
|
WB_DRST <= '0';
|
WB_DHLTRQ <= '0';
|
WB_DHLTRQ <= '0';
|
WB_DRSM <= '0';
|
WB_DRSM <= '0';
|
WB_DPC <= (others => '0');
|
WB_DPC <= (others => '0');
|
WB_DMODE <= '0';
|
WB_DMODE <= '0';
|
WB_DIE <= '1';
|
WB_DIE <= '1';
|
WB_STOPTIME <= '0';
|
WB_STOPTIME <= '0';
|
WB_STOPCYCLE <= '0';
|
WB_STOPCYCLE <= '0';
|
WB_DSI <= (others => '0');
|
WB_DSI <= (others => '0');
|
WB_DHOBRK <= '0';
|
WB_DHOBRK <= '0';
|
WB_DSTEP <= '0';
|
WB_DSTEP <= '0';
|
WB_DFRCSI <= '0';
|
WB_DFRCSI <= '0';
|
WB_DCPQ <= (others => '0');
|
WB_DCPQ <= (others => '0');
|
|
|
-- Halt module
|
-- Halt module
|
|
|
U_HLTU : RV01_HLTU
|
U_HLTU : RV01_HLTU
|
generic map(
|
generic map(
|
PXE => PARALLEL_EXECUTION_ENABLED,
|
PXE => PARALLEL_EXECUTION_ENABLED,
|
NW => NW
|
NW => NW
|
)
|
)
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
RST_i => IRST,
|
RST_i => IRST,
|
IX1_V_i => ID_V_q,
|
IX1_V_i => ID_V_q,
|
IX2_V_i => IX1_V_q,
|
IX2_V_i => IX1_V_q,
|
NOPR_i => IX1_NOPR,
|
NOPR_i => IX1_NOPR,
|
MMODE_i => WB_MMODE,
|
MMODE_i => WB_MMODE,
|
HALT_i => IX3_HALT,
|
HALT_i => IX3_HALT,
|
HPC_i => IX3_HPC,
|
HPC_i => IX3_HPC,
|
CS_OP_i => ID_INSTR_q(0).CS_OP,
|
CS_OP_i => ID_INSTR_q(0).CS_OP,
|
RS1_i => ID_INSTR_q(0).RS1,
|
RS1_i => ID_INSTR_q(0).RS1,
|
ADR_i => ID_INSTR_q(0).IMM(12-1 downto 0),
|
ADR_i => ID_INSTR_q(0).IMM(12-1 downto 0),
|
WE_i => IX1_CP_WE,
|
WE_i => IX1_CP_WE,
|
CSRD_i => ID_OPA0_q,
|
CSRD_i => ID_OPA0_q,
|
CPRE_i => CP_RE_i,
|
CPRE_i => CP_RE_i,
|
CPWE_i => CP_WE_i,
|
CPWE_i => CP_WE_i,
|
CPADR_i => CP_ADR_i,
|
CPADR_i => CP_ADR_i,
|
CPD_i => CP_D_i,
|
CPD_i => CP_D_i,
|
|
|
HMODE_o => WB_HALTD,
|
HMODE_o => WB_HALTD,
|
STRT_o => WB_STRT,
|
STRT_o => WB_STRT,
|
STRTPC_o => WB_STRTPC,
|
STRTPC_o => WB_STRTPC,
|
RSM_o => WB_RSM,
|
RSM_o => WB_RSM,
|
HLTURQ_o => WB_HLTURQ,
|
HLTURQ_o => WB_HLTURQ,
|
HLTOBRK_o => WB_HLTOBRK,
|
HLTOBRK_o => WB_HLTOBRK,
|
HLTOADR_o => WB_HLTOADR,
|
HLTOADR_o => WB_HLTOADR,
|
HLTADR_o => WB_HLTADR,
|
HLTADR_o => WB_HLTADR,
|
CSRQ_o => WB_HCSRQ,
|
CSRQ_o => WB_HCSRQ,
|
HCSR_o => WB_HCSR,
|
HCSR_o => WB_HCSR,
|
ILLG_o => WB_HILLG,
|
ILLG_o => WB_HILLG,
|
HCP_o => WB_HCP,
|
HCP_o => WB_HCP,
|
CPQ_o => WB_HCPQ
|
CPQ_o => WB_HCPQ
|
);
|
);
|
|
|
end generate;
|
end generate;
|
|
|
-- Mux CSRU and HLTU/DBGU commmon output signals
|
-- Mux CSRU and HLTU/DBGU commmon output signals
|
|
|
U_CDCOMUX : RV01_CDCOMUX
|
U_CDCOMUX : RV01_CDCOMUX
|
generic map(
|
generic map(
|
DMP => DM_PRESENT
|
DMP => DM_PRESENT
|
)
|
)
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
HCSR_i => WB_HCSR,
|
HCSR_i => WB_HCSR,
|
HCSRQ_i => WB_HCSRQ,
|
HCSRQ_i => WB_HCSRQ,
|
CSRQ_i => WB_CSRQ,
|
CSRQ_i => WB_CSRQ,
|
HILLG_i => WB_HILLG,
|
HILLG_i => WB_HILLG,
|
ILLG_i => WB_ILLG,
|
ILLG_i => WB_ILLG,
|
CP_ADR_MSB_i => CP_ADR_i(16),
|
CP_ADR_MSB_i => CP_ADR_i(16),
|
HCP_i => WB_HCP,
|
HCP_i => WB_HCP,
|
HCPQ_i => WB_HCPQ,
|
HCPQ_i => WB_HCPQ,
|
CPQ_i => WB_CPQ,
|
CPQ_i => WB_CPQ,
|
DCPQ_i => WB_DCPQ,
|
DCPQ_i => WB_DCPQ,
|
STRT_i => WB_STRT,
|
STRT_i => WB_STRT,
|
DRSM_i => WB_DRSM,
|
DRSM_i => WB_DRSM,
|
DPC_i => WB_DPC,
|
DPC_i => WB_DPC,
|
STRTPC_i => WB_STRTPC,
|
STRTPC_i => WB_STRTPC,
|
|
|
ILLG_o => IX2_ILLG,
|
ILLG_o => IX2_ILLG,
|
CSRU_RES_o => IX2_CSRU_RES,
|
CSRU_RES_o => IX2_CSRU_RES,
|
CP_Q_o => CP_Q_o,
|
CP_Q_o => CP_Q_o,
|
STRT_o => WB_XSTRT,
|
STRT_o => WB_XSTRT,
|
STRTPC_o => WB_XSTRTPC
|
STRTPC_o => WB_XSTRTPC
|
);
|
);
|
|
|
----------------------------------------------------
|
----------------------------------------------------
|
-- Write-Back Checker
|
-- Write-Back Checker
|
----------------------------------------------------
|
----------------------------------------------------
|
|
|
-- synthesis translate_off
|
-- synthesis translate_off
|
|
|
G_WB : if(SIMULATION_ONLY = '1') generate
|
G_WB : if(SIMULATION_ONLY = '1') generate
|
|
|
WB_CHK_ENB <= CHK_ENB_i and not(WB_DMODE);
|
WB_CHK_ENB <= CHK_ENB_i and not(WB_DMODE);
|
|
|
U_WBCHK : RV01_WB_CHECKER
|
U_WBCHK : RV01_WB_CHECKER
|
generic map(
|
generic map(
|
WB_FILENAME => WB_FILENAME
|
WB_FILENAME => WB_FILENAME
|
)
|
)
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
ENB_i => WB_CHK_ENB,
|
ENB_i => WB_CHK_ENB,
|
WE0_i => IX3_WE(0),
|
WE0_i => IX3_WE(0),
|
WE1_i => IX3_WE(1),
|
WE1_i => IX3_WE(1),
|
IX_INSTR0_i => IX2_INSTR_q(0),
|
IX_INSTR0_i => IX2_INSTR_q(0),
|
IX_INSTR1_i => IX2_INSTR_q(1),
|
IX_INSTR1_i => IX2_INSTR_q(1),
|
IX_DRD0_i => IX3_DRD0,
|
IX_DRD0_i => IX3_DRD0,
|
IX_DRD1_i => IX3_DRD1
|
IX_DRD1_i => IX3_DRD1
|
);
|
);
|
|
|
end generate;
|
end generate;
|
|
|
-- synthesis translate_on
|
-- synthesis translate_on
|
|
|
----------------------------------------------------
|
----------------------------------------------------
|
-- Statistics
|
-- Statistics
|
----------------------------------------------------
|
----------------------------------------------------
|
|
|
-- synthesis translate_off
|
-- synthesis translate_off
|
|
|
G_STAT : if(SIMULATION_ONLY = '1') generate
|
G_STAT : if(SIMULATION_ONLY = '1') generate
|
|
|
U_STAT : RV01_STATS
|
U_STAT : RV01_STATS
|
port map(
|
port map(
|
CLK_i => CLK_i,
|
CLK_i => CLK_i,
|
RST_i => IRST,
|
RST_i => IRST,
|
ID_V_i => IF2_V_q,
|
ID_V_i => IF2_V_q,
|
ID_PS_i(0) => ID_PS(0),
|
ID_PS_i(0) => ID_PS(0),
|
ID_PS_i(1) => ID_PS(1),
|
ID_PS_i(1) => ID_PS(1),
|
ID_PXE1_i => ID_PXE1,
|
ID_PXE1_i => ID_PXE1,
|
IX2_V_i => IX2_V_q,
|
IX2_V_i => IX2_V_q,
|
STRT_i => STRT,
|
STRT_i => STRT,
|
HALT_i => IX3_HALT
|
HALT_i => IX3_HALT
|
);
|
);
|
|
|
end generate;
|
end generate;
|
|
|
-- synthesis translate_on
|
-- synthesis translate_on
|
|
|
end ARC;
|
end ARC;
|
|
|