Simply RISC S1 Core - Functional Specification
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S1 Core - Functional Specification
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==============================================
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==================================
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Preface
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Preface
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-------
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-------
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The S1 is a CPU core that makes use of a single SPARC Core
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The S1 is a CPU core that makes use of a single SPARC Core
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extracted from the OpenSPARC T1, with the addition of a
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extracted from the OpenSPARC T1, with the addition of a
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Wishbone Bridge, a Reset Controller and an Interrupt
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Wishbone Bridge, a Reset Controller and an Interrupt
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Controller.
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Controller.
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___________________________________
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___________________________________
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| Simply RISC S1 Core |
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| S1 Core |
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| _______ _____ ________ ________ |
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| _______ _____ ________ ________ |
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|| || || || ||
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|| || || || ||
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|| Reset || Int || SPARC ||Wishbone||
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|| Reset || Int || SPARC ||Wishbone||
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|| Ctrl. ||Ctrl.|| Core || Bridge ||
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|| Ctrl. ||Ctrl.|| Core || Bridge ||
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|| || || || ||
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|| || || || ||
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| ------- ----- ------- -------- |
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| ------- ----- ------- -------- |
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-----------------------------------
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-----------------------------------
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Instruction Set Architecture
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Instruction Set Architecture
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----------------------------
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----------------------------
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The CPU inside the S1 Core is the SPARC Core of the
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The CPU inside the S1 Core is the SPARC Core of the
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OpenSPARC T1 microprocessor, so you can read OpenSPARC
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OpenSPARC T1 microprocessor, so you can read OpenSPARC
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documents for the specification of this CPU.
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documents for the specification of this CPU.
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Basically it follows the SPARC v9 64-bit ISA, specified
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Basically it follows the SPARC v9 64-bit ISA, specified
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in the documents freely available on the opensparc.net
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in the documents freely available on the opensparc.net
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website; for the full documentation you also have to read
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website; for the full documentation you also have to read
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the datasheet and other specs included in the download
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the datasheet and other specs included in the download
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file of the T1 design.
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file of the T1 design.
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Software Support
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Software Support
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----------------
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----------------
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The SPARC v9 ISA is obviously supported by the GCC compiler;
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The SPARC v9 ISA is obviously supported by the GCC compiler;
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also GNU/Linux is supported and the latest versions of the
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also GNU/Linux is supported and the latest versions of the
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kernel are ready for the T1.
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kernel are ready for the T1.
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There's also a complete GNU/Linux distribution, Ubuntu,
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There's also a complete GNU/Linux distribution, Ubuntu,
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that comes ready for the SPARC Core of the T1 and could be
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that comes ready for the SPARC Core of the T1 and could be
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used in a seamless way also for Simply RISC S1 based micros.
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used in a seamless way also for S1 based micros.
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S1 Memory Map
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S1 Memory Map
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-------------
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-------------
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The S1 Core has 64-bit wide Data Bus and Address Bus.
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The S1 Core has 64-bit wide Data Bus and Address Bus.
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Each bit of the Address Bus has a different meaning:
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Each bit of the Address Bus has a different meaning:
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- bits [63:59] specify the one-hot encoding for the T1 target region number;
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- bits [63:59] specify the one-hot encoding for the T1 target region number;
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- bits [58:40] are 19 bits always hardwired to zero;
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- bits [58:40] are 19 bits always hardwired to zero;
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- bits [39:0] are the 40-bit Physical Address as it comes from the SPARC Core.
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- bits [39:0] are the 40-bit Physical Address as it comes from the SPARC Core.
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For most applications the lowest 40-bit address coming from the SPARC Core
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For most applications the lowest 40-bit address coming from the SPARC Core
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should be enough, so it should be safe to ignore the other bits (unless
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should be enough, so it should be safe to ignore the other bits (unless
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you suspect that for instance Physical Address zero in region 0 is
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you suspect that for instance Physical Address zero in region 0 is
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different from address zero in region 1 and so forth).
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different from address zero in region 1 and so forth).
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S1 Physical Address [63:56]
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S1 Physical Address [63:56]
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---------------------------
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---------------------------
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the first byte specifies the T1 target region number (one-hot encoded
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the first byte specifies the T1 target region number (one-hot encoded
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on the most significant 5 bits, the 3 least significant bits are
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on the most significant 5 bits, the 3 least significant bits are
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hardwired to zero):
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hardwired to zero):
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- 0x08 RAM Bank 0 (bit 59 set)
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- 0x08 RAM Bank 0 (bit 59 set)
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- 0x10 RAM Bank 1 (bit 60 set)
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- 0x10 RAM Bank 1 (bit 60 set)
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- 0x20 RAM Bank 2 (bit 61 set)
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- 0x20 RAM Bank 2 (bit 61 set)
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- 0x40 RAM Bank 3 (bit 62 set)
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- 0x40 RAM Bank 3 (bit 62 set)
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- 0x80 I/O Bridge (bit 63 set)
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- 0x80 I/O Bridge (bit 63 set)
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As you can see one of the five most significant bits of the
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As you can see one of the five most significant bits of the
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address must be always set depending on the target region.
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address must be always set depending on the target region.
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S1 Physical Address [39:32]
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S1 Physical Address [39:32]
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---------------------------
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---------------------------
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In the T1 bit 39 is zero for all memory addresses and 1 for I/O
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In the T1 bit 39 is zero for all memory addresses and 1 for I/O
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addresses. Then the T1, from which the S1 is derived, uses the
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addresses. Then the T1, from which the S1 is derived, uses the
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following memory map for bits [39:32] (please note that this
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following memory map for bits [39:32] (please note that this
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mapping is NOT used by the S1):
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mapping is NOT used by the S1):
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- 0x00-0x7F RAM
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- 0x00-0x7F RAM
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- 0x80 JBus
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- 0x80 JBus
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- 0x81-0x95
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- 0x81-0x95
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- 0x96 Clock Unit
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- 0x96 Clock Unit
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- 0x97 RAM Controller
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- 0x97 RAM Controller
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- 0x98 I/O Bridge Management Block
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- 0x98 I/O Bridge Management Block
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- 0x99 TAP Unit
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- 0x99 TAP Unit
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- 0x9A-0x9D
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- 0x9A-0x9D
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- 0x9E TAP2ASI
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- 0x9E TAP2ASI
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- 0x9F I/O Bridge Interrupt Table
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- 0x9F I/O Bridge Interrupt Table
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- 0xA0-0xBF L2 Control Registers
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- 0xA0-0xBF L2 Control Registers
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- 0xC0-0xFE JBus
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- 0xC0-0xFE JBus
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- 0xFF Boot ROM
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- 0xFF Boot ROM
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For the S1 Core the memory map is different and the following
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For the S1 Core the memory map is different and the following
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table applies:
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table applies:
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- 0x00-0x7F RAM
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- 0x00-0x7F RAM
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- 0x80-0x95
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- 0x80-0x95
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- 0x96 Real Time Clock
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- 0x96 Real Time Clock
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- 0x97 RAM Controller
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- 0x97 RAM Controller
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- 0x98 Wishbone Interconnect Arbiter
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- 0x98 Wishbone Interconnect Arbiter
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- 0x99 DMA Controller
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- 0x99 DMA Controller
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- 0x9A-0x9D
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- 0x9A-0x9D
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- 0x9E General Purpose I/O
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- 0x9E General Purpose I/O
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- 0x9F Interrupt Controller
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- 0x9F Interrupt Controller
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- 0xA0-0xFE
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- 0xA0-0xFE
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- 0xFF Boot ROM
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- 0xFF Boot ROM
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If you intend to use in your system not only the least significant
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If you intend to use in your system not only the least significant
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40 bits generated by the SPARC Core, take into account that for
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40 bits generated by the SPARC Core, take into account that for
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accesses not directed to RAM but to configuration registers it
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accesses not directed to RAM but to configuration registers it
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should be an access to the I/O region (bit 63 set), so for instance
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should be an access to the I/O region (bit 63 set), so for instance
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the full 64-bit base address for the Interrupt Controller should
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the full 64-bit base address for the Interrupt Controller should
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be 0x8000_009F_0000_0000.
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be 0x8000_009F_0000_0000.
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S1 Physical Address [2:0]
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S1 Physical Address [2:0]
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-------------------------
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-------------------------
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The S1 Core implements a Wishbone Master interface with a data bus
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The S1 Core implements a Wishbone Master interface with a data bus
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of 64 bits and a granularity of 1 byte.
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of 64 bits and a granularity of 1 byte.
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Then the address generated by the S1 is always aligned on 64-bit
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Then the address generated by the S1 is always aligned on 64-bit
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boundaries, i.e. bits [2:0] are always zero; the information
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boundaries, i.e. bits [2:0] are always zero; the information
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about the bytes that have to be accessed during a Wishbone
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about the bytes that have to be accessed during a Wishbone
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bus cycle is obviously encoded on the SEL signals described
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bus cycle is obviously encoded on the SEL signals described
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in the Wishbone spec.
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in the Wishbone spec.
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Reset Controller
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Reset Controller
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----------------
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----------------
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The boot sequence of the T1 is quite complex; we have then written
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The boot sequence of the T1 is quite complex; we have then written
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a reset controller for the S1 that just takes one reset signal
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a reset controller for the S1 that just takes one reset signal
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and generates all the signals required by the SPARC Core to boot
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and generates all the signals required by the SPARC Core to boot
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up properly.
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up properly.
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Interrupt Controller
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Interrupt Controller
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--------------------
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--------------------
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Early versions of the S1 Core feature a very basic Interrupt
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Early versions of the S1 Core feature a very basic Interrupt
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Controller that latches interrupt requests arriving to the core
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Controller that latches interrupt requests arriving to the core
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that are then signaled to the SPARC Core with the proper CPX
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that are then signaled to the SPARC Core with the proper CPX
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packet.
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packet.
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Currently this block is untested and it will be enhanced in
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Currently this block is untested and it will be enhanced in
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the future.
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the future.
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Wishbone Bridge
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Wishbone Bridge
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---------------
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---------------
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The eight SPARC Cores inside the OpenSPARC T1 microprocessor
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The eight SPARC Cores inside the OpenSPARC T1 microprocessor
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make use of a proprietary protocol to communicate with the
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make use of a proprietary protocol to communicate with the
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rest of the chip; this protocol is often referred to as
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rest of the chip; this protocol is often referred to as
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PCX/CPX protocol, where PCX stands for "Processor-to-Cache
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PCX/CPX protocol, where PCX stands for "Processor-to-Cache
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Xbar" and is used for the requests outgoing the SPARC Cores
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Xbar" and is used for the requests outgoing the SPARC Cores
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and CPX stands for "Cache-to-Processor Xbar" and is used for
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and CPX stands for "Cache-to-Processor Xbar" and is used for
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incoming packets.
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incoming packets.
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The main block designed specifically for the S1 Core is the
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The main block designed specifically for the S1 Core is the
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"SPARC Core to Wishbone Master interface bridge" that translates
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"SPARC Core to Wishbone Master interface bridge" that translates
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the requests and return packets of the SPARC Core into the
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the requests and return packets of the SPARC Core into the
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Wishbone protocol.
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Wishbone protocol.
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You can find the full specification of the Wishbone protocol
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You can find the full specification of the Wishbone protocol
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on the OpenCores site at http://www.opencores.org
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on the OpenCores site at http://www.opencores.org
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Interface Details
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Interface Details
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-----------------
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-----------------
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These are the features of the bus interface of the S1 Core
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These are the features of the bus interface of the S1 Core
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(they can also be referred to as "Wishbone Datasheet"):
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(they can also be referred to as "Wishbone Datasheet"):
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- Wishbone Master interface that follows revision B.3;
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- Wishbone Master interface that follows revision B.3;
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- standard signals names identified by leading "wbm_" chars;
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- standard signals names identified by leading "wbm_" chars;
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- no ERR/RTY support;
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- no ERR/RTY support;
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- 64-bit Address Bus (with some bits unused, see above);
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- 64-bit Address Bus (with some bits unused, see above);
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- 64-bit Data Bus supporting 8, 16, 32 and 64 bit accesses;
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- 64-bit Data Bus supporting 8, 16, 32 and 64 bit accesses;
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- data transfer ordering is Big Endian;
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- data transfer ordering is Big Endian;
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- supports Single Read/Write Cycles.
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- supports Single Read/Write Cycles.
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