// ========== Copyright Header Begin ==========================================
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// ========== Copyright Header Begin ==========================================
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//
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//
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// OpenSPARC T1 Processor File: bw_r_irf_register.v
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// OpenSPARC T1 Processor File: bw_r_irf_register.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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//
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// The above named program is free software; you can redistribute it and/or
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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// License version 2 as published by the Free Software Foundation.
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//
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//
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// The above named program is distributed in the hope that it will be
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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// General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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`ifdef FPGA_SYN_1THREAD
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`ifdef FPGA_SYN_SAVE_BRAM
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module bw_r_irf_register(clk, wren, save, save_addr, restore, restore_addr, wr_data, rd_data);
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input clk;
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input wren;
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input save;
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input [2:0] save_addr;
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input restore;
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input [2:0] restore_addr;
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input [71:0] wr_data;
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output [71:0] rd_data;
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`ifdef FPGA_SYN_ALTERA
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reg [35:0] window[15:0]/* synthesis syn_ramstyle = block_ram*/; // syn_ramstyle = no_rw_check */;
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`else
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reg [35:0] window[15:0]/* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */;
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`endif
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reg [71:0] onereg;
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initial onereg = 72'h0;
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assign rd_data = onereg;
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reg [71:0] restore_data;
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wire [71:0] wrdata = restore ? restore_data : wr_data;
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wire wr_en = wren | restore;
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always @(posedge clk) begin
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if(wr_en) onereg <= wrdata;
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end
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wire [2:0] addr = save ? save_addr : restore_addr;
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wire [3:0] addr1 = {1'b1, addr};
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wire [3:0] addr0 = {1'b0, addr};
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always @(negedge clk) begin
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if(save) window[addr1] <= wren ? wr_data[71:36] : rd_data[71:36];
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else restore_data[71:36] <= window[addr1];
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end
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always @(negedge clk) begin
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if(save) window[addr0] <= wren ? wr_data[35:0] : rd_data[35:0];
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else restore_data[35:0] <= window[addr0];
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end
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endmodule
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`else
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module bw_r_irf_register(clk, wren, save, save_addr, restore, restore_addr, wr_data, rd_data);
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input clk;
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input wren;
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input save;
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input [2:0] save_addr;
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input restore;
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input [2:0] restore_addr;
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input [71:0] wr_data;
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output [71:0] rd_data;
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`ifdef FPGA_SYN_ALTERA
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reg [71:0] window[7:0]/* synthesis syn_ramstyle = block_ram*/; // syn_ramstyle = no_rw_check */;
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`else
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reg [71:0] window[7:0]/* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */;
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`endif
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reg [71:0] onereg;
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reg [2:0] rd_addr;
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reg [2:0] wr_addr;
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reg save_d;
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`ifdef FPGA_SYN_ALTERA
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integer k;
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initial
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begin
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for (k = 0; k < 8 ; k = k + 1)
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begin
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window[k] = 72'h0;
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end
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end
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`endif
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initial
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begin
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onereg = 72'b0;
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wr_addr = 3'h0;
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rd_addr = 3'h0;
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end
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always @(negedge clk) begin
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rd_addr = restore_addr;
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end
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always @(posedge clk) begin
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wr_addr <= save_addr;
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end
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always @(posedge clk) begin
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save_d <= save;
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end
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assign rd_data = onereg;
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wire [71:0] restore_data = window[rd_addr];
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wire [71:0] wrdata = restore ? restore_data : wr_data;
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wire wr_en = wren | (restore & (wr_addr != rd_addr));
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always @(posedge clk) begin
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if(wr_en) onereg <= wrdata;
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end
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always @(negedge clk) begin
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if(save_d) window[wr_addr] <= rd_data;
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end
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endmodule
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`endif
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`else
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module bw_r_irf_register(clk, wrens, save, save_addr, restore, restore_addr, wr_data0, wr_data1, wr_data2, wr_data3, rd_thread, rd_data);
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module bw_r_irf_register(clk, wrens, save, save_addr, restore, restore_addr, wr_data0, wr_data1, wr_data2, wr_data3, rd_thread, rd_data);
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input clk;
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input clk;
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input [3:0] wrens;
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input [3:0] wrens;
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input save;
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input save;
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input [4:0] save_addr;
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input [4:0] save_addr;
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input restore;
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input restore;
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input [4:0] restore_addr;
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input [4:0] restore_addr;
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input [71:0] wr_data0;
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input [71:0] wr_data0;
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input [71:0] wr_data1;
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input [71:0] wr_data1;
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input [71:0] wr_data2;
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input [71:0] wr_data2;
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input [71:0] wr_data3;
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input [71:0] wr_data3;
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input [1:0] rd_thread;
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input [1:0] rd_thread;
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output [71:0] rd_data;
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output [71:0] rd_data;
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`ifdef FPGA_SYN_ALTERA
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reg [71:0] window[31:0]/* synthesis syn_ramstyle = block_ram*/; // syn_ramstyle = no_rw_check */;
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`else
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reg [71:0] window[31:0]/* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */;
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reg [71:0] window[31:0]/* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */;
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`endif
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reg [71:0] reg_th0, reg_th1, reg_th2, reg_th3;
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reg [71:0] reg_th0, reg_th1, reg_th2, reg_th3;
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reg [4:0] rd_addr;
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reg [4:0] rd_addr;
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reg [4:0] wr_addr;
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reg [4:0] wr_addr;
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reg save_d;
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reg save_d;
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initial begin
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initial begin
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reg_th0 = 72'b0;
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reg_th0 = 72'b0;
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reg_th1 = 72'b0;
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reg_th1 = 72'b0;
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reg_th2 = 72'b0;
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reg_th2 = 72'b0;
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reg_th3 = 72'b0;
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reg_th3 = 72'b0;
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end
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end
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bw_r_irf_72_4x1_mux mux4_1(
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bw_r_irf_72_4x1_mux mux4_1(
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.sel(rd_thread),
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.sel(rd_thread),
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.x0(reg_th0),
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.x0(reg_th0),
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.x1(reg_th1),
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.x1(reg_th1),
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.x2(reg_th2),
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.x2(reg_th2),
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.x3(reg_th3),
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.x3(reg_th3),
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.y(rd_data)
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.y(rd_data)
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);
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);
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always @(negedge clk) begin
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always @(negedge clk) begin
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rd_addr = restore_addr;
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rd_addr = restore_addr;
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end
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end
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wire [71:0] restore_data = window[rd_addr];
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wire [71:0] restore_data = window[rd_addr];
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always @(posedge clk) begin
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always @(posedge clk) begin
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wr_addr <= save_addr;
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wr_addr <= save_addr;
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end
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end
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always @(posedge clk) begin
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always @(posedge clk) begin
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save_d <= save;
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save_d <= save;
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end
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end
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wire [71:0] save_data;
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wire [71:0] save_data;
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bw_r_irf_72_4x1_mux mux4_2(
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bw_r_irf_72_4x1_mux mux4_2(
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.sel(wr_addr[4:3]),
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.sel(wr_addr[4:3]),
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.x0(reg_th0),
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.x0(reg_th0),
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.x1(reg_th1),
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.x1(reg_th1),
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.x2(reg_th2),
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.x2(reg_th2),
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.x3(reg_th3),
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.x3(reg_th3),
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.y(save_data)
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.y(save_data)
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);
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);
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always @(negedge clk) begin
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always @(negedge clk) begin
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if(save_d) window[wr_addr] <= save_data;
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if(save_d) window[wr_addr] <= save_data;
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end
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end
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//Register implementation for 4 threads / 2 write & 1 restore port
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//Register implementation for 4 threads / 2 write & 1 restore port
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wire [3:0] restores = (1'b1 << rd_addr[4:3]) & {4{restore}};
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wire [3:0] restores = (1'b1 << rd_addr[4:3]) & {4{restore}};
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//wire [3:0] wren1s = (1'b1 << wr1_th) & {4{wren1}};
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//wire [3:0] wren1s = (1'b1 << wr1_th) & {4{wren1}};
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//wire [3:0] wren2s = (1'b1 << wr2_th) & {4{wren2}};
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//wire [3:0] wren2s = (1'b1 << wr2_th) & {4{wren2}};
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wire [71:0] wrdata0, wrdata1, wrdata2, wrdata3;
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wire [71:0] wrdata0, wrdata1, wrdata2, wrdata3;
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bw_r_irf_72_2x1_mux mux2_5(
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bw_r_irf_72_2x1_mux mux2_5(
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.sel(restores[0]),
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.sel(restores[0]),
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.x0(wr_data0),
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.x0(wr_data0),
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.x1(restore_data),
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.x1(restore_data),
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.y(wrdata0)
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.y(wrdata0)
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);
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);
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bw_r_irf_72_2x1_mux mux2_6(
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bw_r_irf_72_2x1_mux mux2_6(
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.sel(restores[1]),
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.sel(restores[1]),
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.x0(wr_data1),
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.x0(wr_data1),
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.x1(restore_data),
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.x1(restore_data),
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.y(wrdata1)
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.y(wrdata1)
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);
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);
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bw_r_irf_72_2x1_mux mux2_7(
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bw_r_irf_72_2x1_mux mux2_7(
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.sel(restores[2]),
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.sel(restores[2]),
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.x0(wr_data2),
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.x0(wr_data2),
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.x1(restore_data),
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.x1(restore_data),
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.y(wrdata2)
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.y(wrdata2)
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);
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);
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bw_r_irf_72_2x1_mux mux2_8(
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bw_r_irf_72_2x1_mux mux2_8(
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.sel(restores[3]),
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.sel(restores[3]),
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.x0(wr_data3),
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.x0(wr_data3),
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.x1(restore_data),
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.x1(restore_data),
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.y(wrdata3)
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.y(wrdata3)
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);
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);
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//wire [3:0] wr_en = wren1s | wren2s | (restores & {4{(wr_addr[4:0] != rd_addr[4:0])}});
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//wire [3:0] wr_en = wren1s | wren2s | (restores & {4{(wr_addr[4:0] != rd_addr[4:0])}});
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wire [3:0] wr_en = wrens | (restores & {4{(wr_addr[4:0] != rd_addr[4:0])}});
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wire [3:0] wr_en = wrens | (restores & {4{(wr_addr[4:0] != rd_addr[4:0])}});
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//288 Flops
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//288 Flops
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always @(posedge clk) begin
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always @(posedge clk) begin
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if(wr_en[0]) reg_th0 <= wrdata0;
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if(wr_en[0]) reg_th0 <= wrdata0;
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if(wr_en[1]) reg_th1 <= wrdata1;
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if(wr_en[1]) reg_th1 <= wrdata1;
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if(wr_en[2]) reg_th2 <= wrdata2;
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if(wr_en[2]) reg_th2 <= wrdata2;
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if(wr_en[3]) reg_th3 <= wrdata3;
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if(wr_en[3]) reg_th3 <= wrdata3;
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end
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end
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endmodule
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endmodule
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module bw_r_irf_72_4x1_mux(sel, y, x0, x1, x2, x3);
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module bw_r_irf_72_4x1_mux(sel, y, x0, x1, x2, x3);
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input [1:0] sel;
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input [1:0] sel;
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input [71:0] x0;
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input [71:0] x0;
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input [71:0] x1;
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input [71:0] x1;
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input [71:0] x2;
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input [71:0] x2;
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input [71:0] x3;
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input [71:0] x3;
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output [71:0] y;
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output [71:0] y;
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reg [71:0] y;
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reg [71:0] y;
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always @(sel or x0 or x1 or x2 or x3)
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always @(sel or x0 or x1 or x2 or x3)
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case(sel)
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case(sel)
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2'b00: y = x0;
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2'b00: y = x0;
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2'b01: y = x1;
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2'b01: y = x1;
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2'b10: y = x2;
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2'b10: y = x2;
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2'b11: y = x3;
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2'b11: y = x3;
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endcase
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endcase
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endmodule
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endmodule
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module bw_r_irf_72_2x1_mux(sel, y, x0, x1);
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module bw_r_irf_72_2x1_mux(sel, y, x0, x1);
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input sel;
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input sel;
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input [71:0] x0;
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input [71:0] x0;
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input [71:0] x1;
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input [71:0] x1;
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output [71:0] y;
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output [71:0] y;
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reg [71:0] y;
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reg [71:0] y;
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always @(sel or x0 or x1)
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always @(sel or x0 or x1)
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case(sel)
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case(sel)
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1'b0: y = x0;
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1'b0: y = x0;
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1'b1: y = x1;
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1'b1: y = x1;
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endcase
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endcase
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endmodule
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endmodule
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`endif
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