// ========== Copyright Header Begin ==========================================
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// ========== Copyright Header Begin ==========================================
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//
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//
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// OpenSPARC T1 Processor File: bw_r_rf16x32.v
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// OpenSPARC T1 Processor File: bw_r_rf16x32.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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//
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// The above named program is free software; you can redistribute it and/or
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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// License version 2 as published by the Free Software Foundation.
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//
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//
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// The above named program is distributed in the hope that it will be
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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// General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/*
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/*
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// Module Name: bw_r_rf16x32
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// Module Name: bw_r_rf16x32
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// Description:
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// Description:
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// 1r1w array for icache and dcache valid bits.
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// 1r1w array for icache and dcache valid bits.
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// Modified to conform to naming convention
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// Modified to conform to naming convention
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// Added 16 bit wr en
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// Added 16 bit wr en
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// Made bit_wen and din flopped inputs
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// Made bit_wen and din flopped inputs
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// So all inputs are setup to flops in the stage before memory
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// So all inputs are setup to flops in the stage before memory
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// access. The data output is available one cycle later (same
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// access. The data output is available one cycle later (same
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// stage as mem access)
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// stage as mem access)
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//
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//
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// IMPORTANT NOTE: This block has to work even in the case where
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// IMPORTANT NOTE: This block has to work even in the case where
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// there is contention between a read and write operation for the
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// there is contention between a read and write operation for the
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// same address. Based on ease of implementation, the behavior
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// same address. Based on ease of implementation, the behavior
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// during contention is defined as follows.
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// during contention is defined as follows.
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// -- write always succeeds
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// -- write always succeeds
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// -- read data is (array_data & write_data)
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// -- read data is (array_data & write_data)
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// (i.e. old_data & new_data)
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// (i.e. old_data & new_data)
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//
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//
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// So read 0 always succeeds. read 1 succeeds if the data being
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// So read 0 always succeeds. read 1 succeeds if the data being
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// written is also a 1. Otherwise it fails.
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// written is also a 1. Otherwise it fails.
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//
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//
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// new_data = 1, old_data = 0, does not give the expected or
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// new_data = 1, old_data = 0, does not give the expected or
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// predictable result in post layout, so the code has been modified
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// predictable result in post layout, so the code has been modified
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// to be
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// to be
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// old new rd_data
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// old new rd_data
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// --- --- -------
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// --- --- -------
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// 0 0 0
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// 0 0 0
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// 0 1 X
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// 0 1 X
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// 1 0 0
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// 1 0 0
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// 1 1 1
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// 1 1 1
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//
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//
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// **The write still succeeds in ALL cases**
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// **The write still succeeds in ALL cases**
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*/
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*/
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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// Global header file includes
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// Global header file includes
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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//`include "sys.h" // system level definition file which contains the
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//`include "sys.h" // system level definition file which contains the
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// time scale definition
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// time scale definition
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//`include "iop.h"
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//`include "iop.h"
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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// Local header file includes / local defines
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// Local header file includes / local defines
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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//FPGA_SYN enables all FPGA related modifications
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//FPGA_SYN enables all FPGA related modifications
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`ifdef FPGA_SYN
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`define FPGA_SYN_IDCT
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`endif
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module bw_r_rf16x32 (/*AUTOARG*/
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module bw_r_rf16x32 (/*AUTOARG*/
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// Outputs
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// Outputs
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dout, so,
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dout, so,
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// Inputs
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// Inputs
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rclk, se, si, reset_l, sehold, rst_tri_en, rd_adr1, rd_adr2,
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rclk, se, si, reset_l, sehold, rst_tri_en, rd_adr1, rd_adr2,
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rd_adr1_sel, rd_en, wr_adr, wr_en, bit_wen, din
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rd_adr1_sel, rd_en, wr_adr, wr_en, bit_wen, din
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);
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);
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input rclk;
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input rclk;
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input se;
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input se;
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input si;
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input si;
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input reset_l;
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input reset_l;
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input sehold; // scan enable hold
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input sehold; // scan enable hold
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input rst_tri_en;
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input rst_tri_en;
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// 11:5(I);10:4(D)
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// 11:5(I);10:4(D)
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input [6:0] rd_adr1 ; // rd address-1
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input [6:0] rd_adr1 ; // rd address-1
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input [6:0] rd_adr2 ; // rd address-2
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input [6:0] rd_adr2 ; // rd address-2
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input rd_adr1_sel ; // sel rd addr 1
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input rd_adr1_sel ; // sel rd addr 1
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input rd_en ; // rd enable
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input rd_en ; // rd enable
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// 11:7(I);10:6(D)
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// 11:7(I);10:6(D)
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input [6:2] wr_adr ; // wr address
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input [6:2] wr_adr ; // wr address
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input wr_en ; // wr enable
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input wr_en ; // wr enable
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input [15:0] bit_wen ; // write enable with bit select
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input [15:0] bit_wen ; // write enable with bit select
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input din ; // write data
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input din ; // write data
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output [3:0] dout ; // valid bits for tag compare
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output [3:0] dout ; // valid bits for tag compare
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output so;
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output so;
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wire clk;
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wire clk;
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assign clk = rclk;
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assign clk = rclk;
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Declarations
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// Declarations
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// local signals
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// local signals
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wire [6:0] rd_index ;
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wire [6:0] rd_index ;
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// 512 bit array
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// 512 bit array
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`ifdef FPGA_SYN_IDCT
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reg [31:0] idcv_ary_0000;
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reg [31:0] idcv_ary_0000;
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reg [31:0] idcv_ary_0001;
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reg [31:0] idcv_ary_0001;
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reg [31:0] idcv_ary_0010;
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reg [31:0] idcv_ary_0010;
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reg [31:0] idcv_ary_0011;
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reg [31:0] idcv_ary_0011;
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reg [31:0] idcv_ary_0100;
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reg [31:0] idcv_ary_0100;
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reg [31:0] idcv_ary_0101;
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reg [31:0] idcv_ary_0101;
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reg [31:0] idcv_ary_0110;
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reg [31:0] idcv_ary_0110;
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reg [31:0] idcv_ary_0111;
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reg [31:0] idcv_ary_0111;
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reg [31:0] idcv_ary_1000;
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reg [31:0] idcv_ary_1000;
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reg [31:0] idcv_ary_1001;
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reg [31:0] idcv_ary_1001;
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reg [31:0] idcv_ary_1010;
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reg [31:0] idcv_ary_1010;
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reg [31:0] idcv_ary_1011;
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reg [31:0] idcv_ary_1011;
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reg [31:0] idcv_ary_1100;
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reg [31:0] idcv_ary_1100;
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reg [31:0] idcv_ary_1101;
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reg [31:0] idcv_ary_1101;
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reg [31:0] idcv_ary_1110;
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reg [31:0] idcv_ary_1110;
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reg [31:0] idcv_ary_1111;
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reg [31:0] idcv_ary_1111;
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`else
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reg [511:0] idcv_ary;
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`endif
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reg [3:0] vbit,
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reg [3:0] vbit,
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vbit_sa;
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vbit_sa;
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reg [6:2] wr_index_d1;
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reg [6:2] wr_index_d1;
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reg [6:0] rd_index_d1;
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reg [6:0] rd_index_d1;
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reg rdreq_d1,
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reg rdreq_d1,
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wrreq_d1;
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wrreq_d1;
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reg [15:0] bit_wen_d1;
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reg [15:0] bit_wen_d1;
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reg din_d1;
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reg din_d1;
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reg [4:0] index;
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wire rst_all;
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wire rst_all;
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Code Begins Here
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// Code Begins Here
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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assign rst_all = rst_tri_en | ~reset_l;
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assign rst_all = rst_tri_en | ~reset_l;
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// mux merged with flop on index
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// mux merged with flop on index
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assign rd_index = rd_adr1_sel ? rd_adr1:rd_adr2 ;
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assign rd_index = rd_adr1_sel ? rd_adr1:rd_adr2 ;
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// input flops
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// input flops
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (~sehold)
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if (~sehold)
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begin
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begin
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rdreq_d1 <= rd_en ;
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rdreq_d1 <= rd_en ;
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wrreq_d1 <= wr_en ;
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wrreq_d1 <= wr_en ;
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rd_index_d1 <= rd_index;
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rd_index_d1 <= rd_index;
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wr_index_d1 <= wr_adr;
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wr_index_d1 <= wr_adr;
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bit_wen_d1 <= bit_wen;
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bit_wen_d1 <= bit_wen;
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din_d1 <= din;
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din_d1 <= din;
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end
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end
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end
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end
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Read Operation
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// Read Operation
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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`ifdef FPGA_SYN_IDCT
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always @(/*AUTOSENSE*/
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always @(/*AUTOSENSE*/
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idcv_ary_0000 or idcv_ary_0001 or idcv_ary_0010 or idcv_ary_0011 or
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idcv_ary_0000 or idcv_ary_0001 or idcv_ary_0010 or idcv_ary_0011 or
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idcv_ary_0100 or idcv_ary_1001 or idcv_ary_1010 or idcv_ary_0111 or
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idcv_ary_0100 or idcv_ary_1001 or idcv_ary_1010 or idcv_ary_0111 or
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idcv_ary_1000 or idcv_ary_0101 or idcv_ary_0110 or idcv_ary_1011 or
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idcv_ary_1000 or idcv_ary_0101 or idcv_ary_0110 or idcv_ary_1011 or
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idcv_ary_1100 or idcv_ary_1101 or idcv_ary_1110 or idcv_ary_1111 or rd_index_d1 or rdreq_d1)
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idcv_ary_1100 or idcv_ary_1101 or idcv_ary_1110 or idcv_ary_1111 or rd_index_d1 or rdreq_d1)
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`else
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always @(/*AUTOSENSE*/idcv_ary or rd_index_d1 or rdreq_d1)
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`endif
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begin
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begin
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if (rdreq_d1) // should work even if there is read
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if (rdreq_d1) // should work even if there is read
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// write conflict. Data can be latest
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// write conflict. Data can be latest
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// or previous but should not be x
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// or previous but should not be x
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begin
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begin
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`ifdef FPGA_SYN_IDCT
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case(rd_index_d1[1:0])
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case(rd_index_d1[1:0])
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2'b00: begin
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2'b00: begin
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vbit[0] = idcv_ary_0000[{rd_index_d1[6:2]}];
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vbit[0] = idcv_ary_0000[{rd_index_d1[6:2]}];
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vbit[1] = idcv_ary_0001[{rd_index_d1[6:2]}];
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vbit[1] = idcv_ary_0001[{rd_index_d1[6:2]}];
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vbit[2] = idcv_ary_0010[{rd_index_d1[6:2]}];
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vbit[2] = idcv_ary_0010[{rd_index_d1[6:2]}];
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vbit[3] = idcv_ary_0011[{rd_index_d1[6:2]}];
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vbit[3] = idcv_ary_0011[{rd_index_d1[6:2]}];
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end
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end
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2'b01: begin
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2'b01: begin
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vbit[0] = idcv_ary_0100[{rd_index_d1[6:2]}];
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vbit[0] = idcv_ary_0100[{rd_index_d1[6:2]}];
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vbit[1] = idcv_ary_0101[{rd_index_d1[6:2]}];
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vbit[1] = idcv_ary_0101[{rd_index_d1[6:2]}];
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vbit[2] = idcv_ary_0110[{rd_index_d1[6:2]}];
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vbit[2] = idcv_ary_0110[{rd_index_d1[6:2]}];
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vbit[3] = idcv_ary_0111[{rd_index_d1[6:2]}];
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vbit[3] = idcv_ary_0111[{rd_index_d1[6:2]}];
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end
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end
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2'b10: begin
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2'b10: begin
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vbit[0] = idcv_ary_1000[{rd_index_d1[6:2]}];
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vbit[0] = idcv_ary_1000[{rd_index_d1[6:2]}];
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vbit[1] = idcv_ary_1001[{rd_index_d1[6:2]}];
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vbit[1] = idcv_ary_1001[{rd_index_d1[6:2]}];
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vbit[2] = idcv_ary_1010[{rd_index_d1[6:2]}];
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vbit[2] = idcv_ary_1010[{rd_index_d1[6:2]}];
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vbit[3] = idcv_ary_1011[{rd_index_d1[6:2]}];
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vbit[3] = idcv_ary_1011[{rd_index_d1[6:2]}];
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end
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end
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2'b11: begin
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2'b11: begin
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vbit[0] = idcv_ary_1100[{rd_index_d1[6:2]}];
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vbit[0] = idcv_ary_1100[{rd_index_d1[6:2]}];
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vbit[1] = idcv_ary_1101[{rd_index_d1[6:2]}];
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vbit[1] = idcv_ary_1101[{rd_index_d1[6:2]}];
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vbit[2] = idcv_ary_1110[{rd_index_d1[6:2]}];
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vbit[2] = idcv_ary_1110[{rd_index_d1[6:2]}];
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vbit[3] = idcv_ary_1111[{rd_index_d1[6:2]}];
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vbit[3] = idcv_ary_1111[{rd_index_d1[6:2]}];
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end
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end
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endcase
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endcase
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`else
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vbit[0] = idcv_ary[{rd_index_d1, 2'b00}]; // way 0
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vbit[1] = idcv_ary[{rd_index_d1, 2'b01}]; // way 1
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vbit[2] = idcv_ary[{rd_index_d1, 2'b10}]; // way 2
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vbit[3] = idcv_ary[{rd_index_d1, 2'b11}]; // way 3
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`endif
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end // if (rdreq_d1)
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end // if (rdreq_d1)
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else // i/dcache disabled or rd disabled
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else // i/dcache disabled or rd disabled
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begin
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begin
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vbit[3:0] = 4'bx;
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vbit[3:0] = 4'bx;
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end // else: !if(rdreq_d1)
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end // else: !if(rdreq_d1)
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end // always @ (...
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end // always @ (...
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// r-w conflict case, returns old_data & new_data
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// r-w conflict case, returns old_data & new_data
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// 12/06 modified to be
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// 12/06 modified to be
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// 0 0 0
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// 0 0 0
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// 0 1 X
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// 0 1 X
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// 1 0 0
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// 1 0 0
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// 1 1 1
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// 1 1 1
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`ifdef FPGA_SYN_IDCT
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initial
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begin
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for(index = 5'h0; index < 5'h1f; index = index+1)
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begin
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idcv_ary_0000[index] = 1'b0;
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idcv_ary_0001[index] = 1'b0;
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idcv_ary_0010[index] = 1'b0;
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idcv_ary_0011[index] = 1'b0;
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idcv_ary_0100[index] = 1'b0;
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idcv_ary_0101[index] = 1'b0;
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idcv_ary_0110[index] = 1'b0;
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idcv_ary_0111[index] = 1'b0;
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idcv_ary_1000[index] = 1'b0;
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idcv_ary_1001[index] = 1'b0;
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idcv_ary_1010[index] = 1'b0;
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idcv_ary_1011[index] = 1'b0;
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idcv_ary_1100[index] = 1'b0;
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idcv_ary_1101[index] = 1'b0;
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idcv_ary_1110[index] = 1'b0;
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idcv_ary_1111[index] = 1'b0;
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end
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end
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`endif
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reg [3:0] wr_data;
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reg [3:0] wr_data;
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always @ (/*AUTOSENSE*/bit_wen_d1 or rd_index_d1 or rst_all
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always @ (/*AUTOSENSE*/bit_wen_d1 or rd_index_d1 or rst_all
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or wr_index_d1 or wrreq_d1)
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or wr_index_d1 or wrreq_d1)
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begin
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begin
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if (rd_index_d1[6:2] == wr_index_d1[6:2])
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if (rd_index_d1[6:2] == wr_index_d1[6:2])
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case (rd_index_d1[1:0])
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case (rd_index_d1[1:0])
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2'b00: wr_data = bit_wen_d1[3:0] & {4{wrreq_d1 & ~rst_all}};
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2'b00: wr_data = bit_wen_d1[3:0] & {4{wrreq_d1 & ~rst_all}};
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2'b01: wr_data = bit_wen_d1[7:4] & {4{wrreq_d1 & ~rst_all}};
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2'b01: wr_data = bit_wen_d1[7:4] & {4{wrreq_d1 & ~rst_all}};
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2'b10: wr_data = bit_wen_d1[11:8] & {4{wrreq_d1 & ~rst_all}};
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2'b10: wr_data = bit_wen_d1[11:8] & {4{wrreq_d1 & ~rst_all}};
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default: wr_data = bit_wen_d1[15:12] & {4{wrreq_d1 & ~rst_all}};
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default: wr_data = bit_wen_d1[15:12] & {4{wrreq_d1 & ~rst_all}};
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endcase // case(rd_index_d1[1:0])
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endcase // case(rd_index_d1[1:0])
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else
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else
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wr_data = 4'b0;
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wr_data = 4'b0;
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end
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end
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`ifdef FPGA_SYN_IDCT
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assign dout[3:0] = (~reset_l | ~rdreq_d1) ? 4'b0000 :
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assign dout[3:0] = (~reset_l | ~rdreq_d1) ? 4'b0000 :
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(~wr_data & vbit | wr_data & {4{din_d1}} & vbit);
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(~wr_data & vbit | wr_data & {4{din_d1}} & vbit);
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`else
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// SA latch -- to make 0in happy
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always @ (/*AUTOSENSE*/clk or din_d1 or vbit or wr_data)
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begin
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if (clk)
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begin
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vbit_sa <= (~wr_data & vbit |
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wr_data & {4{din_d1}} & (vbit | 4'bxxxx));
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end
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end
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// bug:2776 - remove holding the last read value
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// reset_l rdreq_d1 dout
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// 0 - 0
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// 1 0 0
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// 1 1 vbit_sa
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assign dout[3:0] = (~reset_l | ~rdreq_d1) ? 4'b0000 : vbit_sa[3:0] ;
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`endif
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Write Operation
|
// Write Operation
|
//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Invalidate/Write occurs on 16B boundary.
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// Invalidate/Write occurs on 16B boundary.
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// For this purpose, 4x4 write-enables are required.
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// For this purpose, 4x4 write-enables are required.
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// Index thus corresponds to 11:7,6:5,w[1:0], where w=way (ICache)
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// Index thus corresponds to 11:7,6:5,w[1:0], where w=way (ICache)
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// Index thus corresponds to 10:6,5:4,w[1:0], where w=way (DCache)
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// Index thus corresponds to 10:6,5:4,w[1:0], where w=way (DCache)
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// Thru data-in, vld bit can be set or cleared.
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// Thru data-in, vld bit can be set or cleared.
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always @ (negedge clk)
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always @ (negedge clk)
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begin
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begin
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if (wrreq_d1 & ~rst_all) // should work even if rd-wr conflict
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if (wrreq_d1 & ~rst_all) // should work even if rd-wr conflict
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begin
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begin
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// line 0 (5:4=00)
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// line 0 (5:4=00)
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`ifdef FPGA_SYN_IDCT
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if (bit_wen_d1[0]) idcv_ary_0000[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[0]) idcv_ary_0000[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[1]) idcv_ary_0001[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[1]) idcv_ary_0001[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[2]) idcv_ary_0010[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[2]) idcv_ary_0010[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[3]) idcv_ary_0011[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[3]) idcv_ary_0011[{wr_index_d1[6:2]}] = din_d1;
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`else
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if (bit_wen_d1[0])
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idcv_ary[{wr_index_d1[6:2],2'b00,2'b00}] = din_d1;
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if (bit_wen_d1[1])
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idcv_ary[{wr_index_d1[6:2],2'b00,2'b01}] = din_d1;
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if (bit_wen_d1[2])
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idcv_ary[{wr_index_d1[6:2],2'b00,2'b10}] = din_d1;
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if (bit_wen_d1[3])
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idcv_ary[{wr_index_d1[6:2],2'b00,2'b11}] = din_d1;
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`endif
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// line 1 (5:4=01)
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// line 1 (5:4=01)
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`ifdef FPGA_SYN_IDCT
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if (bit_wen_d1[4]) idcv_ary_0100[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[4]) idcv_ary_0100[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[5]) idcv_ary_0101[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[5]) idcv_ary_0101[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[6]) idcv_ary_0110[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[6]) idcv_ary_0110[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[7]) idcv_ary_0111[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[7]) idcv_ary_0111[{wr_index_d1[6:2]}] = din_d1;
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`else
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if (bit_wen_d1[4])
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idcv_ary[{wr_index_d1[6:2],2'b01,2'b00}] = din_d1;
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if (bit_wen_d1[5])
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idcv_ary[{wr_index_d1[6:2],2'b01,2'b01}] = din_d1;
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if (bit_wen_d1[6])
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idcv_ary[{wr_index_d1[6:2],2'b01,2'b10}] = din_d1;
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if (bit_wen_d1[7])
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idcv_ary[{wr_index_d1[6:2],2'b01,2'b11}] = din_d1;
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`endif
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// line 2 (5:4=10)
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// line 2 (5:4=10)
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`ifdef FPGA_SYN_IDCT
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if (bit_wen_d1[8]) idcv_ary_1000[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[8]) idcv_ary_1000[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[9]) idcv_ary_1001[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[9]) idcv_ary_1001[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[10]) idcv_ary_1010[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[10]) idcv_ary_1010[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[11]) idcv_ary_1011[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[11]) idcv_ary_1011[{wr_index_d1[6:2]}] = din_d1;
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`else
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if (bit_wen_d1[8])
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idcv_ary[{wr_index_d1[6:2],2'b10,2'b00}] = din_d1;
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if (bit_wen_d1[9])
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idcv_ary[{wr_index_d1[6:2],2'b10,2'b01}] = din_d1;
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if (bit_wen_d1[10])
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idcv_ary[{wr_index_d1[6:2],2'b10,2'b10}] = din_d1;
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if (bit_wen_d1[11])
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idcv_ary[{wr_index_d1[6:2],2'b10,2'b11}] = din_d1;
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`endif
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// line 3 (5:4=11)
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// line 3 (5:4=11)
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`ifdef FPGA_SYN_IDCT
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if (bit_wen_d1[12]) idcv_ary_1100[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[12]) idcv_ary_1100[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[13]) idcv_ary_1101[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[13]) idcv_ary_1101[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[14]) idcv_ary_1110[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[14]) idcv_ary_1110[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[15]) idcv_ary_1111[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[15]) idcv_ary_1111[{wr_index_d1[6:2]}] = din_d1;
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`else
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if (bit_wen_d1[12])
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idcv_ary[{wr_index_d1[6:2],2'b11,2'b00}] = din_d1;
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if (bit_wen_d1[13])
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idcv_ary[{wr_index_d1[6:2],2'b11,2'b01}] = din_d1;
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if (bit_wen_d1[14])
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idcv_ary[{wr_index_d1[6:2],2'b11,2'b10}] = din_d1;
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if (bit_wen_d1[15])
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idcv_ary[{wr_index_d1[6:2],2'b11,2'b11}] = din_d1;
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`endif
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end
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end
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end // always @ (...
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end // always @ (...
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// synopsys translate_off
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// synopsys translate_off
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// Monitors, shadow logic and other stuff not directly related to
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// Monitors, shadow logic and other stuff not directly related to
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// memory functionality
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// memory functionality
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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`ifdef INNO_MUXEX
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`else
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// Address monitor
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// Address monitor
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always @ (/*AUTOSENSE*/rd_index_d1 or rdreq_d1 or wr_index_d1
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always @ (/*AUTOSENSE*/rd_index_d1 or rdreq_d1 or wr_index_d1
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or wrreq_d1)
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or wrreq_d1)
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begin
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begin
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if (rdreq_d1 && (rd_index_d1 == 7'bX))
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if (rdreq_d1 && (rd_index_d1 == 7'bX))
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begin
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begin
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// 0in <fire -message "FATAL ERROR: bw_r_rf16x32 read address X"
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// 0in <fire -message "FATAL ERROR: bw_r_rf16x32 read address X"
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`ifdef DEFINE_0IN
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`else
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//$display("RFRDADDR", "Error: bw_r_rf16x32 read address is %b\n", rd_index_d1);
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//$error("RFRDADDR", "Error: bw_r_rf16x32 read address is %b\n", rd_index_d1);
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`endif
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end
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end
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else if (wrreq_d1 && (wr_index_d1 == 5'bX))
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else if (wrreq_d1 && (wr_index_d1 == 5'bX))
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begin
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begin
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// 0in <fire -message "FATAL ERROR: bw_r_rf16x32 write address X"
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// 0in <fire -message "FATAL ERROR: bw_r_rf16x32 write address X"
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`ifdef DEFINE_0IN
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`else
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//$display("RFWRADDR", "Error: bw_r_rf16x32 write address is %b\n", wr_index_d1);
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//$error("RFWRADDR", "Error: bw_r_rf16x32 write address is %b\n", wr_index_d1);
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`endif
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end
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end
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end // always @ (...
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end // always @ (...
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// !`ifdef INNO_MUXEX
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`endif // !`ifdef INNO_MUXEX
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//reg [127:0] w0;
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//reg [127:0] w0;
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//reg [127:0] w1;
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//reg [127:0] w1;
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//reg [127:0] w2;
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//reg [127:0] w2;
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//reg [127:0] w3;
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//reg [127:0] w3;
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//integer i;
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//integer i;
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//
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//
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// always @(idcv_ary) begin
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// always @(idcv_ary) begin
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// for (i=0;i<128; i=i+1) begin
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// for (i=0;i<128; i=i+1) begin
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// w0[i] = idcv_ary[4*i];
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// w0[i] = idcv_ary[4*i];
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// w1[i] = idcv_ary[4*i+1];
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// w1[i] = idcv_ary[4*i+1];
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// w2[i] = idcv_ary[4*i+2];
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// w2[i] = idcv_ary[4*i+2];
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// w3[i] = idcv_ary[4*i+3];
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// w3[i] = idcv_ary[4*i+3];
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// end
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// end
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// end
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// end
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//
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//
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// reg [511:0] icv_ary;
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// reg [511:0] icv_ary;
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//
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//
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// always @ (idcv_ary)
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// always @ (idcv_ary)
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// icv_ary = idcv_ary;
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// icv_ary = idcv_ary;
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// synopsys translate_on
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// synopsys translate_on
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endmodule // bw_r_rf16x32
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endmodule // bw_r_rf16x32
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