// ========== Copyright Header Begin ==========================================
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// ========== Copyright Header Begin ==========================================
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//
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//
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// OpenSPARC T1 Processor File: bw_r_scm.v
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// OpenSPARC T1 Processor File: bw_r_scm.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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//
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// The above named program is free software; you can redistribute it and/or
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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// License version 2 as published by the Free Software Foundation.
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//
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//
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// The above named program is distributed in the hope that it will be
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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// General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/*
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/*
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// Description: Store Buffer of Load/Store Unit (CAM Side)
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// Description: Store Buffer of Load/Store Unit (CAM Side)
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// - Physically divided into CAM and DATA RAMs.
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// - Physically divided into CAM and DATA RAMs.
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// - CAM RAM has a single cam port and a single
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// - CAM RAM has a single cam port and a single
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// port for read/writes. The cam port is for loads,
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// port for read/writes. The cam port is for loads,
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// write for stores, read for test/diagnostic purposes.
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// write for stores, read for test/diagnostic purposes.
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// rd or write can be simultaneous with cam. can rd and cam
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// rd or write can be simultaneous with cam. can rd and cam
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// a single entry simultaneously. cannot write and cam
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// a single entry simultaneously. cannot write and cam
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// the same entry.
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// the same entry.
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// - DATA RAM read occurs for a load raw match in the
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// - DATA RAM read occurs for a load raw match in the
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// stb CAM RAM. DATA RAM write occurs a store. Both
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// stb CAM RAM. DATA RAM write occurs a store. Both
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// actions are architecturally guaranteed to be
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// actions are architecturally guaranteed to be
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// mutex.
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// mutex.
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// - Write occurs simultaneously to both arrays.
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// - Write occurs simultaneously to both arrays.
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// - Reads are not necessarily simultaneous and are
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// - Reads are not necessarily simultaneous and are
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// controlled by individual read signals.
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// controlled by individual read signals.
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// - Certain bits are maintained outside the array
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// - Certain bits are maintained outside the array
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// in the stb's control section, such as the valid
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// in the stb's control section, such as the valid
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// bits.
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// bits.
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//
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//
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*/
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*/
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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// Local header file includes / local defines
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// Local header file includes / local defines
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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//FPGA_SYN enables all FPGA related modifications
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//FPGA_SYN enables all FPGA related modifications
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`ifdef FPGA_SYN
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`define FPGA_SYN_SCM
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`endif
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module bw_r_scm (/*AUTOARG*/
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module bw_r_scm (/*AUTOARG*/
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// Outputs
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// Outputs
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stb_rdata_ramc, stb_ld_full_raw, stb_ld_partial_raw,
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stb_rdata_ramc, stb_ld_full_raw, stb_ld_partial_raw,
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stb_cam_hit_ptr, stb_cam_hit, stb_cam_mhit,
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stb_cam_hit_ptr, stb_cam_hit, stb_cam_mhit,
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// Inputs
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// Inputs
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stb_cam_data, stb_alt_wr_data, stb_camwr_data, stb_alt_wsel,
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stb_cam_data, stb_alt_wr_data, stb_camwr_data, stb_alt_wsel,
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stb_cam_vld, stb_cam_cm_tid, stb_cam_sqsh_msk, stb_cam_rw_ptr,
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stb_cam_vld, stb_cam_cm_tid, stb_cam_sqsh_msk, stb_cam_rw_ptr,
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stb_cam_wptr_vld, stb_cam_rptr_vld, stb_cam_rw_tid,
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stb_cam_wptr_vld, stb_cam_rptr_vld, stb_cam_rw_tid,
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stb_quad_ld_cam, rclk, rst_tri_en
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stb_quad_ld_cam, rclk, rst_tri_en
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) ;
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) ;
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parameter NUMENTRIES = 32 ; // number of entries in stb
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parameter NUMENTRIES = 32 ; // number of entries in stb
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input [44:15] stb_cam_data ; // data for compare; disjoint msb
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input [44:15] stb_cam_data ; // data for compare; disjoint msb
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input [44:15] stb_alt_wr_data ; // data for compare; disjoint msb
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input [44:15] stb_alt_wr_data ; // data for compare; disjoint msb
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input [14:0] stb_camwr_data ; // data for compare/write; common lsb
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input [14:0] stb_camwr_data ; // data for compare/write; common lsb
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input stb_alt_wsel ;
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input stb_alt_wsel ;
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input stb_cam_vld ; // cam is required.
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input stb_cam_vld ; // cam is required.
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input [1:0] stb_cam_cm_tid ; // thread id for cam operation.
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input [1:0] stb_cam_cm_tid ; // thread id for cam operation.
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input [7:0] stb_cam_sqsh_msk; // mask for squashing cam results.
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input [7:0] stb_cam_sqsh_msk; // mask for squashing cam results.
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input [2:0] stb_cam_rw_ptr ; // wr pointer for single port.
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input [2:0] stb_cam_rw_ptr ; // wr pointer for single port.
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input stb_cam_wptr_vld ;// write pointer vld
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input stb_cam_wptr_vld ;// write pointer vld
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input stb_cam_rptr_vld ;// write pointer vld
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input stb_cam_rptr_vld ;// write pointer vld
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input [1:0] stb_cam_rw_tid ; // thread id for rw.
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input [1:0] stb_cam_rw_tid ; // thread id for rw.
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input stb_quad_ld_cam ; // quad-ld cam.
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input stb_quad_ld_cam ; // quad-ld cam.
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input rclk ; // clock
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input rclk ; // clock
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//input scan_ena ; // no longer required !
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//input scan_ena ; // no longer required !
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//input [7:0] adj ;
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//input [7:0] adj ;
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input rst_tri_en ;
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input rst_tri_en ;
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output [44:0] stb_rdata_ramc ; // rd data from CAM RAM.
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output [44:0] stb_rdata_ramc ; // rd data from CAM RAM.
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// raw output is muxed on a thread basis.
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// raw output is muxed on a thread basis.
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output [7:0] stb_ld_full_raw ; // ld with full raw.
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output [7:0] stb_ld_full_raw ; // ld with full raw.
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output [7:0] stb_ld_partial_raw ; // ld with partial raw.
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output [7:0] stb_ld_partial_raw ; // ld with partial raw.
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output [2:0] stb_cam_hit_ptr ;
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output [2:0] stb_cam_hit_ptr ;
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output stb_cam_hit ; // any hit in stb
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output stb_cam_hit ; // any hit in stb
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output stb_cam_mhit ; // multiple hits in stb
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output stb_cam_mhit ; // multiple hits in stb
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/*UTOREG*/
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/*UTOREG*/
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// Beginning of automatic regs (for this module's undeclared outputs)
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// Beginning of automatic regs (for this module's undeclared outputs)
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// End of automatics
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// End of automatics
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reg [44:0] stb_rdata_ramc ;
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reg [44:0] stb_rdata_ramc ;
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reg [31:0] rw_wdline ;
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reg [31:0] rw_wdline ;
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reg [44:0] stb_ramc [NUMENTRIES-1:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */;
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reg [44:0] stb_ramc [NUMENTRIES-1:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */;
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reg [44:0] ramc_entry ;
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reg [44:0] ramc_entry ;
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reg [36:0] cam_tag ;
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reg [36:0] cam_tag ;
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reg [31:0] ptag_hit ;
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reg [31:0] ptag_hit ;
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reg [7:0] cam_bmask ;
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reg [7:0] cam_bmask ;
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reg [31:0] byte_match ;
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reg [31:0] byte_match ;
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reg [31:0] byte_overlap ;
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reg [31:0] byte_overlap ;
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reg [31:0] ld_full_raw ;
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reg [31:0] ld_full_raw ;
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reg [31:0] ld_partial_raw ;
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reg [31:0] ld_partial_raw ;
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reg [44:15] alt_wr_data ;
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reg [44:15] alt_wr_data ;
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reg [44:15] pipe_wr_data ;
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reg [44:15] pipe_wr_data ;
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reg [14:0] camwr_data ;
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reg [14:0] camwr_data ;
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reg wptr_vld ;
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reg wptr_vld ;
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reg rptr_vld_tmp ;
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reg rptr_vld_tmp ;
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reg [1:0] cam_tid ;
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reg [1:0] cam_tid ;
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reg [1:0] cam_vld ;
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reg [1:0] cam_vld ;
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reg alt_wsel ;
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reg alt_wsel ;
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wire rptr_vld ;
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wire rptr_vld ;
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wire ldq ;
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wire ldq ;
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wire [7:0] sqsh_msk ;
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wire [7:0] sqsh_msk ;
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wire [7:0] ld_full_raw_mx ;
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wire [7:0] ld_full_raw_mx ;
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wire [7:0] ld_partial_raw_mx ;
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wire [7:0] ld_partial_raw_mx ;
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wire [7:0] ptag_hit_mx ;
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wire [7:0] ptag_hit_mx ;
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wire [7:0] byte_overlap_mx ;
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wire [7:0] byte_overlap_mx ;
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wire [7:0] byte_match_mx ;
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wire [7:0] byte_match_mx ;
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wire [7:0] cam_hit ;
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wire [7:0] cam_hit ;
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wire [44:0] wdata_ramc ;
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wire [44:0] wdata_ramc ;
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wire [44:0] cam_data ;
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wire [44:0] cam_data ;
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wire [44:15] wr_data ;
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wire [44:15] wr_data ;
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`ifdef FPGA_SYN_SCM
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reg [4:0] stb_addr;
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reg [4:0] stb_addr;
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`endif
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integer i,j,k,l ;
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integer i,j,k,l ;
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wire scan_ena ;
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wire scan_ena ;
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assign scan_ena = 1'b0 ;
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assign scan_ena = 1'b0 ;
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//=========================================================================================
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//=========================================================================================
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// generate wordlines
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// generate wordlines
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//=========================================================================================
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//=========================================================================================
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assign sqsh_msk[7:0] = stb_cam_sqsh_msk[7:0];
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assign sqsh_msk[7:0] = stb_cam_sqsh_msk[7:0];
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// cam_vld and cam_tid_tmp are set-up a phase earlier.
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// cam_vld and cam_tid_tmp are set-up a phase earlier.
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// Comment out - Now setup to posedge.
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// Comment out - Now setup to posedge.
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/*always @(negedge clk)
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/*always @(negedge clk)
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begin
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begin
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cam_tid_tmp[1:0] <= stb_cam_cm_tid[1:0] ;
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cam_tid_tmp[1:0] <= stb_cam_cm_tid[1:0] ;
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cam_vld_tmp <= stb_cam_vld ;
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cam_vld_tmp <= stb_cam_vld ;
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end */
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end */
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`ifdef FPGA_SYN_SCM
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`else
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// Wordlines need to be generated locally
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always @ (posedge rclk)
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begin
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for (i=0;i<32;i=i+1)
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begin
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if ({stb_cam_rw_tid[1:0],stb_cam_rw_ptr[2:0]} == i)
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rw_wdline[i] <= 1'b1;
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else
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rw_wdline[i] <= 1'b0;
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end
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end
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`endif
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always @(posedge rclk)
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always @(posedge rclk)
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begin
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begin
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pipe_wr_data[44:15] <= stb_cam_data[44:15];
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pipe_wr_data[44:15] <= stb_cam_data[44:15];
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alt_wr_data[44:15] <= stb_alt_wr_data[44:15];
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alt_wr_data[44:15] <= stb_alt_wr_data[44:15];
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camwr_data[14:0] <= stb_camwr_data[14:0];
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camwr_data[14:0] <= stb_camwr_data[14:0];
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wptr_vld <= stb_cam_wptr_vld ;
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wptr_vld <= stb_cam_wptr_vld ;
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rptr_vld_tmp <= stb_cam_rptr_vld ;
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rptr_vld_tmp <= stb_cam_rptr_vld ;
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cam_tid[1:0] <= stb_cam_cm_tid[1:0] ;
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cam_tid[1:0] <= stb_cam_cm_tid[1:0] ;
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//cam_tid[1:0] <= cam_tid_tmp[1:0] ;
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//cam_tid[1:0] <= cam_tid_tmp[1:0] ;
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//ldq <= stb_quad_ld_cam ; Bug 2870
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//ldq <= stb_quad_ld_cam ; Bug 2870
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alt_wsel <= stb_alt_wsel ;
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alt_wsel <= stb_alt_wsel ;
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`ifdef FPGA_SYN_SCM
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stb_addr <= {stb_cam_rw_tid[1:0],stb_cam_rw_ptr[2:0]};
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stb_addr <= {stb_cam_rw_tid[1:0],stb_cam_rw_ptr[2:0]};
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`endif
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end
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end
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assign ldq = stb_quad_ld_cam ;
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assign ldq = stb_quad_ld_cam ;
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assign rptr_vld = rptr_vld_tmp | rst_tri_en ;
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assign rptr_vld = rptr_vld_tmp | rst_tri_en ;
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//=========================================================================================
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//=========================================================================================
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// write or read to/from memory
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// write or read to/from memory
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//=========================================================================================
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//=========================================================================================
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// For blk-st, select out-of-pipe.
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// For blk-st, select out-of-pipe.
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assign wr_data[44:15] = alt_wsel ?
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assign wr_data[44:15] = alt_wsel ?
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alt_wr_data[44:15] : pipe_wr_data[44:15] ;
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alt_wr_data[44:15] : pipe_wr_data[44:15] ;
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assign wdata_ramc[44:0] = {wr_data[44:15],camwr_data[14:0]};
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assign wdata_ramc[44:0] = {wr_data[44:15],camwr_data[14:0]};
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// Write
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// Write
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always @ (negedge rclk)
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always @ (negedge rclk)
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begin
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begin
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`ifdef FPGA_SYN_SCM
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if(wptr_vld) begin
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if(wptr_vld) begin
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if(~rst_tri_en) begin
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if(~rst_tri_en) begin
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stb_ramc[stb_addr] <= wdata_ramc[44:0];
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stb_ramc[stb_addr] <= wdata_ramc[44:0];
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stb_rdata_ramc[44:0] <= wdata_ramc[44:0];
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stb_rdata_ramc[44:0] <= wdata_ramc[44:0];
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end else begin
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end else begin
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stb_rdata_ramc[44:0] <= stb_ramc[stb_addr];
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stb_rdata_ramc[44:0] <= stb_ramc[stb_addr];
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end
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end
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end
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end
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`else
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for (j=0;j<NUMENTRIES;j=j+1)
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begin
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if (rw_wdline[j] & wptr_vld)
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begin
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if (~rst_tri_en)
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begin
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stb_ramc[j] <= wdata_ramc[44:0];
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// write data is write-thru
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stb_rdata_ramc[44:0] <= wdata_ramc[44:0];
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end
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else
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begin
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// INNO - default rd if wr squashed by scan_ena.
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stb_rdata_ramc[44:0] <= stb_ramc[j];
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end
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end
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end
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`endif
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// Read
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// Read
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`ifdef FPGA_SYN_SCM
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if(rptr_vld & ~scan_ena) begin
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if(rptr_vld & ~scan_ena) begin
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if (rptr_vld & wptr_vld & ~rst_tri_en) begin
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if (rptr_vld & wptr_vld & ~rst_tri_en) begin
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stb_rdata_ramc[44:0] <= wdata_ramc[44:0];
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stb_rdata_ramc[44:0] <= wdata_ramc[44:0];
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end
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end
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else begin
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else begin
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stb_rdata_ramc[44:0] <= stb_ramc[stb_addr];
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stb_rdata_ramc[44:0] <= stb_ramc[stb_addr];
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end
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end
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end
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end
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`else
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for (k=0;k<NUMENTRIES;k=k+1)
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begin
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if (rw_wdline[k] & rptr_vld & ~scan_ena)
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begin
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if (rptr_vld & wptr_vld & ~rst_tri_en) // INNO - write-thru
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stb_rdata_ramc[44:0] <= wdata_ramc[44:0];
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else
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stb_rdata_ramc[44:0] <= stb_ramc[k];
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end
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end
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`endif
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end
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end
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//=========================================================================================
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//=========================================================================================
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// CAM contents of CAM RAM
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// CAM contents of CAM RAM
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//=========================================================================================
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//=========================================================================================
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// - Generate full/partial raw for incoming load.
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// - Generate full/partial raw for incoming load.
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// - Output signals need to be qualified with per entry
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// - Output signals need to be qualified with per entry
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// vlds before causing any subsequent event, the read of
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// vlds before causing any subsequent event, the read of
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// the DATA RAM specifically.
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// the DATA RAM specifically.
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// - full_raw & vld will cause rd of DATA RAM.
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// - full_raw & vld will cause rd of DATA RAM.
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// - partial_raw & vld will cause ld to follow corresponding
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// - partial_raw & vld will cause ld to follow corresponding
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// st on way out to xbar.
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// st on way out to xbar.
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// - logic to generate partial and full raws may be done outside
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// - logic to generate partial and full raws may be done outside
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// but that would require an additional signal per entry to
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// but that would require an additional signal per entry to
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// be output.
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// be output.
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// Mapping of cam/write data
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// Mapping of cam/write data
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//
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//
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// | 40-3=37b(pa) | 1b(stquad) | 8b(bytemask) | <- use
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// | 40-3=37b(pa) | 1b(stquad) | 8b(bytemask) | <- use
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// | 45:9 | 8 | 7:0 | <- input port
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// | 45:9 | 8 | 7:0 | <- input port
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// **^ stquad rm'ed
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// **^ stquad rm'ed
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assign cam_data[44:0] = {stb_cam_data[44:15],stb_camwr_data[14:0]};
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assign cam_data[44:0] = {stb_cam_data[44:15],stb_camwr_data[14:0]};
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always @ (posedge rclk)
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always @ (posedge rclk)
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begin
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begin
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for (l=0;l<NUMENTRIES;l=l+1)
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for (l=0;l<NUMENTRIES;l=l+1)
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begin
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begin
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ramc_entry[44:0] = stb_ramc[l] ;
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ramc_entry[44:0] = stb_ramc[l] ;
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cam_tag[36:0] = ramc_entry[44:8] ;
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cam_tag[36:0] = ramc_entry[44:8] ;
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cam_bmask[7:0] = ramc_entry[7:0] ;
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cam_bmask[7:0] = ramc_entry[7:0] ;
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//stq = ramc_entry[8] ; // additional bit -stq
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//stq = ramc_entry[8] ; // additional bit -stq
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// Prior to adding stb_quad_ld_cam port.
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// Prior to adding stb_quad_ld_cam port.
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/*ptag_hit[l] =
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/*ptag_hit[l] =
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((cam_tag[36:1] == cam_data[44:9]) &
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((cam_tag[36:1] == cam_data[44:9]) &
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(((cam_tag[0] == cam_data[8]) & ~stq) | stq)) & stcam_vld_tmp & ~scan_ena ;*/
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(((cam_tag[0] == cam_data[8]) & ~stq) | stq)) & stcam_vld_tmp & ~scan_ena ;*/
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// Modification.
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// Modification.
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// * remove ramc_entry[8]. Or keep it but it won't be used.
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// * remove ramc_entry[8]. Or keep it but it won't be used.
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// * Instead we'll control this from outside.
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// * Instead we'll control this from outside.
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ptag_hit[l] =
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ptag_hit[l] =
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(cam_tag[36:1] == cam_data[44:9]) &
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(cam_tag[36:1] == cam_data[44:9]) &
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(((cam_tag[0] == cam_data[8]) & ~ldq) | ldq) & stb_cam_vld & ~scan_ena ;
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(((cam_tag[0] == cam_data[8]) & ~ldq) | ldq) & stb_cam_vld & ~scan_ena ;
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byte_match[l] = |(cam_bmask[7:0] & cam_data[7:0]) & stb_cam_vld & ~scan_ena ;
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byte_match[l] = |(cam_bmask[7:0] & cam_data[7:0]) & stb_cam_vld & ~scan_ena ;
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// Simplification :
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// Simplification :
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byte_overlap[l] = |(~cam_bmask[7:0] & cam_data[7:0]) & stb_cam_vld & ~scan_ena ;
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byte_overlap[l] = |(~cam_bmask[7:0] & cam_data[7:0]) & stb_cam_vld & ~scan_ena ;
|
|
|
end
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end
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end
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end
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|
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// Mux the raw signals down to 8b quantities. Squash mask comes mid-way thru cycle.
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// Mux the raw signals down to 8b quantities. Squash mask comes mid-way thru cycle.
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|
|
|
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assign byte_overlap_mx[7:0] =
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assign byte_overlap_mx[7:0] =
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(cam_tid[1:0] == 2'b00) ? byte_overlap[7:0] :
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(cam_tid[1:0] == 2'b00) ? byte_overlap[7:0] :
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(cam_tid[1:0] == 2'b01) ? byte_overlap[15:8] :
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(cam_tid[1:0] == 2'b01) ? byte_overlap[15:8] :
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(cam_tid[1:0] == 2'b10) ? byte_overlap[23:16] :
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(cam_tid[1:0] == 2'b10) ? byte_overlap[23:16] :
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(cam_tid[1:0] == 2'b11) ? byte_overlap[31:24] : 8'bxxxx_xxxx ;
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(cam_tid[1:0] == 2'b11) ? byte_overlap[31:24] : 8'bxxxx_xxxx ;
|
|
|
assign byte_match_mx[7:0] =
|
assign byte_match_mx[7:0] =
|
(cam_tid[1:0] == 2'b00) ? byte_match[7:0] :
|
(cam_tid[1:0] == 2'b00) ? byte_match[7:0] :
|
(cam_tid[1:0] == 2'b01) ? byte_match[15:8] :
|
(cam_tid[1:0] == 2'b01) ? byte_match[15:8] :
|
(cam_tid[1:0] == 2'b10) ? byte_match[23:16] :
|
(cam_tid[1:0] == 2'b10) ? byte_match[23:16] :
|
(cam_tid[1:0] == 2'b11) ? byte_match[31:24] : 8'bxxxx_xxxx ;
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(cam_tid[1:0] == 2'b11) ? byte_match[31:24] : 8'bxxxx_xxxx ;
|
|
|
assign ptag_hit_mx[7:0] =
|
assign ptag_hit_mx[7:0] =
|
(cam_tid[1:0] == 2'b00) ? ptag_hit[7:0] :
|
(cam_tid[1:0] == 2'b00) ? ptag_hit[7:0] :
|
(cam_tid[1:0] == 2'b01) ? ptag_hit[15:8] :
|
(cam_tid[1:0] == 2'b01) ? ptag_hit[15:8] :
|
(cam_tid[1:0] == 2'b10) ? ptag_hit[23:16] :
|
(cam_tid[1:0] == 2'b10) ? ptag_hit[23:16] :
|
(cam_tid[1:0] == 2'b11) ? ptag_hit[31:24] : 8'bxxxx_xxxx ;
|
(cam_tid[1:0] == 2'b11) ? ptag_hit[31:24] : 8'bxxxx_xxxx ;
|
|
|
assign stb_ld_full_raw[7:0] =
|
assign stb_ld_full_raw[7:0] =
|
ptag_hit_mx[7:0] & byte_match_mx[7:0] & ~byte_overlap_mx[7:0] & ~sqsh_msk[7:0] ;
|
ptag_hit_mx[7:0] & byte_match_mx[7:0] & ~byte_overlap_mx[7:0] & ~sqsh_msk[7:0] ;
|
assign stb_ld_partial_raw[7:0] =
|
assign stb_ld_partial_raw[7:0] =
|
ptag_hit_mx[7:0] & byte_match_mx[7:0] & byte_overlap_mx[7:0] & ~sqsh_msk[7:0] ;
|
ptag_hit_mx[7:0] & byte_match_mx[7:0] & byte_overlap_mx[7:0] & ~sqsh_msk[7:0] ;
|
|
|
assign cam_hit[7:0] =
|
assign cam_hit[7:0] =
|
ptag_hit_mx[7:0] & byte_match_mx[7:0] & ~sqsh_msk[7:0] ;
|
ptag_hit_mx[7:0] & byte_match_mx[7:0] & ~sqsh_msk[7:0] ;
|
assign stb_cam_hit = |(cam_hit[7:0]);
|
assign stb_cam_hit = |(cam_hit[7:0]);
|
|
|
// The stb data is meant to be read for single hit full raw case. It may actually be read
|
// The stb data is meant to be read for single hit full raw case. It may actually be read
|
// for full raw, partial raw or multiple hit case but the read output will be ignored for
|
// for full raw, partial raw or multiple hit case but the read output will be ignored for
|
// partial and multiple hit case. Multiple hits will not cause a hazard as the ptr is first
|
// partial and multiple hit case. Multiple hits will not cause a hazard as the ptr is first
|
// encoded and then decoded to form the wdline for the stb-data
|
// encoded and then decoded to form the wdline for the stb-data
|
// Use cam_hit result to void false hits.
|
// Use cam_hit result to void false hits.
|
assign stb_cam_hit_ptr[0] = cam_hit[1] | cam_hit[3] | cam_hit[5] | cam_hit[7] ;
|
assign stb_cam_hit_ptr[0] = cam_hit[1] | cam_hit[3] | cam_hit[5] | cam_hit[7] ;
|
assign stb_cam_hit_ptr[1] = cam_hit[2] | cam_hit[3] | cam_hit[6] | cam_hit[7] ;
|
assign stb_cam_hit_ptr[1] = cam_hit[2] | cam_hit[3] | cam_hit[6] | cam_hit[7] ;
|
assign stb_cam_hit_ptr[2] = cam_hit[4] | cam_hit[5] | cam_hit[6] | cam_hit[7] ;
|
assign stb_cam_hit_ptr[2] = cam_hit[4] | cam_hit[5] | cam_hit[6] | cam_hit[7] ;
|
|
|
//Generating multiple hits
|
//Generating multiple hits
|
assign stb_cam_mhit = (cam_hit[0] & cam_hit[1]) | (cam_hit[2] & cam_hit[3]) |
|
assign stb_cam_mhit = (cam_hit[0] & cam_hit[1]) | (cam_hit[2] & cam_hit[3]) |
|
(cam_hit[4] & cam_hit[5]) | (cam_hit[6] & cam_hit[7]) |
|
(cam_hit[4] & cam_hit[5]) | (cam_hit[6] & cam_hit[7]) |
|
((cam_hit[0] | cam_hit[1]) & (cam_hit[2] | cam_hit[3])) |
|
((cam_hit[0] | cam_hit[1]) & (cam_hit[2] | cam_hit[3])) |
|
((cam_hit[4] | cam_hit[5]) & (cam_hit[6] | cam_hit[7])) |
|
((cam_hit[4] | cam_hit[5]) & (cam_hit[6] | cam_hit[7])) |
|
((|cam_hit[3:0]) & (|cam_hit[7:4]));
|
((|cam_hit[3:0]) & (|cam_hit[7:4]));
|
|
|
//--------------------------------------------------------------
|
//--------------------------------------------------------------
|
// Error Checking.
|
// Error Checking.
|
//--------------------------------------------------------------
|
//--------------------------------------------------------------
|
|
|
// 1. simultaneous rd/wr on single port - terminate
|
// 1. simultaneous rd/wr on single port - terminate
|
// 2. simultaneous cam and wr - terminate
|
// 2. simultaneous cam and wr - terminate
|
// * PUT OUTSIDE OF SRAM RTL, AS RST NOT AVAILABLE. *
|
// * PUT OUTSIDE OF SRAM RTL, AS RST NOT AVAILABLE. *
|
|
|
endmodule
|
endmodule
|
|
|
