// ========== Copyright Header Begin ==========================================
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// ========== Copyright Header Begin ==========================================
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//
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//
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// OpenSPARC T1 Processor File: cluster_header.v
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// OpenSPARC T1 Processor File: cluster_header.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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//
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// The above named program is free software; you can redistribute it and/or
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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// License version 2 as published by the Free Software Foundation.
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//
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//
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// The above named program is distributed in the hope that it will be
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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// General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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// The cluster header is instatiated as a hard macro.
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// The cluster header is instatiated as a hard macro.
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// This model is for simulation only.
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// This model is for simulation only.
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/*
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`include "sys.h"
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/* ========== Copyright Header Begin ==========================================
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*
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* OpenSPARC T1 Processor File: sys.h
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* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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*
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* The above named program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* The above named program is distributed in the hope that it will be
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* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public
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* License along with this work; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* ========== Copyright Header End ============================================
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*/
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// -*- verilog -*-
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////////////////////////////////////////////////////////////////////////
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/*
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//
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// Description: Global header file that contain definitions that
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// are common/shared at the systme level
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*/
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////////////////////////////////////////////////////////////////////////
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//
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// Setting the time scale
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// If the timescale changes, JP_TIMESCALE may also have to change.
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`timescale 1ps/1ps
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//
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// JBUS clock
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// =========
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//
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// Afara Link Defines
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// ==================
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// Reliable Link
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// Afara Link Objects
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// Afara Link Object Format - Reliable Link
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// Afara Link Object Format - Congestion
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// Afara Link Object Format - Acknowledge
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// Afara Link Object Format - Request
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// Afara Link Object Format - Message
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// Acknowledge Types
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// Request Types
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// Afara Link Frame
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//
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// UCB Packet Type
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// ===============
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//
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//
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// UCB Data Packet Format
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// ======================
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//
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// Size encoding for the UCB_SIZE_HI/LO field
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// 000 - byte
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// 001 - half-word
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// 010 - word
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// 011 - double-word
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// 111 - quad-word
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//
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// UCB Interrupt Packet Format
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// ===========================
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//
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//`define UCB_THR_HI 9 // (6) cpu/thread ID shared with
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//`define UCB_THR_LO 4 data packet format
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//`define UCB_PKT_HI 3 // (4) packet type shared with
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//`define UCB_PKT_LO 0 // data packet format
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//
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// FCRAM Bus Widths
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// ================
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//
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//
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// ENET clock periods
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// ==================
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//
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//
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// JBus Bridge defines
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// =================
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//
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//
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// PCI Device Address Configuration
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// ================================
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//
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module cluster_header (/*AUTOARG*/
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module cluster_header (/*AUTOARG*/
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// Outputs
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// Outputs
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dbginit_l, cluster_grst_l, rclk, so,
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dbginit_l, cluster_grst_l, rclk, so,
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// Inputs
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// Inputs
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gclk, cluster_cken, arst_l, grst_l, adbginit_l, gdbginit_l, si,
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gclk, cluster_cken, arst_l, grst_l, adbginit_l, gdbginit_l, si,
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se
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se
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);
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);
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input gclk;
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input gclk;
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input cluster_cken;
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input cluster_cken;
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input arst_l;
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input arst_l;
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input grst_l;
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input grst_l;
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input adbginit_l;
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input adbginit_l;
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input gdbginit_l;
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input gdbginit_l;
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output dbginit_l;
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output dbginit_l;
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output cluster_grst_l;
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output cluster_grst_l;
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output rclk;
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output rclk;
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input si; // scan ports for reset flop repeaters
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input si; // scan ports for reset flop repeaters
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input se;
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input se;
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output so;
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output so;
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`ifdef FPGA_SYN
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// assign #10 rclk = gclk;
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// assign #10 rclk = gclk;
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// assign #10 dbginit_l = gdbginit_l;
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// assign #10 dbginit_l = gdbginit_l;
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// assign #10 cluster_grst_l = grst_l;
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// assign #10 cluster_grst_l = grst_l;
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// assign so = 1'b0;
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// assign so = 1'b0;
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reg dbginit_l;
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reg dbginit_l;
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reg cluster_grst_l;
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reg cluster_grst_l;
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assign #10 rclk = gclk;
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assign #10 rclk = gclk;
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always @(negedge rclk) begin
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always @(negedge rclk) begin
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dbginit_l <= gdbginit_l;
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dbginit_l <= gdbginit_l;
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cluster_grst_l <= grst_l;
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cluster_grst_l <= grst_l;
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end
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end
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`else
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wire pre_sync_enable;
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wire sync_enable;
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wire cluster_grst_l;
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wire dbginit_l;
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wire rst_sync_so;
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bw_u1_syncff_4x sync_cluster_master ( // no scan hook-up
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.so(),
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.q (pre_sync_enable),
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.ck (gclk),
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.d (cluster_cken),
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.sd(1'b0),
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.se(1'b0)
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);
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bw_u1_scanl_2x sync_cluster_slave ( // use scan lock-up latch
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.so (sync_enable),
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.ck (gclk),
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.sd (pre_sync_enable)
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);
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// NOTE! Pound delay in the below statement is meant to provide 10 ps
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// delay between gclk and rclk to allow the synchronizer for rst, dbginit,
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// and sync pulses to be modelled accurately. gclk and rclk need to have
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// at least one simulator timestep separation to allow the flop->flop
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// synchronizer to work correctly.
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assign #10 rclk = gclk & sync_enable;
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synchronizer_asr rst_repeater (
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.sync_out(cluster_grst_l),
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.so(rst_sync_so),
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.async_in(grst_l),
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.gclk(gclk),
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.rclk(rclk),
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.arst_l(arst_l),
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.si(si),
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.se(se)
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);
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synchronizer_asr dbginit_repeater (
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.sync_out(dbginit_l),
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.so(so),
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.async_in(gdbginit_l),
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.gclk(gclk),
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.rclk(rclk),
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.arst_l(adbginit_l),
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.si(rst_sync_so),
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.se(se)
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);
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`endif
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endmodule // cluster_header
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endmodule // cluster_header
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