// ========== Copyright Header Begin ==========================================
|
// ========== Copyright Header Begin ==========================================
|
//
|
//
|
// OpenSPARC T1 Processor File: cmp_sram_redhdr.v
|
// OpenSPARC T1 Processor File: cmp_sram_redhdr.v
|
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
|
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
|
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
|
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
|
//
|
//
|
// The above named program is free software; you can redistribute it and/or
|
// The above named program is free software; you can redistribute it and/or
|
// modify it under the terms of the GNU General Public
|
// modify it under the terms of the GNU General Public
|
// License version 2 as published by the Free Software Foundation.
|
// License version 2 as published by the Free Software Foundation.
|
//
|
//
|
// The above named program is distributed in the hope that it will be
|
// The above named program is distributed in the hope that it will be
|
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
|
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
// General Public License for more details.
|
// General Public License for more details.
|
//
|
//
|
// You should have received a copy of the GNU General Public
|
// You should have received a copy of the GNU General Public
|
// License along with this work; if not, write to the Free Software
|
// License along with this work; if not, write to the Free Software
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
//
|
//
|
// ========== Copyright Header End ============================================
|
// ========== Copyright Header End ============================================
|
//
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//
|
// Cluster Name: Efuse Cluster
|
// Cluster Name: Efuse Cluster
|
// Unit Name: cmp_redhdr (sram redundancy header)
|
// Unit Name: cmp_redhdr (sram redundancy header)
|
// Block Name: EFC
|
// Block Name: EFC
|
//
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//
|
// This is the header used to read and write the fuse values to the
|
// This is the header used to read and write the fuse values to the
|
// RAM blocks. It is used to drive the ICD, DCD and L2T. It is
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// RAM blocks. It is used to drive the ICD, DCD and L2T. It is
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// outside the array it is driving.
|
// outside the array it is driving.
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//
|
//
|
// Top level signal renaming:
|
// Top level signal renaming:
|
// s/ary/<your_ary_name>/g
|
// s/ary/<your_ary_name>/g
|
// s/xfuse/<your_ary_initial>fuse/g
|
// s/xfuse/<your_ary_initial>fuse/g
|
//
|
//
|
// E.g. fuse_ary_wren -> fuse_icd_wren
|
// E.g. fuse_ary_wren -> fuse_icd_wren
|
// efc_spc_xfuse_data -> efc_spc_ifuse_data, efc_sct_fuse_data
|
// efc_spc_xfuse_data -> efc_spc_ifuse_data, efc_sct_fuse_data
|
//
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//
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//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
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/*
|
`include "sys.h"
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/* ========== Copyright Header Begin ==========================================
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`include "iop.h"
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*
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|
* OpenSPARC T1 Processor File: sys.h
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|
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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|
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
|
|
*
|
|
* The above named program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public
|
|
* License version 2 as published by the Free Software Foundation.
|
|
*
|
|
* The above named program is distributed in the hope that it will be
|
|
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
* General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public
|
|
* License along with this work; if not, write to the Free Software
|
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
|
*
|
|
* ========== Copyright Header End ============================================
|
|
*/
|
|
// -*- verilog -*-
|
|
////////////////////////////////////////////////////////////////////////
|
|
/*
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|
//
|
|
// Description: Global header file that contain definitions that
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|
// are common/shared at the systme level
|
|
*/
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|
////////////////////////////////////////////////////////////////////////
|
|
//
|
|
// Setting the time scale
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// If the timescale changes, JP_TIMESCALE may also have to change.
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`timescale 1ps/1ps
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//
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// JBUS clock
|
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// =========
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//
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// Afara Link Defines
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// ==================
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// Reliable Link
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// Afara Link Objects
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// Afara Link Object Format - Reliable Link
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// Afara Link Object Format - Congestion
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// Afara Link Object Format - Acknowledge
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// Afara Link Object Format - Request
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// Afara Link Object Format - Message
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// Acknowledge Types
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// Request Types
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// Afara Link Frame
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//
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// UCB Packet Type
|
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// ===============
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//
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//
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// UCB Data Packet Format
|
|
// ======================
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//
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// Size encoding for the UCB_SIZE_HI/LO field
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// 000 - byte
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// 001 - half-word
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// 010 - word
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// 011 - double-word
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// 111 - quad-word
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//
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// UCB Interrupt Packet Format
|
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// ===========================
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//
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//`define UCB_THR_HI 9 // (6) cpu/thread ID shared with
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|
//`define UCB_THR_LO 4 data packet format
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//`define UCB_PKT_HI 3 // (4) packet type shared with
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//`define UCB_PKT_LO 0 // data packet format
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//
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// FCRAM Bus Widths
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// ================
|
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//
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//
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// ENET clock periods
|
|
// ==================
|
|
//
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//
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|
// JBus Bridge defines
|
|
// =================
|
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//
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//
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|
// PCI Device Address Configuration
|
|
// ================================
|
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//
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/*
|
|
/* ========== Copyright Header Begin ==========================================
|
|
*
|
|
* OpenSPARC T1 Processor File: iop.h
|
|
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
|
|
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
|
|
*
|
|
* The above named program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public
|
|
* License version 2 as published by the Free Software Foundation.
|
|
*
|
|
* The above named program is distributed in the hope that it will be
|
|
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
* General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public
|
|
* License along with this work; if not, write to the Free Software
|
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
|
*
|
|
* ========== Copyright Header End ============================================
|
|
*/
|
|
//-*- verilog -*-
|
|
////////////////////////////////////////////////////////////////////////
|
|
/*
|
|
//
|
|
// Description: Global header file that contain definitions that
|
|
// are common/shared at the IOP chip level
|
|
*/
|
|
////////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
// Address Map Defines
|
|
// ===================
|
|
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// CMP space
|
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// IOP space
|
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|
|
//`define ENET_ING_CSR 8'h84
|
|
//`define ENET_EGR_CMD_CSR 8'h85
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// L2 space
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// More IOP space
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//Cache Crossbar Width and Field Defines
|
|
//======================================
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//bits 133:128 are shared by different fields
|
|
//for different packet types.
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//End cache crossbar defines
|
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|
|
// Number of COS supported by EECU
|
|
|
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|
|
//
|
|
// BSC bus sizes
|
|
// =============
|
|
//
|
|
|
|
// General
|
|
|
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|
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// CTags
|
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// reinstated temporarily
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// CoS
|
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// L2$ Bank
|
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// L2$ Req
|
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// L2$ Ack
|
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// Enet Egress Command Unit
|
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// Enet Egress Packet Unit
|
|
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// This is cleaved in between Egress Datapath Ack's
|
|
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|
|
// Enet Egress Datapath
|
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|
// In-Order / Ordered Queue: EEPU
|
|
// Tag is: TLEN, SOF, EOF, QID = 15
|
|
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|
|
// Nack + Tag Info + CTag
|
|
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|
// ENET Ingress Queue Management Req
|
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// ENET Ingress Queue Management Ack
|
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|
// Enet Ingress Packet Unit
|
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// ENET Ingress Packet Unit Ack
|
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|
// In-Order / Ordered Queue: PCI
|
|
// Tag is: CTAG
|
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|
|
// PCI-X Request
|
|
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|
|
// PCI_X Acknowledge
|
|
|
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//
|
|
// BSC array sizes
|
|
//================
|
|
//
|
|
|
|
|
|
|
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|
// ECC syndrome bits per memory element
|
|
|
|
|
|
|
|
|
|
//
|
|
// BSC Port Definitions
|
|
// ====================
|
|
//
|
|
// Bits 7 to 4 of curr_port_id
|
|
|
|
|
|
|
|
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|
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|
|
// Number of ports of each type
|
|
|
|
|
|
// Bits needed to represent above
|
|
|
|
|
|
// How wide the linked list pointers are
|
|
// 60b for no payload (2CoS)
|
|
// 80b for payload (2CoS)
|
|
|
|
//`define BSC_OBJ_PTR 80
|
|
//`define BSC_HD1_HI 69
|
|
//`define BSC_HD1_LO 60
|
|
//`define BSC_TL1_HI 59
|
|
//`define BSC_TL1_LO 50
|
|
//`define BSC_CT1_HI 49
|
|
//`define BSC_CT1_LO 40
|
|
//`define BSC_HD0_HI 29
|
|
//`define BSC_HD0_LO 20
|
|
//`define BSC_TL0_HI 19
|
|
//`define BSC_TL0_LO 10
|
|
//`define BSC_CT0_HI 9
|
|
//`define BSC_CT0_LO 0
|
|
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|
// I2C STATES in DRAMctl
|
|
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|
|
//
|
|
// IOB defines
|
|
// ===========
|
|
//
|
|
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|
|
//`define IOB_INT_STAT_WIDTH 32
|
|
//`define IOB_INT_STAT_HI 31
|
|
//`define IOB_INT_STAT_LO 0
|
|
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|
|
// fixme - double check address mapping
|
|
// CREG in `IOB_INT_CSR space
|
|
|
|
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|
|
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|
|
// CREG in `IOB_MAN_CSR space
|
|
|
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// Address map for TAP access of SPARC ASI
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//
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// CIOP UCB Bus Width
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// ==================
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//
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//`define IOB_EECU_WIDTH 16 // ethernet egress command
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//`define EECU_IOB_WIDTH 16
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//`define IOB_NRAM_WIDTH 16 // NRAM (RLDRAM previously)
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//`define NRAM_IOB_WIDTH 4
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//`define IOB_ENET_ING_WIDTH 32 // ethernet ingress
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//`define ENET_ING_IOB_WIDTH 8
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//`define IOB_ENET_EGR_WIDTH 4 // ethernet egress
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//`define ENET_EGR_IOB_WIDTH 4
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//`define IOB_ENET_MAC_WIDTH 4 // ethernet MAC
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//`define ENET_MAC_IOB_WIDTH 4
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//`define IOB_BSC_WIDTH 4 // BSC
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//`define BSC_IOB_WIDTH 4
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//`define IOB_CLSP_WIDTH 4 // clk spine unit
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//`define CLSP_IOB_WIDTH 4
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//
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// CIOP UCB Buf ID Type
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// ====================
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//
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//
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// Interrupt Device ID
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// ===================
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//
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// Caution: DUMMY_DEV_ID has to be 9 bit wide
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// for fields to line up properly in the IOB.
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//
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// Soft Error related definitions
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// ==============================
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//
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//
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// CMP clock
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// =========
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//
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//
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// NRAM/IO Interface
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// =================
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//
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//
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// NRAM/ENET Interface
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// ===================
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//
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//
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// IO/FCRAM Interface
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// ==================
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//
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//
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// PCI Interface
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// ==================
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// Load/store size encodings
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// -------------------------
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// Size encoding
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// 000 - byte
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// 001 - half-word
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// 010 - word
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// 011 - double-word
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// 100 - quad
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//
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// JBI<->SCTAG Interface
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// =======================
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// Outbound Header Format
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// Inbound Header Format
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//
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// JBI->IOB Mondo Header Format
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// ============================
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//
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// JBI->IOB Mondo Bus Width/Cycle
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// ==============================
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// Cycle 1 Header[15:8]
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// Cycle 2 Header[ 7:0]
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// Cycle 3 J_AD[127:120]
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// Cycle 4 J_AD[119:112]
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// .....
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// Cycle 18 J_AD[ 7: 0]
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//FPGA_SYN enables all FPGA related modifications
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//FPGA_SYN enables all FPGA related modifications
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`ifdef FPGA_SYN
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`define FPGA_SYN_CLK
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`endif
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module cmp_sram_redhdr (/*AUTOARG*/
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module cmp_sram_redhdr (/*AUTOARG*/
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// Outputs
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// Outputs
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fuse_ary_wren, fuse_ary_rid, fuse_ary_repair_value,
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fuse_ary_wren, fuse_ary_rid, fuse_ary_repair_value,
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fuse_ary_repair_en, spc_efc_xfuse_data, scanout,
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fuse_ary_repair_en, spc_efc_xfuse_data, scanout,
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// Inputs
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// Inputs
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rclk, se, scanin, arst_l, testmode_l, efc_spc_fuse_clk1,
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rclk, se, scanin, arst_l, testmode_l, efc_spc_fuse_clk1,
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efc_spc_fuse_clk2, efc_spc_xfuse_data, efc_spc_xfuse_ashift,
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efc_spc_fuse_clk2, efc_spc_xfuse_data, efc_spc_xfuse_ashift,
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efc_spc_xfuse_dshift, ary_fuse_repair_value, ary_fuse_repair_en
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efc_spc_xfuse_dshift, ary_fuse_repair_value, ary_fuse_repair_en
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);
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);
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input rclk;
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input rclk;
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input se;
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input se;
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input scanin; // CMP clock, L1 phase
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input scanin; // CMP clock, L1 phase
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input arst_l;
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input arst_l;
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input testmode_l;
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input testmode_l;
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// eFuse controller interface
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// eFuse controller interface
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input efc_spc_fuse_clk1;
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input efc_spc_fuse_clk1;
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input efc_spc_fuse_clk2;
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input efc_spc_fuse_clk2;
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input efc_spc_xfuse_data;
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input efc_spc_xfuse_data;
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input efc_spc_xfuse_ashift; // addr shift; low during rst
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input efc_spc_xfuse_ashift; // addr shift; low during rst
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input efc_spc_xfuse_dshift; // data shift; low during rst
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input efc_spc_xfuse_dshift; // data shift; low during rst
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|
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// interface to cache redundancy logic
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// interface to cache redundancy logic
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input [7:0] ary_fuse_repair_value; //data out for redundancy register
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input [7:0] ary_fuse_repair_value; //data out for redundancy register
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input [1:0] ary_fuse_repair_en; //enable bits out
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input [1:0] ary_fuse_repair_en; //enable bits out
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// outputs
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// outputs
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// interface to icache
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// interface to icache
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output fuse_ary_wren; //redundancy reg wr enable, qualified
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output fuse_ary_wren; //redundancy reg wr enable, qualified
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output [5:0] fuse_ary_rid; //redundancy register id
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output [5:0] fuse_ary_rid; //redundancy register id
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output [7:0] fuse_ary_repair_value;//data in for redundancy register
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output [7:0] fuse_ary_repair_value;//data in for redundancy register
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output [1:0] fuse_ary_repair_en; //enable bits to turn on redundancy
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output [1:0] fuse_ary_repair_en; //enable bits to turn on redundancy
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// serial rd data to controller
|
// serial rd data to controller
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output spc_efc_xfuse_data;
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output spc_efc_xfuse_data;
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|
|
// normal scan out
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// normal scan out
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output scanout;
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output scanout;
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|
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`ifdef FPGA_SYN_CLK
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assign fuse_ary_wren = 1'b0;
|
assign fuse_ary_wren = 1'b0;
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assign fuse_ary_rid = 6'b0;
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assign fuse_ary_rid = 6'b0;
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assign fuse_ary_repair_value = 8'b0;
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assign fuse_ary_repair_value = 8'b0;
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assign fuse_ary_repair_en = 2'b0;
|
assign fuse_ary_repair_en = 2'b0;
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assign spc_efc_xfuse_data = 1'b0;
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assign spc_efc_xfuse_data = 1'b0;
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assign scanout = 1'b0;
|
assign scanout = 1'b0;
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|
`else
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|
|
// local signals
|
|
wire clk;
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|
wire int_clk1;
|
|
wire int_clk2;
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|
wire int_scanout; // !! hook up to last flop in scan chain !!
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wire int_scanin; // !! hook up to 1st flop in scan chain !!
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wire [6:0] addr_shft_nxt;
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wire [6:0] addr_shft_ff;
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|
wire addr_shft_en;
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wire wren_bit;
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wire [11:0] data_shft_nxt;
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wire [11:0] data_shft_ff;
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wire data_shft_en;
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wire dshift_dly1_ff;
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|
wire dshift_dly2_ff;
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|
wire ashift_dly1_ff;
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|
wire ashift_dly2_ff;
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|
wire wren_ff;
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wire wren_ph1;
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wire rden_ph1;
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|
|
/*AUTOWIRE*/
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|
// Beginning of automatic wires (for undeclared instantiated-module outputs)
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|
// End of automatics
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|
|
|
//
|
|
// Code Begins Here
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|
//
|
|
|
|
assign clk = rclk;
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|
|
|
// Test logic
|
|
assign int_clk1 = (~testmode_l) ? rclk : efc_spc_fuse_clk1;
|
|
assign int_clk2 = (~testmode_l) ? rclk : efc_spc_fuse_clk2;
|
|
assign int_scanout = 1'b0;
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|
|
// Need latch to avoid hold time problems
|
|
// connect int_scanout to last flop in scan chain
|
|
bw_u1_scanlg_2x so_lockup(.so (scanout),
|
|
.sd (int_scanout),
|
|
.ck (clk), .se(se));
|
|
// connect int_scanin to first flop in scan chain
|
|
bw_u1_scanlg_2x si_lockup(.so (int_scanin),
|
|
.sd (scanin),
|
|
.ck (clk), .se(se));
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|
|
|
// Shift registers
|
|
// Address
|
|
assign addr_shft_en = efc_spc_xfuse_ashift;
|
|
assign addr_shft_nxt = {addr_shft_ff[5:0], efc_spc_xfuse_data};
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|
|
dffe_s #(7) addr_shft_reg (.din (addr_shft_nxt),
|
|
.q (addr_shft_ff),
|
|
.en (addr_shft_en),
|
|
.clk (int_clk1), .se(se), .si(), .so());
|
|
|
|
assign fuse_ary_rid[5:0] = addr_shft_ff[6:1];
|
|
assign wren_bit = addr_shft_ff[0];
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|
|
|
// Data
|
|
assign data_shft_en = efc_spc_xfuse_dshift | dshift_dly1_ff | rden_ph1;
|
|
|
|
// mux2es
|
|
assign data_shft_nxt = rden_ph1
|
|
? {{3{ary_fuse_repair_en[1]}},
|
|
ary_fuse_repair_value[7:0],
|
|
ary_fuse_repair_en[0]}
|
|
: {data_shft_ff[10:0],
|
|
efc_spc_xfuse_data};
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|
|
|
// 10:9 is unused
|
|
dffe_s #(12) data_shft_reg (.din (data_shft_nxt),
|
|
.q (data_shft_ff),
|
|
.en (data_shft_en),
|
|
.clk (int_clk1), .se(se), .si(), .so());
|
|
|
|
assign fuse_ary_repair_value = data_shft_ff[8:1];
|
|
assign fuse_ary_repair_en = {(data_shft_ff[11] & wren_ff),
|
|
(data_shft_ff[0] & wren_ff)};
|
|
|
|
// Control
|
|
dff_s #(1) ashift_dly1_reg (.din (efc_spc_xfuse_ashift),
|
|
.q (ashift_dly1_ff),
|
|
.clk (int_clk1), .se(se), .si(), .so());
|
|
dff_s #(1) ashift_dly2_reg (.din (ashift_dly1_ff),
|
|
.q (ashift_dly2_ff),
|
|
.clk (int_clk1), .se(se), .si(), .so());
|
|
|
|
dffrl_async #(1) dshift_dly1_reg (.din (efc_spc_xfuse_dshift),
|
|
.q (dshift_dly1_ff),
|
|
.rst_l (arst_l),
|
|
.clk (int_clk1), .se(se), .si(), .so());
|
|
dffrl_async #(1) dshift_dly2_reg (.din (dshift_dly1_ff),
|
|
.q (dshift_dly2_ff),
|
|
.rst_l (arst_l),
|
|
.clk (int_clk1), .se(se), .si(), .so());
|
|
|
|
assign wren_ph1 = dshift_dly2_ff && ~dshift_dly1_ff && wren_bit;
|
|
assign rden_ph1 = ashift_dly2_ff && ~ashift_dly1_ff && ~wren_bit;
|
|
|
|
// use phase two for wren since array writes in phase one
|
|
dffrl_async #(1) wren_reg (.din (wren_ph1),
|
|
.q (wren_ff),
|
|
.rst_l (arst_l),
|
|
.clk (int_clk2), .se(se), .si(), .so());
|
|
|
|
// address is never shifted out
|
|
assign spc_efc_xfuse_data = data_shft_ff[11];
|
|
assign fuse_ary_wren = wren_ff & testmode_l;
|
|
`endif
|
|
|
|
|
endmodule // cmp_sram_redhdr
|
endmodule // cmp_sram_redhdr
|
|
|
// Local Variables:
|
// Local Variables:
|
// verilog-library-directories:("." "../../common/rtl")
|
// verilog-library-directories:("." "../../common/rtl")
|
// verilog-library-files: ("../../common/rtl/swrvr_clib.v")
|
// verilog-library-files: ("../../common/rtl/swrvr_clib.v")
|
// verilog-auto-sense-defines-constant:t
|
// verilog-auto-sense-defines-constant:t
|
// End:
|
// End:
|
|
|