// ========== Copyright Header Begin ==========================================
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// ========== Copyright Header Begin ==========================================
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//
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//
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// OpenSPARC T1 Processor File: lsu_asi_decode.v
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// OpenSPARC T1 Processor File: lsu_asi_decode.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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//
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// The above named program is free software; you can redistribute it and/or
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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// License version 2 as published by the Free Software Foundation.
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//
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//
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// The above named program is distributed in the hope that it will be
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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// General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/*
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/*
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// Description: ASI Decode for LSU
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// Description: ASI Decode for LSU
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*/
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*/
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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// Global header file includes
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// Global header file includes
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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// system level definition file which contains the/*
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`include "sys.h" // system level definition file which contains the
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/* ========== Copyright Header Begin ==========================================
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*
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* OpenSPARC T1 Processor File: sys.h
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* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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*
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* The above named program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* The above named program is distributed in the hope that it will be
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* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public
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* License along with this work; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* ========== Copyright Header End ============================================
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*/
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// -*- verilog -*-
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////////////////////////////////////////////////////////////////////////
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/*
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//
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// Description: Global header file that contain definitions that
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// are common/shared at the systme level
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*/
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////////////////////////////////////////////////////////////////////////
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//
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// Setting the time scale
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// If the timescale changes, JP_TIMESCALE may also have to change.
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`timescale 1ps/1ps
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//
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// JBUS clock
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// =========
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//
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// Afara Link Defines
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// ==================
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// Reliable Link
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// Afara Link Objects
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// Afara Link Object Format - Reliable Link
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// Afara Link Object Format - Congestion
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// Afara Link Object Format - Acknowledge
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// Afara Link Object Format - Request
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// Afara Link Object Format - Message
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// Acknowledge Types
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// Request Types
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// Afara Link Frame
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//
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// UCB Packet Type
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// ===============
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//
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//
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// UCB Data Packet Format
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// ======================
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//
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// Size encoding for the UCB_SIZE_HI/LO field
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// 000 - byte
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// 001 - half-word
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// 010 - word
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// 011 - double-word
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// 111 - quad-word
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//
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// UCB Interrupt Packet Format
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// ===========================
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//
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//`define UCB_THR_HI 9 // (6) cpu/thread ID shared with
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//`define UCB_THR_LO 4 data packet format
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//`define UCB_PKT_HI 3 // (4) packet type shared with
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//`define UCB_PKT_LO 0 // data packet format
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//
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// FCRAM Bus Widths
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// ================
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//
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//
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// ENET clock periods
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// ==================
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//
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//
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// JBus Bridge defines
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// =================
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//
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//
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// PCI Device Address Configuration
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// ================================
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//
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// time scale definition
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// time scale definition
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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// Local header file includes / local defines
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// Local header file includes / local defines
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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module lsu_asi_decode (/*AUTOARG*/
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module lsu_asi_decode (/*AUTOARG*/
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// Outputs
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// Outputs
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asi_internal_d, nucleus_asi_d, primary_asi_d, secondary_asi_d,
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asi_internal_d, nucleus_asi_d, primary_asi_d, secondary_asi_d,
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lendian_asi_d, nofault_asi_d, quad_asi_d, binit_quad_asi_d,
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lendian_asi_d, nofault_asi_d, quad_asi_d, binit_quad_asi_d,
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dcache_byp_asi_d, tlb_lng_ltncy_asi_d, tlb_byp_asi_d,
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dcache_byp_asi_d, tlb_lng_ltncy_asi_d, tlb_byp_asi_d,
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as_if_user_asi_d, atomic_asi_d, blk_asi_d, dc_diagnstc_asi_d,
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as_if_user_asi_d, atomic_asi_d, blk_asi_d, dc_diagnstc_asi_d,
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dtagv_diagnstc_asi_d, wr_only_asi_d, rd_only_asi_d, unimp_asi_d,
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dtagv_diagnstc_asi_d, wr_only_asi_d, rd_only_asi_d, unimp_asi_d,
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ifu_nontlb_asi_d, recognized_asi_d, ifill_tlb_asi_d,
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ifu_nontlb_asi_d, recognized_asi_d, ifill_tlb_asi_d,
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dfill_tlb_asi_d, rd_only_ltlb_asi_d, wr_only_ltlb_asi_d,
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dfill_tlb_asi_d, rd_only_ltlb_asi_d, wr_only_ltlb_asi_d,
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phy_use_ec_asi_d, phy_byp_ec_asi_d, mmu_rd_only_asi_d,
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phy_use_ec_asi_d, phy_byp_ec_asi_d, mmu_rd_only_asi_d,
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intrpt_disp_asi_d, dmmu_asi58_d, immu_asi50_d,
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intrpt_disp_asi_d, dmmu_asi58_d, immu_asi50_d,
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// Inputs
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// Inputs
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asi_d
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asi_d
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);
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);
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input [7:0] asi_d ;
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input [7:0] asi_d ;
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output asi_internal_d ;
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output asi_internal_d ;
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output nucleus_asi_d ;
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output nucleus_asi_d ;
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output primary_asi_d ;
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output primary_asi_d ;
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output secondary_asi_d ;
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output secondary_asi_d ;
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output lendian_asi_d ;
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output lendian_asi_d ;
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output nofault_asi_d ;
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output nofault_asi_d ;
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output quad_asi_d ;
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output quad_asi_d ;
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output binit_quad_asi_d ;
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output binit_quad_asi_d ;
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output dcache_byp_asi_d ;
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output dcache_byp_asi_d ;
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output tlb_lng_ltncy_asi_d ;
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output tlb_lng_ltncy_asi_d ;
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output tlb_byp_asi_d ;
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output tlb_byp_asi_d ;
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output as_if_user_asi_d ;
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output as_if_user_asi_d ;
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output atomic_asi_d ;
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output atomic_asi_d ;
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output blk_asi_d ;
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output blk_asi_d ;
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//output blk_cmt_asi_d ;
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//output blk_cmt_asi_d ;
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output dc_diagnstc_asi_d;
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output dc_diagnstc_asi_d;
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output dtagv_diagnstc_asi_d;
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output dtagv_diagnstc_asi_d;
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output wr_only_asi_d ;
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output wr_only_asi_d ;
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output rd_only_asi_d ;
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output rd_only_asi_d ;
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output unimp_asi_d ;
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output unimp_asi_d ;
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output ifu_nontlb_asi_d ; // non-tlb asi's in ifu
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output ifu_nontlb_asi_d ; // non-tlb asi's in ifu
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output recognized_asi_d ;
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output recognized_asi_d ;
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output ifill_tlb_asi_d ; // itlb fill asi
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output ifill_tlb_asi_d ; // itlb fill asi
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output dfill_tlb_asi_d ; // dtlb fill asi
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output dfill_tlb_asi_d ; // dtlb fill asi
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output rd_only_ltlb_asi_d ; // read-only long-latency asi
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output rd_only_ltlb_asi_d ; // read-only long-latency asi
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output wr_only_ltlb_asi_d ; // write-only long-latency asi
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output wr_only_ltlb_asi_d ; // write-only long-latency asi
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output phy_use_ec_asi_d ;
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output phy_use_ec_asi_d ;
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output phy_byp_ec_asi_d ;
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output phy_byp_ec_asi_d ;
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output mmu_rd_only_asi_d ; // does not include asi with va
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output mmu_rd_only_asi_d ; // does not include asi with va
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output intrpt_disp_asi_d ;
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output intrpt_disp_asi_d ;
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output dmmu_asi58_d ;
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output dmmu_asi58_d ;
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output immu_asi50_d;
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output immu_asi50_d;
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wire quad_ldd_real, quad_ldd_real_little ;
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wire quad_ldd_real, quad_ldd_real_little ;
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wire asi_if_user_prim_all_d,asi_if_user_sec_all_d ;
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wire asi_if_user_prim_all_d,asi_if_user_sec_all_d ;
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wire asi_if_user_prim_d,asi_if_user_sec_d ;
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wire asi_if_user_prim_d,asi_if_user_sec_d ;
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wire nucleus_asi_exact_d ;
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wire nucleus_asi_exact_d ;
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wire prim_asi_exact_d ;
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wire prim_asi_exact_d ;
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wire phy_use_ec_asi ;
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wire phy_use_ec_asi ;
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wire phy_byp_ec_asi ;
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wire phy_byp_ec_asi ;
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wire sec_asi_exact_d ;
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wire sec_asi_exact_d ;
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wire idemap,ddemap,ddata_in,ddaccess ;
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wire idemap,ddemap,ddata_in,ddaccess ;
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wire dtag_read,idata_in,idaccess,invld_all,itag_read ;
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wire dtag_read,idata_in,idaccess,invld_all,itag_read ;
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wire blk_asif_usr_plittle, blk_asif_usr_slittle ;
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wire blk_asif_usr_plittle, blk_asif_usr_slittle ;
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wire blk_plittle, blk_slittle ;
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wire blk_plittle, blk_slittle ;
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wire blk_asif_usr_p, blk_asif_usr_s ;
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wire blk_asif_usr_p, blk_asif_usr_s ;
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wire blk_cmt_p, blk_cmt_s;
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wire blk_cmt_p, blk_cmt_s;
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wire blk_p, blk_s ;
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wire blk_p, blk_s ;
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wire binit_nucleus_d, binit_nucleus_little_d ;
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wire binit_nucleus_d, binit_nucleus_little_d ;
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wire real_mem_little,real_io_little ;
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wire real_mem_little,real_io_little ;
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wire unimp_CD_prm;
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wire unimp_CD_prm;
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wire unimp_CD_sec;
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wire unimp_CD_sec;
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// Start decode in d-stage. Required late e-stage. The logic could
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// Start decode in d-stage. Required late e-stage. The logic could
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// be moved to the e-stage to save staging flops.
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// be moved to the e-stage to save staging flops.
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wire dtsb_8k_ptr, dtsb_64k_ptr, dtsb_dir_ptr;
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wire dtsb_8k_ptr, dtsb_64k_ptr, dtsb_dir_ptr;
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wire itsb_8k_ptr, itsb_64k_ptr;
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wire itsb_8k_ptr, itsb_64k_ptr;
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assign dtsb_8k_ptr = (asi_d[7:0] == 8'h59) ;
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assign dtsb_8k_ptr = (asi_d[7:0] == 8'h59) ;
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assign dtsb_64k_ptr = (asi_d[7:0] == 8'h5A) ;
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assign dtsb_64k_ptr = (asi_d[7:0] == 8'h5A) ;
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assign dtsb_dir_ptr = (asi_d[7:0] == 8'h5B) ;
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assign dtsb_dir_ptr = (asi_d[7:0] == 8'h5B) ;
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assign itsb_8k_ptr = (asi_d[7:0] == 8'h51) ;
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assign itsb_8k_ptr = (asi_d[7:0] == 8'h51) ;
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assign itsb_64k_ptr = (asi_d[7:0] == 8'h52) ;
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assign itsb_64k_ptr = (asi_d[7:0] == 8'h52) ;
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assign mmu_rd_only_asi_d =
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assign mmu_rd_only_asi_d =
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dtsb_8k_ptr | dtsb_64k_ptr | dtsb_dir_ptr | itsb_8k_ptr | itsb_64k_ptr ;
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dtsb_8k_ptr | dtsb_64k_ptr | dtsb_dir_ptr | itsb_8k_ptr | itsb_64k_ptr ;
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assign intrpt_disp_asi_d = (asi_d[7:0] == 8'h73) ; // INTR_W
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assign intrpt_disp_asi_d = (asi_d[7:0] == 8'h73) ; // INTR_W
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assign dmmu_asi58_d = (asi_d[7:0] == 8'h58) ;
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assign dmmu_asi58_d = (asi_d[7:0] == 8'h58) ;
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assign immu_asi50_d = (asi_d[7:0] == 8'h50) ;
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assign immu_asi50_d = (asi_d[7:0] == 8'h50) ;
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// ASI Internal Registers - switches out thread among other things
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// ASI Internal Registers - switches out thread among other things
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assign asi_internal_d =
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assign asi_internal_d =
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(asi_d[7:0] == 8'h40) | // streaming/ma
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(asi_d[7:0] == 8'h40) | // streaming/ma
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(asi_d[7:0] == 8'h45) | // LSU Control
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(asi_d[7:0] == 8'h45) | // LSU Control
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(asi_d[7:0] == 8'h50) | // I-TSB Tag Target/SFSR/TSB/Tag-Access
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(asi_d[7:0] == 8'h50) | // I-TSB Tag Target/SFSR/TSB/Tag-Access
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itsb_8k_ptr | // I-TSB 8K Ptr
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itsb_8k_ptr | // I-TSB 8K Ptr
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itsb_64k_ptr | // I-TSB 64K Ptr
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itsb_64k_ptr | // I-TSB 64K Ptr
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dmmu_asi58_d |
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dmmu_asi58_d |
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//(asi_d[7:0] == 8'h58) | // D-TSB Tag Target/SFSR/SFAR/TSB/Tag-Access/VA-PA-Watchpt
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//(asi_d[7:0] == 8'h58) | // D-TSB Tag Target/SFSR/SFAR/TSB/Tag-Access/VA-PA-Watchpt
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(asi_d[7:0] == 8'h21) | // Primary/Secondary Context
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(asi_d[7:0] == 8'h21) | // Primary/Secondary Context
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(asi_d[7:0] == 8'h20) | // Scratchpad.
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(asi_d[7:0] == 8'h20) | // Scratchpad.
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(asi_d[7:0] == 8'h25) | // Queue
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(asi_d[7:0] == 8'h25) | // Queue
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(asi_d[7:0] == 8'h4F) | // Hyp Scratchpad
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(asi_d[7:0] == 8'h4F) | // Hyp Scratchpad
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dtsb_8k_ptr | // D-TSB 8K Ptr
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dtsb_8k_ptr | // D-TSB 8K Ptr
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dtsb_64k_ptr | // D-TSB 64K Ptr
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dtsb_64k_ptr | // D-TSB 64K Ptr
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dtsb_dir_ptr | // D-TSB Direct Ptr
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dtsb_dir_ptr | // D-TSB Direct Ptr
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(asi_d[7:0] == 8'h72) | // INTR_RECEIVE
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(asi_d[7:0] == 8'h72) | // INTR_RECEIVE
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intrpt_disp_asi_d | // INTR_W
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intrpt_disp_asi_d | // INTR_W
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(asi_d[7:0] == 8'h74) | // INTR_R
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(asi_d[7:0] == 8'h74) | // INTR_R
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(asi_d[7:0] == 8'h44) | // Self-Timed Margin Ctl
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(asi_d[7:0] == 8'h44) | // Self-Timed Margin Ctl
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(asi_d[7:0] == 8'h31) | // dmmu_zctxt_ps0_tsb
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(asi_d[7:0] == 8'h31) | // dmmu_zctxt_ps0_tsb
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(asi_d[7:0] == 8'h32) | // dmmu_zctxt_ps1_tsb
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(asi_d[7:0] == 8'h32) | // dmmu_zctxt_ps1_tsb
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(asi_d[7:0] == 8'h39) | // dmmu_nzctxt_ps0_tsb
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(asi_d[7:0] == 8'h39) | // dmmu_nzctxt_ps0_tsb
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(asi_d[7:0] == 8'h3A) | // dmmu_nzctxt_ps1_tsb
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(asi_d[7:0] == 8'h3A) | // dmmu_nzctxt_ps1_tsb
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(asi_d[7:0] == 8'h33) | // dmmu_zctxt_cfg_tsb
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(asi_d[7:0] == 8'h33) | // dmmu_zctxt_cfg_tsb
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(asi_d[7:0] == 8'h3B) | // dmmu_nzctxt_cfg_tsb
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(asi_d[7:0] == 8'h3B) | // dmmu_nzctxt_cfg_tsb
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(asi_d[7:0] == 8'h35) | // immu_zctxt_ps0_tsb
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(asi_d[7:0] == 8'h35) | // immu_zctxt_ps0_tsb
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(asi_d[7:0] == 8'h36) | // immu_zctxt_ps1_tsb
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(asi_d[7:0] == 8'h36) | // immu_zctxt_ps1_tsb
|
(asi_d[7:0] == 8'h3D) | // immu_nzctxt_ps0_tsb
|
(asi_d[7:0] == 8'h3D) | // immu_nzctxt_ps0_tsb
|
(asi_d[7:0] == 8'h3E) | // immu_nzctxt_ps1_tsb
|
(asi_d[7:0] == 8'h3E) | // immu_nzctxt_ps1_tsb
|
(asi_d[7:0] == 8'h37) | // immu_zctxt_cfg_tsb
|
(asi_d[7:0] == 8'h37) | // immu_zctxt_cfg_tsb
|
(asi_d[7:0] == 8'h3F) | // immu_nzctxt_cfg_tsb
|
(asi_d[7:0] == 8'h3F) | // immu_nzctxt_cfg_tsb
|
dc_diagnstc_asi_d | // Dcache Diagnostic
|
dc_diagnstc_asi_d | // Dcache Diagnostic
|
dtagv_diagnstc_asi_d | // Dcache Diagnostic
|
dtagv_diagnstc_asi_d | // Dcache Diagnostic
|
tlb_lng_ltncy_asi_d |
|
tlb_lng_ltncy_asi_d |
|
ifu_nontlb_asi_d ;
|
ifu_nontlb_asi_d ;
|
|
|
assign ifu_nontlb_asi_d =
|
assign ifu_nontlb_asi_d =
|
(asi_d[7:0] == 8'h42) | // instruction-mask
|
(asi_d[7:0] == 8'h42) | // instruction-mask
|
(asi_d[7:0] == 8'h43) | // error-inj
|
(asi_d[7:0] == 8'h43) | // error-inj
|
(asi_d[7:0] == 8'h4B) | // sparc-error-enable
|
(asi_d[7:0] == 8'h4B) | // sparc-error-enable
|
(asi_d[7:0] == 8'h4C) | // sparc-error-status
|
(asi_d[7:0] == 8'h4C) | // sparc-error-status
|
(asi_d[7:0] == 8'h4D) | // sparc-error-address
|
(asi_d[7:0] == 8'h4D) | // sparc-error-address
|
(asi_d[7:0] == 8'h66) | // icache-instr
|
(asi_d[7:0] == 8'h66) | // icache-instr
|
(asi_d[7:0] == 8'h67) ; // icache-tag
|
(asi_d[7:0] == 8'h67) ; // icache-tag
|
|
|
assign dc_diagnstc_asi_d = (asi_d[7:0] == 8'h46) ;
|
assign dc_diagnstc_asi_d = (asi_d[7:0] == 8'h46) ;
|
assign dtagv_diagnstc_asi_d = (asi_d[7:0] == 8'h47) ;
|
assign dtagv_diagnstc_asi_d = (asi_d[7:0] == 8'h47) ;
|
|
|
assign idemap = (asi_d[7:0] == 8'h57) ; // I-MMU Demap Operation
|
assign idemap = (asi_d[7:0] == 8'h57) ; // I-MMU Demap Operation
|
assign ddemap = (asi_d[7:0] == 8'h5F) ; // D-MMU Demap Operation
|
assign ddemap = (asi_d[7:0] == 8'h5F) ; // D-MMU Demap Operation
|
assign ddata_in = (asi_d[7:0] == 8'h5C) ; // D-TLB Data-In
|
assign ddata_in = (asi_d[7:0] == 8'h5C) ; // D-TLB Data-In
|
assign ddaccess = (asi_d[7:0] == 8'h5D) ; // D-TLB Data-Access
|
assign ddaccess = (asi_d[7:0] == 8'h5D) ; // D-TLB Data-Access
|
assign dtag_read = (asi_d[7:0] == 8'h5E) ; // D-TLB Tag Read
|
assign dtag_read = (asi_d[7:0] == 8'h5E) ; // D-TLB Tag Read
|
assign idata_in = (asi_d[7:0] == 8'h54) ; // I-TLB Data-In
|
assign idata_in = (asi_d[7:0] == 8'h54) ; // I-TLB Data-In
|
assign idaccess = (asi_d[7:0] == 8'h55) ; // I-TLB Data-Access
|
assign idaccess = (asi_d[7:0] == 8'h55) ; // I-TLB Data-Access
|
assign invld_all = (asi_d[7:0] == 8'h60) ; // I/D Invalidate All
|
assign invld_all = (asi_d[7:0] == 8'h60) ; // I/D Invalidate All
|
assign itag_read = (asi_d[7:0] == 8'h56) ; // I-TLB Tag Read
|
assign itag_read = (asi_d[7:0] == 8'h56) ; // I-TLB Tag Read
|
|
|
assign tlb_lng_ltncy_asi_d =
|
assign tlb_lng_ltncy_asi_d =
|
idemap | ddemap | ddata_in |
|
idemap | ddemap | ddata_in |
|
ddaccess | dtag_read | idata_in |
|
ddaccess | dtag_read | idata_in |
|
idaccess | invld_all | itag_read ;
|
idaccess | invld_all | itag_read ;
|
|
|
assign wr_only_ltlb_asi_d =
|
assign wr_only_ltlb_asi_d =
|
ddata_in | idata_in |
|
ddata_in | idata_in |
|
idemap | ddemap |
|
idemap | ddemap |
|
invld_all ;
|
invld_all ;
|
|
|
assign rd_only_ltlb_asi_d =
|
assign rd_only_ltlb_asi_d =
|
dtag_read | itag_read ;
|
dtag_read | itag_read ;
|
|
|
assign ifill_tlb_asi_d = // itlb fill asi
|
assign ifill_tlb_asi_d = // itlb fill asi
|
idata_in | idaccess ;
|
idata_in | idaccess ;
|
|
|
assign dfill_tlb_asi_d = // i/d tlb fill asi
|
assign dfill_tlb_asi_d = // i/d tlb fill asi
|
ddata_in | ddaccess ;
|
ddata_in | ddaccess ;
|
|
|
assign nucleus_asi_exact_d =
|
assign nucleus_asi_exact_d =
|
(asi_d[7:0] == 8'h04) | // asi_nucleus
|
(asi_d[7:0] == 8'h04) | // asi_nucleus
|
(asi_d[7:0] == 8'h0C) ; // asi_nucleus_little
|
(asi_d[7:0] == 8'h0C) ; // asi_nucleus_little
|
|
|
// Nucleus Ctxt
|
// Nucleus Ctxt
|
assign nucleus_asi_d =
|
assign nucleus_asi_d =
|
nucleus_asi_exact_d |
|
nucleus_asi_exact_d |
|
(asi_d[7:0] == 8'h24) | // asi_nucleus_quad_ldd
|
(asi_d[7:0] == 8'h24) | // asi_nucleus_quad_ldd
|
(asi_d[7:0] == 8'h2C) ; // asi_nucleus_quad_ldd_little
|
(asi_d[7:0] == 8'h2C) ; // asi_nucleus_quad_ldd_little
|
|
|
assign asi_if_user_prim_d =
|
assign asi_if_user_prim_d =
|
(asi_d[7:0] == 8'h10) | // asi_as_if_user_primary
|
(asi_d[7:0] == 8'h10) | // asi_as_if_user_primary
|
(asi_d[7:0] == 8'h18) ; // asi_as_if_user_primary_little
|
(asi_d[7:0] == 8'h18) ; // asi_as_if_user_primary_little
|
|
|
// asi_if_user primary asi
|
// asi_if_user primary asi
|
assign asi_if_user_prim_all_d =
|
assign asi_if_user_prim_all_d =
|
asi_if_user_prim_d |
|
asi_if_user_prim_d |
|
(asi_d[7:0] == 8'h22) | // asi_as_if_user_primary_quad_ldd (blk-init)
|
(asi_d[7:0] == 8'h22) | // asi_as_if_user_primary_quad_ldd (blk-init)
|
(asi_d[7:0] == 8'h2A) ; // asi_as_if_user_primary_quad_ldd_little (blk-init)
|
(asi_d[7:0] == 8'h2A) ; // asi_as_if_user_primary_quad_ldd_little (blk-init)
|
|
|
assign prim_asi_exact_d =
|
assign prim_asi_exact_d =
|
(asi_d[7:0] == 8'h80) | // asi_primary
|
(asi_d[7:0] == 8'h80) | // asi_primary
|
(asi_d[7:0] == 8'h88) ; // asi_primary_little
|
(asi_d[7:0] == 8'h88) ; // asi_primary_little
|
|
|
// Primary Ctxt
|
// Primary Ctxt
|
assign primary_asi_d =
|
assign primary_asi_d =
|
asi_if_user_prim_all_d |
|
asi_if_user_prim_all_d |
|
prim_asi_exact_d |
|
prim_asi_exact_d |
|
(asi_d[7:0] == 8'h82) | // asi_primary_no_fault
|
(asi_d[7:0] == 8'h82) | // asi_primary_no_fault
|
(asi_d[7:0] == 8'h8A) | // asi_primary_no_fault_little
|
(asi_d[7:0] == 8'h8A) | // asi_primary_no_fault_little
|
(asi_d[7:0] == 8'hE2) | // asi_primary_quad_ldd (blk-init)
|
(asi_d[7:0] == 8'hE2) | // asi_primary_quad_ldd (blk-init)
|
(asi_d[7:0] == 8'hEA) | // asi_primary_quad_ldd_little (blk-init)
|
(asi_d[7:0] == 8'hEA) | // asi_primary_quad_ldd_little (blk-init)
|
blk_asif_usr_p | blk_asif_usr_plittle |
|
blk_asif_usr_p | blk_asif_usr_plittle |
|
blk_plittle | blk_p | // block primary asi
|
blk_plittle | blk_p | // block primary asi
|
blk_cmt_p | // Bug 4051
|
blk_cmt_p | // Bug 4051
|
unimp_CD_prm ; // Bug 4532
|
unimp_CD_prm ; // Bug 4532
|
|
|
assign asi_if_user_sec_d =
|
assign asi_if_user_sec_d =
|
(asi_d[7:0] == 8'h11) | // asi_as_if_user_secondary
|
(asi_d[7:0] == 8'h11) | // asi_as_if_user_secondary
|
(asi_d[7:0] == 8'h19) ; // asi_as_if_user_secondary_little
|
(asi_d[7:0] == 8'h19) ; // asi_as_if_user_secondary_little
|
|
|
// asi_if_user secondary asi
|
// asi_if_user secondary asi
|
assign asi_if_user_sec_all_d =
|
assign asi_if_user_sec_all_d =
|
asi_if_user_sec_d |
|
asi_if_user_sec_d |
|
(asi_d[7:0] == 8'h23) | // asi_as_if_user_secondary_quad_ldd (blk-init)
|
(asi_d[7:0] == 8'h23) | // asi_as_if_user_secondary_quad_ldd (blk-init)
|
(asi_d[7:0] == 8'h2B) ; // asi_as_if_user_secondary_quad_ldd_little (blk-init)
|
(asi_d[7:0] == 8'h2B) ; // asi_as_if_user_secondary_quad_ldd_little (blk-init)
|
|
|
assign as_if_user_asi_d = asi_if_user_prim_all_d | asi_if_user_sec_all_d |
|
assign as_if_user_asi_d = asi_if_user_prim_all_d | asi_if_user_sec_all_d |
|
blk_asif_usr_p | blk_asif_usr_plittle | blk_asif_usr_s | blk_asif_usr_slittle ;
|
blk_asif_usr_p | blk_asif_usr_plittle | blk_asif_usr_s | blk_asif_usr_slittle ;
|
|
|
assign sec_asi_exact_d =
|
assign sec_asi_exact_d =
|
(asi_d[7:0] == 8'h81) | // asi_secondary
|
(asi_d[7:0] == 8'h81) | // asi_secondary
|
(asi_d[7:0] == 8'h89) ; // asi_secondary_little
|
(asi_d[7:0] == 8'h89) ; // asi_secondary_little
|
|
|
// Secondary Ctxt
|
// Secondary Ctxt
|
assign secondary_asi_d =
|
assign secondary_asi_d =
|
asi_if_user_sec_all_d |
|
asi_if_user_sec_all_d |
|
sec_asi_exact_d |
|
sec_asi_exact_d |
|
(asi_d[7:0] == 8'h83) | // asi_secondary_no_fault
|
(asi_d[7:0] == 8'h83) | // asi_secondary_no_fault
|
(asi_d[7:0] == 8'h8B) | // asi_secondary_no_fault_little
|
(asi_d[7:0] == 8'h8B) | // asi_secondary_no_fault_little
|
(asi_d[7:0] == 8'hE3) | // asi_secondary_quad_ldd (blk-init)
|
(asi_d[7:0] == 8'hE3) | // asi_secondary_quad_ldd (blk-init)
|
(asi_d[7:0] == 8'hEB) | // asi_secondary_quad_ldd_little (blk-init)
|
(asi_d[7:0] == 8'hEB) | // asi_secondary_quad_ldd_little (blk-init)
|
blk_asif_usr_s | blk_asif_usr_slittle |
|
blk_asif_usr_s | blk_asif_usr_slittle |
|
blk_slittle | blk_s | // block secondary asi
|
blk_slittle | blk_s | // block secondary asi
|
blk_cmt_s | // Bug 4051
|
blk_cmt_s | // Bug 4051
|
unimp_CD_sec; // Bug 4532
|
unimp_CD_sec; // Bug 4532
|
|
|
// Little Endian
|
// Little Endian
|
assign lendian_asi_d =
|
assign lendian_asi_d =
|
(asi_d[7:0] == 8'h0C) | // asi_nucleus_little
|
(asi_d[7:0] == 8'h0C) | // asi_nucleus_little
|
(asi_d[7:0] == 8'h2C) | // asi_nucleus_quad_ldd_little
|
(asi_d[7:0] == 8'h2C) | // asi_nucleus_quad_ldd_little
|
(asi_d[7:0] == 8'h18) | // asi_as_if_user_primary_little
|
(asi_d[7:0] == 8'h18) | // asi_as_if_user_primary_little
|
(asi_d[7:0] == 8'h8A) | // asi_primary_no_fault_little
|
(asi_d[7:0] == 8'h8A) | // asi_primary_no_fault_little
|
(asi_d[7:0] == 8'h8B) | // asi_secondary_no_fault_little
|
(asi_d[7:0] == 8'h8B) | // asi_secondary_no_fault_little
|
(asi_d[7:0] == 8'h2A) | // asi_as_if_user_primary_quad_ldd_little (blk-init)
|
(asi_d[7:0] == 8'h2A) | // asi_as_if_user_primary_quad_ldd_little (blk-init)
|
(asi_d[7:0] == 8'hEA) | // asi_primary_quad_ldd_little (blk-init)
|
(asi_d[7:0] == 8'hEA) | // asi_primary_quad_ldd_little (blk-init)
|
(asi_d[7:0] == 8'h19) | // asi_as_if_user_secondary_little
|
(asi_d[7:0] == 8'h19) | // asi_as_if_user_secondary_little
|
(asi_d[7:0] == 8'h89) | // asi_secondary_little
|
(asi_d[7:0] == 8'h89) | // asi_secondary_little
|
(asi_d[7:0] == 8'h88) | // asi_primary_little
|
(asi_d[7:0] == 8'h88) | // asi_primary_little
|
(asi_d[7:0] == 8'h2B) | // asi_as_if_user_secondary_quad_ldd_little (blk-init)
|
(asi_d[7:0] == 8'h2B) | // asi_as_if_user_secondary_quad_ldd_little (blk-init)
|
(asi_d[7:0] == 8'hEB) | // asi_secondary_quad_ldd_little (blk-init)
|
(asi_d[7:0] == 8'hEB) | // asi_secondary_quad_ldd_little (blk-init)
|
real_mem_little |
|
real_mem_little |
|
real_io_little |
|
real_io_little |
|
//(asi_d[7:0] == 8'h1D) | // asi_phys_bypass_ec_with_ebit_littl
|
//(asi_d[7:0] == 8'h1D) | // asi_phys_bypass_ec_with_ebit_littl
|
//(asi_d[7:0] == 8'h1C) | // asi_phys_bypass_ec_with_ebit_littl
|
//(asi_d[7:0] == 8'h1C) | // asi_phys_bypass_ec_with_ebit_littl
|
blk_asif_usr_plittle | blk_asif_usr_slittle | // little
|
blk_asif_usr_plittle | blk_asif_usr_slittle | // little
|
blk_plittle | blk_slittle | // little
|
blk_plittle | blk_slittle | // little
|
quad_ldd_real_little | // asi_quad_ldd_real_little
|
quad_ldd_real_little | // asi_quad_ldd_real_little
|
binit_nucleus_little_d ;// asi_nucleus_blk_init_st_quad_ldd_little
|
binit_nucleus_little_d ;// asi_nucleus_blk_init_st_quad_ldd_little
|
|
|
// No Fault
|
// No Fault
|
assign nofault_asi_d =
|
assign nofault_asi_d =
|
(asi_d[7:0] == 8'h82) | // asi_primary_no_fault
|
(asi_d[7:0] == 8'h82) | // asi_primary_no_fault
|
(asi_d[7:0] == 8'h8A) | // asi_primary_no_fault_little
|
(asi_d[7:0] == 8'h8A) | // asi_primary_no_fault_little
|
(asi_d[7:0] == 8'h83) | // asi_secondary_no_fault
|
(asi_d[7:0] == 8'h83) | // asi_secondary_no_fault
|
(asi_d[7:0] == 8'h8B) ; // asi_secondary_no_fault_little
|
(asi_d[7:0] == 8'h8B) ; // asi_secondary_no_fault_little
|
|
|
assign binit_nucleus_d =
|
assign binit_nucleus_d =
|
(asi_d[7:0] == 8'h27) ; // asi_nucleus_blk_init_st_quad_ldd
|
(asi_d[7:0] == 8'h27) ; // asi_nucleus_blk_init_st_quad_ldd
|
assign binit_nucleus_little_d =
|
assign binit_nucleus_little_d =
|
(asi_d[7:0] == 8'h2F) ; // asi_nucleus_blk_init_st_quad_ldd_little
|
(asi_d[7:0] == 8'h2F) ; // asi_nucleus_blk_init_st_quad_ldd_little
|
|
|
// Quad (These are duplicated - they can be shared)
|
// Quad (These are duplicated - they can be shared)
|
assign binit_quad_asi_d =
|
assign binit_quad_asi_d =
|
binit_nucleus_d | // asi_nucleus_blk_init_st_quad_ldd
|
binit_nucleus_d | // asi_nucleus_blk_init_st_quad_ldd
|
binit_nucleus_little_d |// asi_nucleus_blk_init_st_quad_ldd_little
|
binit_nucleus_little_d |// asi_nucleus_blk_init_st_quad_ldd_little
|
(asi_d[7:0] == 8'h22) | // asi_as_if_user_primary_quad_ldd (blk-init)
|
(asi_d[7:0] == 8'h22) | // asi_as_if_user_primary_quad_ldd (blk-init)
|
(asi_d[7:0] == 8'h2A) | // asi_as_if_user_primary_quad_ldd_little (blk-init)
|
(asi_d[7:0] == 8'h2A) | // asi_as_if_user_primary_quad_ldd_little (blk-init)
|
(asi_d[7:0] == 8'h23) | // asi_as_if_user_secondary_quad_ldd (blk-init)
|
(asi_d[7:0] == 8'h23) | // asi_as_if_user_secondary_quad_ldd (blk-init)
|
(asi_d[7:0] == 8'h2B) | // asi_as_if_user_secondary_quad_ldd_little (blk-init)
|
(asi_d[7:0] == 8'h2B) | // asi_as_if_user_secondary_quad_ldd_little (blk-init)
|
(asi_d[7:0] == 8'hE2) | // asi_primary_quad_ldd (blk-init)
|
(asi_d[7:0] == 8'hE2) | // asi_primary_quad_ldd (blk-init)
|
(asi_d[7:0] == 8'hEA) | // asi_primary_quad_ldd_little (blk-init)
|
(asi_d[7:0] == 8'hEA) | // asi_primary_quad_ldd_little (blk-init)
|
(asi_d[7:0] == 8'hE3) | // asi_secondary_quad_ldd (blk-init)
|
(asi_d[7:0] == 8'hE3) | // asi_secondary_quad_ldd (blk-init)
|
(asi_d[7:0] == 8'hEB) ; // asi_secondary_quad_ldd_little (blk-init)
|
(asi_d[7:0] == 8'hEB) ; // asi_secondary_quad_ldd_little (blk-init)
|
|
|
assign quad_ldd_real =
|
assign quad_ldd_real =
|
(asi_d[7:0] == 8'h26) ; // asi_quad_ldd_real
|
(asi_d[7:0] == 8'h26) ; // asi_quad_ldd_real
|
assign quad_ldd_real_little =
|
assign quad_ldd_real_little =
|
(asi_d[7:0] == 8'h2E) ; // asi_quad_ldd_real_little
|
(asi_d[7:0] == 8'h2E) ; // asi_quad_ldd_real_little
|
|
|
assign quad_asi_d =
|
assign quad_asi_d =
|
binit_quad_asi_d | // blk-init quad asi
|
binit_quad_asi_d | // blk-init quad asi
|
quad_ldd_real | // asi_quad_ldd_real
|
quad_ldd_real | // asi_quad_ldd_real
|
quad_ldd_real_little | // asi_quad_ldd_real_little
|
quad_ldd_real_little | // asi_quad_ldd_real_little
|
(asi_d[7:0] == 8'h24) | // asi_nucleus_quad_ldd
|
(asi_d[7:0] == 8'h24) | // asi_nucleus_quad_ldd
|
(asi_d[7:0] == 8'h2C) ; // asi_nucleus_quad_ldd_little
|
(asi_d[7:0] == 8'h2C) ; // asi_nucleus_quad_ldd_little
|
|
|
// EC
|
// EC
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assign real_io_little = (asi_d[7:0] == 8'h1D) ;
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assign real_io_little = (asi_d[7:0] == 8'h1D) ;
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assign real_mem_little = (asi_d[7:0] == 8'h1C) ;
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assign real_mem_little = (asi_d[7:0] == 8'h1C) ;
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assign phy_byp_ec_asi =
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assign phy_byp_ec_asi =
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(asi_d[7:0] == 8'h15) | // asi_phys_bypass_ec_with_ebit(real_io)
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(asi_d[7:0] == 8'h15) | // asi_phys_bypass_ec_with_ebit(real_io)
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real_io_little ; // asi_phys_bypass_ec_with_ebit_little(real_io_little)
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real_io_little ; // asi_phys_bypass_ec_with_ebit_little(real_io_little)
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//(asi_d[7:0] == 8'h1D) ; // asi_phys_bypass_ec_with_ebit_little(real_io_little)
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//(asi_d[7:0] == 8'h1D) ; // asi_phys_bypass_ec_with_ebit_little(real_io_little)
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// asi assumed for io address specifically !!
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// asi assumed for io address specifically !!
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// asi assumed for io address specifically !!
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// asi assumed for io address specifically !!
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assign phy_use_ec_asi =
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assign phy_use_ec_asi =
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(asi_d[7:0] == 8'h14) | // asi_phys_use_ec(real_mem)
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(asi_d[7:0] == 8'h14) | // asi_phys_use_ec(real_mem)
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real_mem_little ; // asi_phys_use_ec_little(real_mem_little)
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real_mem_little ; // asi_phys_use_ec_little(real_mem_little)
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//(asi_d[7:0] == 8'h1C) ; // asi_phys_use_ec_little(real_mem_little)
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//(asi_d[7:0] == 8'h1C) ; // asi_phys_use_ec_little(real_mem_little)
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assign phy_use_ec_asi_d = phy_use_ec_asi ;
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assign phy_use_ec_asi_d = phy_use_ec_asi ;
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assign phy_byp_ec_asi_d = phy_byp_ec_asi ;
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assign phy_byp_ec_asi_d = phy_byp_ec_asi ;
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// Physical Use - Always results in R->P xslation.
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// Physical Use - Always results in R->P xslation.
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assign tlb_byp_asi_d =
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assign tlb_byp_asi_d =
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phy_byp_ec_asi | phy_use_ec_asi |
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phy_byp_ec_asi | phy_use_ec_asi |
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quad_ldd_real | quad_ldd_real_little ;
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quad_ldd_real | quad_ldd_real_little ;
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// Atomic asi
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// Atomic asi
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assign atomic_asi_d = nucleus_asi_exact_d | prim_asi_exact_d | sec_asi_exact_d |
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assign atomic_asi_d = nucleus_asi_exact_d | prim_asi_exact_d | sec_asi_exact_d |
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asi_if_user_prim_d | asi_if_user_sec_d | phy_use_ec_asi ;
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asi_if_user_prim_d | asi_if_user_sec_d | phy_use_ec_asi ;
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assign dcache_byp_asi_d = tlb_byp_asi_d ;
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assign dcache_byp_asi_d = tlb_byp_asi_d ;
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// ASI causing Data Access Exceptions - (TBD)
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// ASI causing Data Access Exceptions - (TBD)
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assign rd_only_asi_d =
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assign rd_only_asi_d =
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(asi_d[7:0] == 8'h82) | // asi_primary_no_fault
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(asi_d[7:0] == 8'h82) | // asi_primary_no_fault
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(asi_d[7:0] == 8'h8A) | // asi_primary_no_fault_little
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(asi_d[7:0] == 8'h8A) | // asi_primary_no_fault_little
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(asi_d[7:0] == 8'h83) | // asi_secondary_no_fault
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(asi_d[7:0] == 8'h83) | // asi_secondary_no_fault
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(asi_d[7:0] == 8'h8B) | // asi_secondary_no_fault_little
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(asi_d[7:0] == 8'h8B) | // asi_secondary_no_fault_little
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(asi_d[7:0] == 8'h74) ; // asi_swrvr_udb_intr_r !! Does not have to be done by intrpt blk !!
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(asi_d[7:0] == 8'h74) ; // asi_swrvr_udb_intr_r !! Does not have to be done by intrpt blk !!
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assign wr_only_asi_d =
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assign wr_only_asi_d =
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(asi_d[7:0] == 8'h73) ; // asi_swrvr_udb_intr_w
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(asi_d[7:0] == 8'h73) ; // asi_swrvr_udb_intr_w
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// Block Asi
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// Block Asi
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assign blk_asif_usr_p = (asi_d[7:0] == 8'h16) ; // asi_block_as_if_user_primary
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assign blk_asif_usr_p = (asi_d[7:0] == 8'h16) ; // asi_block_as_if_user_primary
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assign blk_asif_usr_plittle = (asi_d[7:0] == 8'h1E) ; // asi_block_as_if_user_primary_little
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assign blk_asif_usr_plittle = (asi_d[7:0] == 8'h1E) ; // asi_block_as_if_user_primary_little
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assign blk_asif_usr_s = (asi_d[7:0] == 8'h17) ; // asi_block_as_if_user_secondary
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assign blk_asif_usr_s = (asi_d[7:0] == 8'h17) ; // asi_block_as_if_user_secondary
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assign blk_asif_usr_slittle = (asi_d[7:0] == 8'h1F) ; // asi_block_as_if_user_secondary_little
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assign blk_asif_usr_slittle = (asi_d[7:0] == 8'h1F) ; // asi_block_as_if_user_secondary_little
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assign blk_plittle = (asi_d[7:0] == 8'hF8) ; // asi_block_primary_little
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assign blk_plittle = (asi_d[7:0] == 8'hF8) ; // asi_block_primary_little
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assign blk_slittle = (asi_d[7:0] == 8'hF9) ; // asi_block_secondary_little
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assign blk_slittle = (asi_d[7:0] == 8'hF9) ; // asi_block_secondary_little
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assign blk_cmt_p = (asi_d[7:0] == 8'hE0) ; // asi_block_commit_primary ?? behaviour
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assign blk_cmt_p = (asi_d[7:0] == 8'hE0) ; // asi_block_commit_primary ?? behaviour
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assign blk_cmt_s = (asi_d[7:0] == 8'hE1) ; // asi_block_commit_secondary ?? behaviour
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assign blk_cmt_s = (asi_d[7:0] == 8'hE1) ; // asi_block_commit_secondary ?? behaviour
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assign blk_p = (asi_d[7:0] == 8'hF0) ; // asi_block_primary
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assign blk_p = (asi_d[7:0] == 8'hF0) ; // asi_block_primary
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assign blk_s = (asi_d[7:0] == 8'hF1) ; // asi_block_secondary
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assign blk_s = (asi_d[7:0] == 8'hF1) ; // asi_block_secondary
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//assign blk_cmt_asi_d = blk_cmt_p | blk_cmt_s ;
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//assign blk_cmt_asi_d = blk_cmt_p | blk_cmt_s ;
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assign blk_asi_d =
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assign blk_asi_d =
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blk_asif_usr_p | blk_asif_usr_s |
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blk_asif_usr_p | blk_asif_usr_s |
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blk_plittle | blk_slittle |
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blk_plittle | blk_slittle |
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//blk_cmt_p | blk_cmt_s |
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//blk_cmt_p | blk_cmt_s |
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blk_p | blk_s |
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blk_p | blk_s |
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blk_asif_usr_plittle | blk_asif_usr_slittle | // little
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blk_asif_usr_plittle | blk_asif_usr_slittle | // little
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blk_plittle | blk_slittle ; // little
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blk_plittle | blk_slittle ; // little
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// add to little-endian decode
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// add to little-endian decode
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// add to use_real ...
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// add to use_real ...
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//assign as_if_supv =
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//assign as_if_supv =
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// (asi_d[7:0] == 8'h??) | // asi_if_supv_real
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// (asi_d[7:0] == 8'h??) | // asi_if_supv_real
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// (asi_d[7:0] == 8'h??) ; // asi_if_supv_real_little
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// (asi_d[7:0] == 8'h??) ; // asi_if_supv_real_little
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wire unimp_C ;
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wire unimp_C ;
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assign unimp_C =
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assign unimp_C =
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((asi_d[7:4]==4'hC) &
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((asi_d[7:4]==4'hC) &
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~((asi_d[3:0]==4'h6) |
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~((asi_d[3:0]==4'h6) |
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(asi_d[3:0]==4'h7) |
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(asi_d[3:0]==4'h7) |
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(asi_d[3:0]==4'hE) |
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(asi_d[3:0]==4'hE) |
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(asi_d[3:0]==4'hF))) ;
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(asi_d[3:0]==4'hF))) ;
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wire unimp_D ;
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wire unimp_D ;
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assign unimp_D =
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assign unimp_D =
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((asi_d[7:4]==4'hD) &
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((asi_d[7:4]==4'hD) &
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~((asi_d[3:0]==4'h4) |
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~((asi_d[3:0]==4'h4) |
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(asi_d[3:0]==4'h5) |
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(asi_d[3:0]==4'h5) |
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(asi_d[3:0]==4'h6) |
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(asi_d[3:0]==4'h6) |
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(asi_d[3:0]==4'h7) |
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(asi_d[3:0]==4'h7) |
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(asi_d[3:0]==4'hC) |
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(asi_d[3:0]==4'hC) |
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(asi_d[3:0]==4'hD) |
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(asi_d[3:0]==4'hD) |
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(asi_d[3:0]==4'hE) |
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(asi_d[3:0]==4'hE) |
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(asi_d[3:0]==4'hF))) ;
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(asi_d[3:0]==4'hF))) ;
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assign unimp_CD_prm =
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assign unimp_CD_prm =
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(asi_d[7:0] == 8'hC0) |
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(asi_d[7:0] == 8'hC0) |
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(asi_d[7:0] == 8'hC2) |
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(asi_d[7:0] == 8'hC2) |
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(asi_d[7:0] == 8'hC4) |
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(asi_d[7:0] == 8'hC4) |
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(asi_d[7:0] == 8'hC8) |
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(asi_d[7:0] == 8'hC8) |
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(asi_d[7:0] == 8'hCA) |
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(asi_d[7:0] == 8'hCA) |
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(asi_d[7:0] == 8'hCC) |
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(asi_d[7:0] == 8'hCC) |
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(asi_d[7:0] == 8'hD0) |
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(asi_d[7:0] == 8'hD0) |
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(asi_d[7:0] == 8'hD2) |
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(asi_d[7:0] == 8'hD2) |
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(asi_d[7:0] == 8'hD8) |
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(asi_d[7:0] == 8'hD8) |
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(asi_d[7:0] == 8'hDA) ;
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(asi_d[7:0] == 8'hDA) ;
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assign unimp_CD_sec =
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assign unimp_CD_sec =
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(asi_d[7:0] == 8'hC1) |
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(asi_d[7:0] == 8'hC1) |
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(asi_d[7:0] == 8'hC3) |
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(asi_d[7:0] == 8'hC3) |
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(asi_d[7:0] == 8'hC5) |
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(asi_d[7:0] == 8'hC5) |
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(asi_d[7:0] == 8'hC9) |
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(asi_d[7:0] == 8'hC9) |
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(asi_d[7:0] == 8'hCB) |
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(asi_d[7:0] == 8'hCB) |
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(asi_d[7:0] == 8'hCD) |
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(asi_d[7:0] == 8'hCD) |
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(asi_d[7:0] == 8'hD1) |
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(asi_d[7:0] == 8'hD1) |
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(asi_d[7:0] == 8'hD3) |
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(asi_d[7:0] == 8'hD3) |
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(asi_d[7:0] == 8'hD9) |
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(asi_d[7:0] == 8'hD9) |
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(asi_d[7:0] == 8'hDB) ;
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(asi_d[7:0] == 8'hDB) ;
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// Unimplemented asi
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// Unimplemented asi
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assign unimp_asi_d =
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assign unimp_asi_d =
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// Bug 4692 - all unimplemented internal asi are now
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// Bug 4692 - all unimplemented internal asi are now
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// illegal.
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// illegal.
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// (asi_d[7:0] == 8'h6E) | // asi_icache_pre_decode
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// (asi_d[7:0] == 8'h6E) | // asi_icache_pre_decode
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// (asi_d[7:0] == 8'h6F) | // asi_icache_next_field
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// (asi_d[7:0] == 8'h6F) | // asi_icache_next_field
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// (asi_d[7:0] == 8'h48) | // asi_intr_dispatch_status
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// (asi_d[7:0] == 8'h48) | // asi_intr_dispatch_status
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// (asi_d[7:0] == 8'h49) | // asi_intr_receive
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// (asi_d[7:0] == 8'h49) | // asi_intr_receive
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// (asi_d[7:0] == 8'h4A) | // asi_upa_config_register
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// (asi_d[7:0] == 8'h4A) | // asi_upa_config_register
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// (asi_d[7:0] == 8'h4E) | // asi_ecache_tag_data
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// (asi_d[7:0] == 8'h4E) | // asi_ecache_tag_data
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// dflush_asi_d | //Bug 4580
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// dflush_asi_d | //Bug 4580
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unimp_C | unimp_D | // Bug 4438
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unimp_C | unimp_D | // Bug 4438
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blk_cmt_p | blk_cmt_s ;
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blk_cmt_p | blk_cmt_s ;
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// Set of recognized asi's
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// Set of recognized asi's
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assign recognized_asi_d =
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assign recognized_asi_d =
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asi_internal_d | nucleus_asi_d | primary_asi_d | secondary_asi_d | lendian_asi_d |
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asi_internal_d | nucleus_asi_d | primary_asi_d | secondary_asi_d | lendian_asi_d |
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nofault_asi_d | quad_asi_d | tlb_byp_asi_d | unimp_asi_d | blk_asi_d ;
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nofault_asi_d | quad_asi_d | tlb_byp_asi_d | unimp_asi_d | blk_asi_d ;
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// Displacement Flush for L2
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// Displacement Flush for L2
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//assign dflush_asi_d =
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//assign dflush_asi_d =
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// (asi_d[7:0] == 8'h30) ; // asi_direct_map_ecache
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// (asi_d[7:0] == 8'h30) ; // asi_direct_map_ecache
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endmodule
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endmodule
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