// ========== Copyright Header Begin ==========================================
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// ========== Copyright Header Begin ==========================================
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//
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//
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// OpenSPARC T1 Processor File: lsu_pcx_qmon.v
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// OpenSPARC T1 Processor File: lsu_pcx_qmon.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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//
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// The above named program is free software; you can redistribute it and/or
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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// License version 2 as published by the Free Software Foundation.
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//
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//
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// The above named program is distributed in the hope that it will be
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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// General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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`ifdef SIMPLY_RISC_TWEAKS
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`define SIMPLY_RISC_SCANIN .si(0)
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`else
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`define SIMPLY_RISC_SCANIN .si()
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`endif
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/*
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/*
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// Description: Monitors queue state of pcx.
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// Description: Monitors queue state of pcx.
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*/
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*/
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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// Global header file includes
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// Global header file includes
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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// system level definition file which contains the/*
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`include "sys.h" // system level definition file which contains the
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/* ========== Copyright Header Begin ==========================================
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*
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* OpenSPARC T1 Processor File: sys.h
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* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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*
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* The above named program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* The above named program is distributed in the hope that it will be
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* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public
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* License along with this work; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* ========== Copyright Header End ============================================
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*/
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// -*- verilog -*-
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////////////////////////////////////////////////////////////////////////
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/*
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//
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// Description: Global header file that contain definitions that
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// are common/shared at the systme level
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*/
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////////////////////////////////////////////////////////////////////////
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//
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// Setting the time scale
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// If the timescale changes, JP_TIMESCALE may also have to change.
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`timescale 1ps/1ps
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//
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// JBUS clock
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// =========
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//
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// Afara Link Defines
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// ==================
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// Reliable Link
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// Afara Link Objects
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// Afara Link Object Format - Reliable Link
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// Afara Link Object Format - Congestion
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// Afara Link Object Format - Acknowledge
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// Afara Link Object Format - Request
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// Afara Link Object Format - Message
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// Acknowledge Types
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// Request Types
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// Afara Link Frame
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//
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// UCB Packet Type
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// ===============
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//
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//
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// UCB Data Packet Format
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// ======================
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//
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// Size encoding for the UCB_SIZE_HI/LO field
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// 000 - byte
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// 001 - half-word
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// 010 - word
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// 011 - double-word
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// 111 - quad-word
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//
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// UCB Interrupt Packet Format
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// ===========================
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//
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//`define UCB_THR_HI 9 // (6) cpu/thread ID shared with
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//`define UCB_THR_LO 4 data packet format
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//`define UCB_PKT_HI 3 // (4) packet type shared with
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//`define UCB_PKT_LO 0 // data packet format
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//
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// FCRAM Bus Widths
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// ================
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//
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//
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// ENET clock periods
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// ==================
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//
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//
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// JBus Bridge defines
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// =================
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//
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//
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// PCI Device Address Configuration
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// ================================
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//
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// time scale definition
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// time scale definition
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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// Local header file includes / local defines
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// Local header file includes / local defines
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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module lsu_pcx_qmon (/*AUTOARG*/
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module lsu_pcx_qmon (/*AUTOARG*/
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// Outputs
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// Outputs
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so, qwrite, sel_qentry0,
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so, qwrite, sel_qentry0,
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// Inputs
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// Inputs
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rclk, grst_l, arst_l, si, se, send_by_pcx, send_to_pcx
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rclk, grst_l, arst_l, si, se, send_by_pcx, send_to_pcx
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) ;
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) ;
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input rclk ;
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input rclk ;
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input grst_l;
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input grst_l;
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input arst_l;
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input arst_l;
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input si;
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input si;
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input se;
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input se;
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output so;
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output so;
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input send_by_pcx ; // PCX sends packet to dest.
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input send_by_pcx ; // PCX sends packet to dest.
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input send_to_pcx ; // SKB sends packet to PCX.
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input send_to_pcx ; // SKB sends packet to PCX.
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output qwrite ; // PCX queue is writable.
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output qwrite ; // PCX queue is writable.
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output sel_qentry0 ; // entry to be written.
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output sel_qentry0 ; // entry to be written.
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wire clk;
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wire clk;
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wire reset ,dbb_reset_l ;
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wire reset ,dbb_reset_l ;
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wire entry0_rst, entry1_rst ;
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wire entry0_rst, entry1_rst ;
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wire entry0_en, entry1_en ;
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wire entry0_en, entry1_en ;
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wire entry0_din, entry1_din ;
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wire entry0_din, entry1_din ;
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wire entry0_full,entry1_full;
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wire entry0_full,entry1_full;
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dffrl_async rstff(.din (grst_l),
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dffrl_async rstff(.din (grst_l),
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.q (dbb_reset_l),
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.q (dbb_reset_l),
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.clk (clk), .se(se), .si(), .so(),
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.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so(),
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.rst_l (arst_l));
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.rst_l (arst_l));
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assign reset = ~dbb_reset_l;
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assign reset = ~dbb_reset_l;
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assign clk = rclk;
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assign clk = rclk;
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//======================================================================================
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//======================================================================================
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//
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//
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// Queue Monitor
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// Queue Monitor
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//
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//
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//======================================================================================
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//======================================================================================
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//
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//
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// Pipeline :
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// Pipeline :
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//--------------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------------
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//
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//
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// | req to pcx | payload to pcx| | |
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// | req to pcx | payload to pcx| | |
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// | qfull=0 | arb/grant=1 | | |
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// | qfull=0 | arb/grant=1 | | |
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// | qentry=1 | | | |
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// | qentry=1 | | | |
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// | | | | |
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// | | | | |
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// | | req to pcx | payload to pcx| |
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// | | req to pcx | payload to pcx| |
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// | | qfull=0 | arb/grant=0 | |
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// | | qfull=0 | arb/grant=0 | |
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// | | qentry=2 | | |
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// | | qentry=2 | | |
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// | | | req to pcx | payload to pcx|
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// | | | req to pcx | payload to pcx|
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// | | | qfull=0 | arb/grant |
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// | | | qfull=0 | arb/grant |
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//
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//
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//
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//
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// OPERATION :
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// OPERATION :
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// Monitors state per 2 input queue of pcx for given processor.
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// Monitors state per 2 input queue of pcx for given processor.
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// - Implemented as FIFO.
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// - Implemented as FIFO.
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// - The queue is cleared on reset.
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// - The queue is cleared on reset.
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// - A packet sent from the core to pcx will set a bit in the
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// - A packet sent from the core to pcx will set a bit in the
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// corresponding logical queue entry.
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// corresponding logical queue entry.
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// - A packet sent from pcx to dest, will cause entry0 to be cleared.
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// - A packet sent from pcx to dest, will cause entry0 to be cleared.
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// Only entry0 need be cleared as entry1 will shift to entry0 on
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// Only entry0 need be cleared as entry1 will shift to entry0 on
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// a grant by the pcx.
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// a grant by the pcx.
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// - The queue will never overflow as a packet will never be sent
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// - The queue will never overflow as a packet will never be sent
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// from the skb to the pcx unless at least one queue entry is free.
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// from the skb to the pcx unless at least one queue entry is free.
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// Timing : May have to flop grant and then use it.
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// Timing : May have to flop grant and then use it.
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assign entry0_rst = reset |
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assign entry0_rst = reset |
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(send_by_pcx & ~entry0_en) ; // pcx sends to dest.
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(send_by_pcx & ~entry0_en) ; // pcx sends to dest.
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assign entry0_en = ( entry1_full & send_by_pcx) | // shift entry1 to entry0
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assign entry0_en = ( entry1_full & send_by_pcx) | // shift entry1 to entry0
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(~(entry0_full & ~send_by_pcx) & send_to_pcx) ;
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(~(entry0_full & ~send_by_pcx) & send_to_pcx) ;
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assign entry0_din = entry0_en ;
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assign entry0_din = entry0_en ;
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// represents oldest packet.
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// represents oldest packet.
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dffre qstate_entry0 (
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dffre_s qstate_entry0 (
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.din (entry0_din), .q (entry0_full),
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.din (entry0_din), .q (entry0_full),
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.rst (entry0_rst), .en (entry0_en), .clk (clk),
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.rst (entry0_rst), .en (entry0_en), .clk (clk),
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.se (1'b0), .si (), .so ()
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.se (1'b0), `SIMPLY_RISC_SCANIN, .so ()
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);
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);
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assign entry1_rst = reset |
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assign entry1_rst = reset |
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(send_by_pcx & ~entry1_en) ;
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(send_by_pcx & ~entry1_en) ;
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assign entry1_en = entry0_full & send_to_pcx
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assign entry1_en = entry0_full & send_to_pcx
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& ~(send_by_pcx & ~entry1_full) ; // new packet to entry1
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& ~(send_by_pcx & ~entry1_full) ; // new packet to entry1
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assign entry1_din = entry1_en ;
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assign entry1_din = entry1_en ;
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// represents youngest packet.
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// represents youngest packet.
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dffre qstate_entry1 (
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dffre_s qstate_entry1 (
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.din (entry1_din), .q (entry1_full),
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.din (entry1_din), .q (entry1_full),
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.rst (entry1_rst), .en (entry1_en), .clk (clk),
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.rst (entry1_rst), .en (entry1_en), .clk (clk),
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.se (1'b0), .si (), .so ()
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.se (1'b0), `SIMPLY_RISC_SCANIN, .so ()
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);
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);
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assign qwrite = ~entry1_full ;
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assign qwrite = ~entry1_full ;
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//(entry1_full & send_by_pcx) ; // look at top of stack only.
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//(entry1_full & send_by_pcx) ; // look at top of stack only.
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assign sel_qentry0 =
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assign sel_qentry0 =
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(~entry0_full & ~send_to_pcx) ;
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(~entry0_full & ~send_to_pcx) ;
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//(~entry0_full |
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//(~entry0_full |
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//(~entry1_full & entry0_full & send_by_pcx)) & ~send_to_pcx ;
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//(~entry1_full & entry0_full & send_by_pcx)) & ~send_to_pcx ;
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// select which entry to write.
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// select which entry to write.
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endmodule
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endmodule
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