// ========== Copyright Header Begin ==========================================
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// ========== Copyright Header Begin ==========================================
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//
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//
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// OpenSPARC T1 Processor File: lsu_tlbdp.v
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// OpenSPARC T1 Processor File: lsu_tlbdp.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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//
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// The above named program is free software; you can redistribute it and/or
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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// License version 2 as published by the Free Software Foundation.
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//
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//
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// The above named program is distributed in the hope that it will be
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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// General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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`ifdef SIMPLY_RISC_TWEAKS
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`define SIMPLY_RISC_SCANIN .si(0)
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`else
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`define SIMPLY_RISC_SCANIN .si()
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`endif
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/*
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`include "lsu.h"
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/* ========== Copyright Header Begin ==========================================
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*
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* OpenSPARC T1 Processor File: lsu.h
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* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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*
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* The above named program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* The above named program is distributed in the hope that it will be
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* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public
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* License along with this work; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* ========== Copyright Header End ============================================
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*/
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//`define STB_PCX_WY_HI 107
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//`define STB_PCX_WY_LO 106
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// TLB Tag and Data Format
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// I-TLB version - lsu_tlb only.
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// Invalidate Format
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//addr<5:4>=00
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//addr<5:4>=01
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//addr<5:4>=10
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//addr<5:4>=11
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// cpuid - 4b
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// CPUany, addr<5:4>=00,10
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// CPUany, addr<5:4>=01,11
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// CPUany, addr<5:4>=01,11
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// DTAG parity error Invalidate
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// CPX BINIT STORE
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module lsu_tlbdp(/*AUTOARG*/
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module lsu_tlbdp(/*AUTOARG*/
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// Outputs
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// Outputs
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so, lsu_tlb_rd_data, tlb_pgnum_buf, tlb_pgnum_buf2,
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so, lsu_tlb_rd_data, tlb_pgnum_buf, tlb_pgnum_buf2,
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tlb_rd_tte_data_ie_buf, stb_cam_vld, tte_data_parity_error,
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tlb_rd_tte_data_ie_buf, stb_cam_vld, tte_data_parity_error,
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tte_tag_parity_error, cache_way_hit_buf1, cache_way_hit_buf2,
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tte_tag_parity_error, cache_way_hit_buf1, cache_way_hit_buf2,
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lsu_tlu_tte_pg_sz_g,
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lsu_tlu_tte_pg_sz_g,
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// Inputs
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// Inputs
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rclk, si, se, tlb_rd_tte_tag, tlb_rd_tte_data,
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rclk, si, se, tlb_rd_tte_tag, tlb_rd_tte_data,
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lsu_tlb_data_rd_vld_g, tlb_pgnum, asi_internal_m, lsu_alt_space_m,
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lsu_tlb_data_rd_vld_g, tlb_pgnum, asi_internal_m, lsu_alt_space_m,
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tlb_cam_hit, ifu_lsu_ld_inst_e, lsu_dtlb_bypass_e,
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tlb_cam_hit, ifu_lsu_ld_inst_e, lsu_dtlb_bypass_e,
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tlb_rd_tte_data_parity, tlb_rd_tte_tag_parity, cache_way_hit
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tlb_rd_tte_data_parity, tlb_rd_tte_tag_parity, cache_way_hit
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);
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);
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input rclk;
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input rclk;
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input si;
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input si;
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input se;
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input se;
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output so;
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output so;
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input [58:0] tlb_rd_tte_tag ; // tte tag from tlb
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input [58:0] tlb_rd_tte_tag ; // tte tag from tlb
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input [42:0] tlb_rd_tte_data ; // tte data from tlb
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input [42:0] tlb_rd_tte_data ; // tte data from tlb
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input lsu_tlb_data_rd_vld_g ; // select between tte tag/data rd.
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input lsu_tlb_data_rd_vld_g ; // select between tte tag/data rd.
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input [39:10] tlb_pgnum;
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input [39:10] tlb_pgnum;
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input asi_internal_m;
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input asi_internal_m;
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input lsu_alt_space_m;
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input lsu_alt_space_m;
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// **new**
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// **new**
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output [63:0] lsu_tlb_rd_data ; // tag or data rd from tlb
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output [63:0] lsu_tlb_rd_data ; // tag or data rd from tlb
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output [39:10] tlb_pgnum_buf;
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output [39:10] tlb_pgnum_buf;
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output [39:37] tlb_pgnum_buf2;
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output [39:37] tlb_pgnum_buf2;
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// output [42:0] tlb_rd_tte_data_buf;
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// output [42:0] tlb_rd_tte_data_buf;
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output tlb_rd_tte_data_ie_buf;
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output tlb_rd_tte_data_ie_buf;
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//======================================================
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//======================================================
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//stb cam vld mved from stb_rwctl
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//stb cam vld mved from stb_rwctl
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input tlb_cam_hit ;
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input tlb_cam_hit ;
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input ifu_lsu_ld_inst_e;
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input ifu_lsu_ld_inst_e;
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input lsu_dtlb_bypass_e;
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input lsu_dtlb_bypass_e;
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output stb_cam_vld;
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output stb_cam_vld;
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input tlb_rd_tte_data_parity ; // data parity bit from tte data
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input tlb_rd_tte_data_parity ; // data parity bit from tte data
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input tlb_rd_tte_tag_parity ; // data parity bit from tte tag
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input tlb_rd_tte_tag_parity ; // data parity bit from tte tag
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output tte_data_parity_error ;
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output tte_data_parity_error ;
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output tte_tag_parity_error ;
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output tte_tag_parity_error ;
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input [3:0] cache_way_hit;
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input [3:0] cache_way_hit;
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output [3:0] cache_way_hit_buf1;
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output [3:0] cache_way_hit_buf1;
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output [3:0] cache_way_hit_buf2;
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output [3:0] cache_way_hit_buf2;
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output [2:0] lsu_tlu_tte_pg_sz_g ; // page-size of tte
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output [2:0] lsu_tlu_tte_pg_sz_g ; // page-size of tte
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wire tlb_rd_tte_data_27_22_sel_buf;
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wire tlb_rd_tte_data_27_22_sel_buf;
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wire tlb_rd_tte_data_21_16_sel_buf;
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wire tlb_rd_tte_data_21_16_sel_buf;
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wire tlb_rd_tte_data_15_13_sel_buf;
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wire tlb_rd_tte_data_15_13_sel_buf;
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wire lsu_tte_pg_sz_b2, lsu_tte_pg_sz_b1, lsu_tte_pg_sz_b0;
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wire lsu_tte_pg_sz_b2, lsu_tte_pg_sz_b1, lsu_tte_pg_sz_b0;
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wire pg_sz_b0, pg_sz_b1, pg_sz_b2;
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wire pg_sz_b0, pg_sz_b1, pg_sz_b2;
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`ifdef SIMPLY_RISC_TWEAKS
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wire ld_inst_vld_m;
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`endif
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//===============================================================
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//===============================================================
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wire tlb_tte_data_mx_sel2, tlb_tte_data_mx_sel1, tlb_tte_data_mx_sel0;
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wire tlb_tte_data_mx_sel2, tlb_tte_data_mx_sel1, tlb_tte_data_mx_sel0;
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//tlb_tte_data_mx_sel2 ; // select for bits 21-19
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//tlb_tte_data_mx_sel2 ; // select for bits 21-19
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//tlb_tte_data_mx_sel1 ; // select for bits 18-16
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//tlb_tte_data_mx_sel1 ; // select for bits 18-16
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//tlb_tte_data_mx_sel0 ; // select for bits 15-13
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//tlb_tte_data_mx_sel0 ; // select for bits 15-13
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assign tlb_tte_data_mx_sel2 = tlb_rd_tte_data_27_22_sel_buf;
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assign tlb_tte_data_mx_sel2 = tlb_rd_tte_data_27_22_sel_buf;
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assign tlb_tte_data_mx_sel1 = tlb_rd_tte_data_21_16_sel_buf;
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assign tlb_tte_data_mx_sel1 = tlb_rd_tte_data_21_16_sel_buf;
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assign tlb_tte_data_mx_sel0 = tlb_rd_tte_data_15_13_sel_buf;
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assign tlb_tte_data_mx_sel0 = tlb_rd_tte_data_15_13_sel_buf;
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// assign pg_sz_b0 =
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// assign pg_sz_b0 =
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// (~tlb_tte_data_mx_sel1 & tlb_tte_data_mx_sel0) | // 64K
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// (~tlb_tte_data_mx_sel1 & tlb_tte_data_mx_sel0) | // 64K
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// ( tlb_tte_data_mx_sel1 & tlb_tte_data_mx_sel0) ; // 4M/256M
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// ( tlb_tte_data_mx_sel1 & tlb_tte_data_mx_sel0) ; // 4M/256M
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assign pg_sz_b0 = tlb_tte_data_mx_sel0;
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assign pg_sz_b0 = tlb_tte_data_mx_sel0;
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assign pg_sz_b1 =
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assign pg_sz_b1 =
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(~tlb_tte_data_mx_sel2 & tlb_tte_data_mx_sel1 & tlb_tte_data_mx_sel0) ; // 4M
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(~tlb_tte_data_mx_sel2 & tlb_tte_data_mx_sel1 & tlb_tte_data_mx_sel0) ; // 4M
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assign pg_sz_b2 =
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assign pg_sz_b2 =
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( tlb_tte_data_mx_sel2 & tlb_tte_data_mx_sel1 & tlb_tte_data_mx_sel0) ; // 256M
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( tlb_tte_data_mx_sel2 & tlb_tte_data_mx_sel1 & tlb_tte_data_mx_sel0) ; // 256M
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assign lsu_tte_pg_sz_b2 = pg_sz_b2 ;
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assign lsu_tte_pg_sz_b2 = pg_sz_b2 ;
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assign lsu_tte_pg_sz_b1 = pg_sz_b1 ;
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assign lsu_tte_pg_sz_b1 = pg_sz_b1 ;
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assign lsu_tte_pg_sz_b0 = pg_sz_b0 ;
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assign lsu_tte_pg_sz_b0 = pg_sz_b0 ;
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assign lsu_tlu_tte_pg_sz_g[2:0] = {pg_sz_b2,pg_sz_b1,pg_sz_b0} ;
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assign lsu_tlu_tte_pg_sz_g[2:0] = {pg_sz_b2,pg_sz_b1,pg_sz_b0} ;
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// CAM VLD GENERATION
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// CAM VLD GENERATION
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// Unfortunately because of timing considerations, this cannot be qualified with
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// Unfortunately because of timing considerations, this cannot be qualified with
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// flush and inst_vld. Must exclude other conditions though such as internal asi
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// flush and inst_vld. Must exclude other conditions though such as internal asi
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// atomics etc !!! (NOTE : earlier version of inst_vld may be obtained.
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// atomics etc !!! (NOTE : earlier version of inst_vld may be obtained.
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wire clk;
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wire clk;
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assign clk =rclk;
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assign clk =rclk;
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wire dtlb_bypass_m ;
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wire dtlb_bypass_m ;
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dff #(1) dtlb_bypass_stgm (
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dff_s #(1) dtlb_bypass_stgm (
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.din (lsu_dtlb_bypass_e), .q (dtlb_bypass_m),
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.din (lsu_dtlb_bypass_e), .q (dtlb_bypass_m),
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.clk (clk),
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.clk (clk),
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.se (se), .si (), .so ()
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.se (se), `SIMPLY_RISC_SCANIN, .so ()
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);
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);
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dff #(1) ld_inst_vld_stgm (
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dff_s #(1) ld_inst_vld_stgm (
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.din (ifu_lsu_ld_inst_e), .q (ld_inst_vld_m),
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.din (ifu_lsu_ld_inst_e), .q (ld_inst_vld_m),
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.clk (clk),
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.clk (clk),
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.se (se), .si (), .so ()
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.se (se), `SIMPLY_RISC_SCANIN, .so ()
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);
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);
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assign stb_cam_vld = ld_inst_vld_m & (tlb_cam_hit | dtlb_bypass_m) &
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assign stb_cam_vld = ld_inst_vld_m & (tlb_cam_hit | dtlb_bypass_m) &
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~(asi_internal_m & lsu_alt_space_m); //bug 4635, revisit
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~(asi_internal_m & lsu_alt_space_m); //bug 4635, revisit
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//======================================================================
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//======================================================================
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//buffer all inputs first
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//buffer all inputs first
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wire [58:0] tlb_rd_tte_tag_buf ;
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wire [58:0] tlb_rd_tte_tag_buf ;
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wire [42:0] tlb_rd_tte_data_buf ;
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wire [42:0] tlb_rd_tte_data_buf ;
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wire lsu_tte_pg_sz_b1_buf;
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wire lsu_tte_pg_sz_b1_buf;
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wire lsu_tte_pg_sz_b0_buf;
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wire lsu_tte_pg_sz_b0_buf;
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wire lsu_tte_pg_sz_b2_buf;
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wire lsu_tte_pg_sz_b2_buf;
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wire [39:10] tlb_pgnum_l;
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wire [39:10] tlb_pgnum_l;
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wire [39:10] tlb_pgnum_buf;
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wire [39:10] tlb_pgnum_buf;
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wire [39:37] tlb_pgnum_buf2;
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wire [39:37] tlb_pgnum_buf2;
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//BUFFERS
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//BUFFERS
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assign tlb_rd_tte_tag_buf[58:0] = tlb_rd_tte_tag[58:0];
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assign tlb_rd_tte_tag_buf[58:0] = tlb_rd_tte_tag[58:0];
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assign lsu_tte_pg_sz_b1_buf = lsu_tte_pg_sz_b1;
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assign lsu_tte_pg_sz_b1_buf = lsu_tte_pg_sz_b1;
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assign lsu_tte_pg_sz_b0_buf = lsu_tte_pg_sz_b0;
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assign lsu_tte_pg_sz_b0_buf = lsu_tte_pg_sz_b0;
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assign lsu_tte_pg_sz_b2_buf = lsu_tte_pg_sz_b2;
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assign lsu_tte_pg_sz_b2_buf = lsu_tte_pg_sz_b2;
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//tlb_pgnum buffer
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//tlb_pgnum buffer
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assign tlb_pgnum_l [39:10] = ~ tlb_pgnum[39:10];
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assign tlb_pgnum_l [39:10] = ~ tlb_pgnum[39:10];
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assign tlb_pgnum_buf[39:10] = ~ tlb_pgnum_l[39:10];
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assign tlb_pgnum_buf[39:10] = ~ tlb_pgnum_l[39:10];
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assign tlb_pgnum_buf2[39:37] = ~ tlb_pgnum_l[39:37];
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assign tlb_pgnum_buf2[39:37] = ~ tlb_pgnum_l[39:37];
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assign tlb_rd_tte_data_buf[42:0] = tlb_rd_tte_data[42:0];
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assign tlb_rd_tte_data_buf[42:0] = tlb_rd_tte_data[42:0];
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assign tlb_rd_tte_data_ie_buf = tlb_rd_tte_data_buf [9];
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assign tlb_rd_tte_data_ie_buf = tlb_rd_tte_data_buf [`STLB_DATA_IE];
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assign tlb_rd_tte_data_27_22_sel_buf = tlb_rd_tte_data_buf [23];
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assign tlb_rd_tte_data_27_22_sel_buf = tlb_rd_tte_data_buf [`STLB_DATA_27_22_SEL];
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assign tlb_rd_tte_data_21_16_sel_buf = tlb_rd_tte_data_buf [16];
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assign tlb_rd_tte_data_21_16_sel_buf = tlb_rd_tte_data_buf [`STLB_DATA_21_16_SEL];
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assign tlb_rd_tte_data_15_13_sel_buf = tlb_rd_tte_data_buf [12];
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assign tlb_rd_tte_data_15_13_sel_buf = tlb_rd_tte_data_buf [`STLB_DATA_15_13_SEL];
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wire [63:0] formatted_tte_tag, formatted_tte_data;
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wire [63:0] formatted_tte_tag, formatted_tte_data;
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//=================================================================================================
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//=================================================================================================
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// Format TLB Tag
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// Format TLB Tag
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//=================================================================================================
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//=================================================================================================
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|
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assign formatted_tte_tag[63:0] =
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assign formatted_tte_tag[63:0] =
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{
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{
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tlb_rd_tte_tag_buf[58:56],
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tlb_rd_tte_tag_buf[58:56],
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tlb_rd_tte_tag_buf[55],
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tlb_rd_tte_tag_buf[55],
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// ECO 4265 begin
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// ECO 4265 begin
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tlb_rd_tte_tag_buf[54], // Parity
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tlb_rd_tte_tag_buf[`STLB_TAG_PARITY], // Parity
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tlb_rd_tte_tag_buf[27], // mxsel2 - b27:22 vld
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tlb_rd_tte_tag_buf[`STLB_TAG_VA_27_22_V], // mxsel2 - b27:22 vld
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tlb_rd_tte_tag_buf[17], // mxsel1 - b21:16 vld
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tlb_rd_tte_tag_buf[`STLB_TAG_VA_21_16_V], // mxsel1 - b21:16 vld
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tlb_rd_tte_tag_buf[13], // mxsel0 - b15:13 vld
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tlb_rd_tte_tag_buf[`STLB_TAG_VA_15_13_V], // mxsel0 - b15:13 vld
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{8{tlb_rd_tte_tag_buf[53]}}, // (8b)
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{8{tlb_rd_tte_tag_buf[53]}}, // (8b)
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// ECO 4265 end
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// ECO 4265 end
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tlb_rd_tte_tag_buf[53:34], // (20b)
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tlb_rd_tte_tag_buf[`STLB_TAG_VA_47_28_HI:`STLB_TAG_VA_47_28_LO], // (20b)
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tlb_rd_tte_tag_buf[33:28], // (6b)
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tlb_rd_tte_tag_buf[`STLB_TAG_VA_27_22_HI:`STLB_TAG_VA_27_22_LO], // (6b)
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tlb_rd_tte_tag_buf[23:18], // (6b)
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tlb_rd_tte_tag_buf[`STLB_TAG_VA_21_16_HI:`STLB_TAG_VA_21_16_LO], // (6b)
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tlb_rd_tte_tag_buf[16:14], // (3b)
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tlb_rd_tte_tag_buf[`STLB_TAG_VA_15_13_HI:`STLB_TAG_VA_15_13_LO], // (3b)
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tlb_rd_tte_tag_buf[12:0] // (13b)
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tlb_rd_tte_tag_buf[`STLB_TAG_CTXT_12_0_HI:`STLB_TAG_CTXT_12_0_LO] // (13b)
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} ;
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} ;
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/*
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/*
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assign formatted_tte_tag[63:0] =
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assign formatted_tte_tag[63:0] =
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{
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{
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{16{tlb_rd_tte_tag_buf[54]}}, // (16b)
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{16{tlb_rd_tte_tag_buf[54]}}, // (16b)
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tlb_rd_tte_tag_buf[`STLB_TAG_VA_47_22_HI:`STLB_TAG_VA_47_22_LO], // (26b)
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tlb_rd_tte_tag_buf[`STLB_TAG_VA_47_22_HI:`STLB_TAG_VA_47_22_LO], // (26b)
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tlb_rd_tte_tag_buf[`STLB_TAG_VA_21_20_HI:`STLB_TAG_VA_21_20_LO], // (3b)
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tlb_rd_tte_tag_buf[`STLB_TAG_VA_21_20_HI:`STLB_TAG_VA_21_20_LO], // (3b)
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tlb_rd_tte_tag_buf[`STLB_TAG_VA_19],
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tlb_rd_tte_tag_buf[`STLB_TAG_VA_19],
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tlb_rd_tte_tag_buf[`STLB_TAG_VA_18_17_HI:`STLB_TAG_VA_18_17_LO], // (3b)
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tlb_rd_tte_tag_buf[`STLB_TAG_VA_18_17_HI:`STLB_TAG_VA_18_17_LO], // (3b)
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tlb_rd_tte_tag_buf[`STLB_TAG_VA_16],
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tlb_rd_tte_tag_buf[`STLB_TAG_VA_16],
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tlb_rd_tte_tag_buf[`STLB_TAG_VA_15_14_HI:`STLB_TAG_VA_15_14_LO], // (3b)
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tlb_rd_tte_tag_buf[`STLB_TAG_VA_15_14_HI:`STLB_TAG_VA_15_14_LO], // (3b)
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tlb_rd_tte_tag_buf[`STLB_TAG_VA_13],
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tlb_rd_tte_tag_buf[`STLB_TAG_VA_13],
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tlb_rd_tte_tag_buf[`STLB_TAG_CTXT_12_7_HI:`STLB_TAG_CTXT_12_7_LO], // (13b)
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tlb_rd_tte_tag_buf[`STLB_TAG_CTXT_12_7_HI:`STLB_TAG_CTXT_12_7_LO], // (13b)
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tlb_rd_tte_tag_buf[`STLB_TAG_CTXT_6_0_HI:`STLB_TAG_CTXT_6_0_LO]
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tlb_rd_tte_tag_buf[`STLB_TAG_CTXT_6_0_HI:`STLB_TAG_CTXT_6_0_LO]
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} ;
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} ;
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*/
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*/
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//=================================================================================================
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//=================================================================================================
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// Format TLB Data
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// Format TLB Data
|
//=================================================================================================
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//=================================================================================================
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|
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assign formatted_tte_data[63:0] =
|
assign formatted_tte_data[63:0] =
|
{
|
{
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tlb_rd_tte_tag_buf[26], // V (1b)
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tlb_rd_tte_tag_buf[`STLB_TAG_V], // V (1b)
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lsu_tte_pg_sz_b1_buf, // SZ (2b)
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lsu_tte_pg_sz_b1_buf, // SZ (2b)
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lsu_tte_pg_sz_b0_buf,
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lsu_tte_pg_sz_b0_buf,
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tlb_rd_tte_data_buf[10], // NFO (1b)
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tlb_rd_tte_data_buf[`STLB_DATA_NFO], // NFO (1b)
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tlb_rd_tte_data_buf[9], // IE (1b)
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tlb_rd_tte_data_buf[`STLB_DATA_IE], // IE (1b)
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9'd0, // Soft2
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9'd0, // Soft2
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1'b0,
|
1'b0,
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lsu_tte_pg_sz_b2_buf, // SZ (1b)
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lsu_tte_pg_sz_b2_buf, // SZ (1b)
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tlb_rd_tte_tag_buf[24], // U (1b)
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tlb_rd_tte_tag_buf[`STLB_TAG_U], // U (1b)
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// ECO 4265 - begin
|
// ECO 4265 - begin
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tlb_rd_tte_data_buf[42], // Parity (1b)
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tlb_rd_tte_data_buf[`STLB_DATA_PARITY], // Parity (1b)
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tlb_rd_tte_data_buf[23], // mxsel2_l (1b)
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tlb_rd_tte_data_buf[`STLB_DATA_27_22_SEL], // mxsel2_l (1b)
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tlb_rd_tte_data_buf[16], // mxsel1_l (1b)
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tlb_rd_tte_data_buf[`STLB_DATA_21_16_SEL], // mxsel1_l (1b)
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tlb_rd_tte_data_buf[12], // mxsel0_l (1b)
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tlb_rd_tte_data_buf[`STLB_DATA_15_13_SEL], // mxsel0_l (1b)
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2'd0, // Unused Diag bits
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2'd0, // Unused Diag bits
|
// ECO 4265 - end
|
// ECO 4265 - end
|
1'b0, // PA (28b)
|
1'b0, // PA (28b)
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tlb_rd_tte_data_buf[41:30],
|
tlb_rd_tte_data_buf[`STLB_DATA_PA_39_28_HI:`STLB_DATA_PA_39_28_LO],
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tlb_rd_tte_data_buf[29:24],
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tlb_rd_tte_data_buf[`STLB_DATA_PA_27_22_HI:`STLB_DATA_PA_27_22_LO],
|
tlb_rd_tte_data_buf[22:17],
|
tlb_rd_tte_data_buf[`STLB_DATA_PA_21_16_HI:`STLB_DATA_PA_21_16_LO],
|
tlb_rd_tte_data_buf[15:13],
|
tlb_rd_tte_data_buf[`STLB_DATA_PA_15_13_HI:`STLB_DATA_PA_15_13_LO],
|
6'd0, // ?? 12-7 (6b)
|
6'd0, // ?? 12-7 (6b)
|
tlb_rd_tte_data_buf[8], // L (1b)
|
tlb_rd_tte_data_buf[`STLB_DATA_L], // L (1b)
|
tlb_rd_tte_data_buf[7], // CP (1b)
|
tlb_rd_tte_data_buf[`STLB_DATA_CP], // CP (1b)
|
tlb_rd_tte_data_buf[6], // CV (1b)
|
tlb_rd_tte_data_buf[`STLB_DATA_CV], // CV (1b)
|
tlb_rd_tte_data_buf[5], // E (1b)
|
tlb_rd_tte_data_buf[`STLB_DATA_E], // E (1b)
|
tlb_rd_tte_data_buf[4], // P (1b)
|
tlb_rd_tte_data_buf[`STLB_DATA_P], // P (1b)
|
tlb_rd_tte_data_buf[3], // W (1b)
|
tlb_rd_tte_data_buf[`STLB_DATA_W], // W (1b)
|
1'b0
|
1'b0
|
} ;
|
} ;
|
|
|
|
|
//=================================================================================================
|
//=================================================================================================
|
// Select TLB Read data / TLB Read tag
|
// Select TLB Read data / TLB Read tag
|
//=================================================================================================
|
//=================================================================================================
|
|
|
assign lsu_tlb_rd_data[63:0] =
|
assign lsu_tlb_rd_data[63:0] =
|
lsu_tlb_data_rd_vld_g ? formatted_tte_data[63:0] : formatted_tte_tag[63:0];
|
lsu_tlb_data_rd_vld_g ? formatted_tte_data[63:0] : formatted_tte_tag[63:0];
|
|
|
|
|
//=================================================================================================
|
//=================================================================================================
|
// Calculate parity for TLB Tag and Data
|
// Calculate parity for TLB Tag and Data
|
//=================================================================================================
|
//=================================================================================================
|
wire lsu_rd_tte_data_parity, lsu_rd_tte_tag_parity;
|
wire lsu_rd_tte_data_parity, lsu_rd_tte_tag_parity;
|
|
|
assign lsu_rd_tte_data_parity = ^tlb_rd_tte_data_buf[41:0] ;
|
assign lsu_rd_tte_data_parity = ^tlb_rd_tte_data_buf[41:0] ;
|
assign lsu_rd_tte_tag_parity = ^{tlb_rd_tte_tag_buf[58:55],tlb_rd_tte_tag_buf[53:27],
|
assign lsu_rd_tte_tag_parity = ^{tlb_rd_tte_tag_buf[58:55],tlb_rd_tte_tag_buf[53:27],
|
tlb_rd_tte_tag_buf[25],tlb_rd_tte_tag_buf[23:0]} ;
|
tlb_rd_tte_tag_buf[25],tlb_rd_tte_tag_buf[23:0]} ;
|
|
|
assign tte_data_parity_error =
|
assign tte_data_parity_error =
|
tlb_rd_tte_data_parity ^ lsu_rd_tte_data_parity ;
|
tlb_rd_tte_data_parity ^ lsu_rd_tte_data_parity ;
|
assign tte_tag_parity_error =
|
assign tte_tag_parity_error =
|
tlb_rd_tte_tag_parity ^ lsu_rd_tte_tag_parity ;
|
tlb_rd_tte_tag_parity ^ lsu_rd_tte_tag_parity ;
|
|
|
assign cache_way_hit_buf1[3:0] = cache_way_hit[3:0] ;
|
assign cache_way_hit_buf1[3:0] = cache_way_hit[3:0] ;
|
assign cache_way_hit_buf2[3:0] = cache_way_hit[3:0];
|
assign cache_way_hit_buf2[3:0] = cache_way_hit[3:0];
|
|
|
|
|
endmodule
|
endmodule
|
|
|