// ========== Copyright Header Begin ==========================================
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// ========== Copyright Header Begin ==========================================
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//
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//
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// OpenSPARC T1 Processor File: sparc_exu_ecl_divcntl.v
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// OpenSPARC T1 Processor File: sparc_exu_ecl_divcntl.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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//
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// The above named program is free software; you can redistribute it and/or
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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// License version 2 as published by the Free Software Foundation.
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//
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//
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// The above named program is distributed in the hope that it will be
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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// General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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`ifdef SIMPLY_RISC_TWEAKS
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`define SIMPLY_RISC_SCANIN .si(0)
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`else
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`define SIMPLY_RISC_SCANIN .si()
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`endif
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/*
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/*
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// Module Name: sparc_exu_divcntl
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// Module Name: sparc_exu_divcntl
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// Description: Control block for div. Division takes 1 cycle to load
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// Description: Control block for div. Division takes 1 cycle to load
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// the values, 65 cycles to calculate the result, and 1 cycle to
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// the values, 65 cycles to calculate the result, and 1 cycle to
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// calculate the ccs and check for overflow.
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// calculate the ccs and check for overflow.
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// Controlled by a one hot state machine and a 6 bit counter.
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// Controlled by a one hot state machine and a 6 bit counter.
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*/
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*/
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`define IDLE 0
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`define RUN 1
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`define LAST_CALC 2
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`define CHK_OVFL 3
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`define FIX_OVFL 4
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`define DONE 5
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module sparc_exu_ecl_divcntl (/*AUTOARG*/
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module sparc_exu_ecl_divcntl (/*AUTOARG*/
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// Outputs
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// Outputs
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ecl_div_xinmask, ecl_div_keep_d, ecl_div_ld_inputs,
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ecl_div_xinmask, ecl_div_keep_d, ecl_div_ld_inputs,
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ecl_div_sel_adder, ecl_div_last_cycle, ecl_div_almostlast_cycle,
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ecl_div_sel_adder, ecl_div_last_cycle, ecl_div_almostlast_cycle,
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ecl_div_sel_div, divcntl_wb_req_g, divcntl_ccr_cc_w2,
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ecl_div_sel_div, divcntl_wb_req_g, divcntl_ccr_cc_w2,
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ecl_div_sel_64b, ecl_div_sel_u32, ecl_div_sel_pos32,
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ecl_div_sel_64b, ecl_div_sel_u32, ecl_div_sel_pos32,
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ecl_div_sel_neg32, ecl_div_upper32_zero, ecl_div_upper33_one,
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ecl_div_sel_neg32, ecl_div_upper32_zero, ecl_div_upper33_one,
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ecl_div_upper33_zero, ecl_div_dividend_sign, ecl_div_newq,
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ecl_div_upper33_zero, ecl_div_dividend_sign, ecl_div_newq,
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ecl_div_subtract_l, ecl_div_keepx, ecl_div_cin,
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ecl_div_subtract_l, ecl_div_keepx, ecl_div_cin,
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// Inputs
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// Inputs
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clk, se, reset, mdqctl_divcntl_input_vld, wb_divcntl_ack_g,
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clk, se, reset, mdqctl_divcntl_input_vld, wb_divcntl_ack_g,
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mdqctl_divcntl_reset_div, div_ecl_gencc_in_msb_l,
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mdqctl_divcntl_reset_div, div_ecl_gencc_in_msb_l,
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div_ecl_gencc_in_31, div_ecl_upper32_equal, div_ecl_low32_nonzero,
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div_ecl_gencc_in_31, div_ecl_upper32_equal, div_ecl_low32_nonzero,
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ecl_div_signed_div, div_ecl_dividend_msb, div_ecl_xin_msb_l,
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ecl_div_signed_div, div_ecl_dividend_msb, div_ecl_xin_msb_l,
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div_ecl_x_msb, div_ecl_d_msb, div_ecl_cout64,
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div_ecl_x_msb, div_ecl_d_msb, div_ecl_cout64,
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div_ecl_divisorin_31, ecl_div_div64, mdqctl_divcntl_muldone,
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div_ecl_divisorin_31, ecl_div_div64, mdqctl_divcntl_muldone,
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ecl_div_muls, div_ecl_adder_out_31, muls_rs1_31_m_l,
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ecl_div_muls, div_ecl_adder_out_31, muls_rs1_31_m_l,
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div_ecl_cout32, rs2_data_31_m, div_ecl_detect_zero_high,
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div_ecl_cout32, rs2_data_31_m, div_ecl_detect_zero_high,
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div_ecl_detect_zero_low, div_ecl_d_62
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div_ecl_detect_zero_low, div_ecl_d_62
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) ;
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) ;
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input clk;
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input clk;
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input se;
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input se;
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input reset;
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input reset;
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input mdqctl_divcntl_input_vld;
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input mdqctl_divcntl_input_vld;
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input wb_divcntl_ack_g;
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input wb_divcntl_ack_g;
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input mdqctl_divcntl_reset_div;
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input mdqctl_divcntl_reset_div;
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input div_ecl_gencc_in_msb_l;
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input div_ecl_gencc_in_msb_l;
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input div_ecl_gencc_in_31;
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input div_ecl_gencc_in_31;
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input div_ecl_upper32_equal;
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input div_ecl_upper32_equal;
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input div_ecl_low32_nonzero;
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input div_ecl_low32_nonzero;
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input ecl_div_signed_div;
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input ecl_div_signed_div;
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input div_ecl_dividend_msb;
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input div_ecl_dividend_msb;
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input div_ecl_xin_msb_l;
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input div_ecl_xin_msb_l;
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input div_ecl_x_msb;
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input div_ecl_x_msb;
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input div_ecl_d_msb;
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input div_ecl_d_msb;
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input div_ecl_cout64;
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input div_ecl_cout64;
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input div_ecl_divisorin_31;
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input div_ecl_divisorin_31;
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input ecl_div_div64;
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input ecl_div_div64;
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input mdqctl_divcntl_muldone;
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input mdqctl_divcntl_muldone;
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input ecl_div_muls;
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input ecl_div_muls;
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input div_ecl_adder_out_31;
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input div_ecl_adder_out_31;
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input muls_rs1_31_m_l;
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input muls_rs1_31_m_l;
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input div_ecl_cout32;
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input div_ecl_cout32;
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input rs2_data_31_m;
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input rs2_data_31_m;
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input div_ecl_detect_zero_high;
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input div_ecl_detect_zero_high;
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input div_ecl_detect_zero_low;
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input div_ecl_detect_zero_low;
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input div_ecl_d_62;
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input div_ecl_d_62;
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output ecl_div_xinmask;
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output ecl_div_xinmask;
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output ecl_div_keep_d;
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output ecl_div_keep_d;
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output ecl_div_ld_inputs;
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output ecl_div_ld_inputs;
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output ecl_div_sel_adder;
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output ecl_div_sel_adder;
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output ecl_div_last_cycle; // last cycle of calculation
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output ecl_div_last_cycle; // last cycle of calculation
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output ecl_div_almostlast_cycle;//
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output ecl_div_almostlast_cycle;//
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output ecl_div_sel_div;
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output ecl_div_sel_div;
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output divcntl_wb_req_g;
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output divcntl_wb_req_g;
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output [7:0] divcntl_ccr_cc_w2;
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output [7:0] divcntl_ccr_cc_w2;
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output ecl_div_sel_64b;
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output ecl_div_sel_64b;
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output ecl_div_sel_u32;
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output ecl_div_sel_u32;
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output ecl_div_sel_pos32;
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output ecl_div_sel_pos32;
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output ecl_div_sel_neg32;
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output ecl_div_sel_neg32;
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output ecl_div_upper32_zero;
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output ecl_div_upper32_zero;
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output ecl_div_upper33_one;
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output ecl_div_upper33_one;
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output ecl_div_upper33_zero;
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output ecl_div_upper33_zero;
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output ecl_div_dividend_sign;
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output ecl_div_dividend_sign;
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output ecl_div_newq;
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output ecl_div_newq;
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output ecl_div_subtract_l;
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output ecl_div_subtract_l;
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output ecl_div_keepx;
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output ecl_div_keepx;
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output ecl_div_cin;
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output ecl_div_cin;
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wire firstq;
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wire firstq;
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wire q_next; // next q bit
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wire q_next; // next q bit
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wire adderin1_64; // msbs for adder
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wire adderin1_64; // msbs for adder
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wire adderin2_64;
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wire adderin2_64;
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wire firstlast_sub; // subtract for first and last cycle
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wire firstlast_sub; // subtract for first and last cycle
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wire sub_next; // next cycle will subtract
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wire sub_next; // next cycle will subtract
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wire subtract;
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wire subtract;
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wire bit64_halfadd; // partial result for qpredict
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wire bit64_halfadd; // partial result for qpredict
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wire partial_qpredict;
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wire partial_qpredict;
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wire [1:0] q_next_nocout;
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wire [1:0] q_next_nocout;
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wire [1:0] sub_next_nocout;
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wire [1:0] sub_next_nocout;
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wire partial_qpredict_l;
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wire partial_qpredict_l;
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wire divisor_sign;
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wire divisor_sign;
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wire detect_zero;
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wire detect_zero;
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wire new_zero_rem_with_zero;
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wire new_zero_rem_with_zero;
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wire new_zero_rem_no_zero;
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wire new_zero_rem_no_zero;
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wire zero_rem_d;
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wire zero_rem_d;
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wire zero_rem_q;
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wire zero_rem_q;
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wire last_cin_with_zero;
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wire last_cin_with_zero;
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wire last_cin_no_zero;
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wire last_cin_no_zero;
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wire last_cin;
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wire last_cin;
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wire last_cin_next;
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wire last_cin_next;
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// overflow correction wires
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// overflow correction wires
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wire upper32_equal_d1;
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wire upper32_equal_d1;
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wire gencc_in_msb_l_d1;
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wire gencc_in_msb_l_d1;
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wire gencc_in_31_d1;
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wire gencc_in_31_d1;
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wire sel_div_d1;
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wire sel_div_d1;
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wire low32_nonzero_d1;
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wire low32_nonzero_d1;
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// Condition code generation wires
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// Condition code generation wires
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wire [3:0] xcc;
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wire [3:0] xcc;
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wire [3:0] icc;
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wire [3:0] icc;
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wire unsign_ovfl;
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wire unsign_ovfl;
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wire pos_ovfl;
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wire pos_ovfl;
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wire neg_ovfl;
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wire neg_ovfl;
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wire muls_c;
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wire muls_c;
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wire next_muls_c;
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wire next_muls_c;
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wire muls_v;
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wire muls_v;
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wire next_muls_v;
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wire next_muls_v;
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wire muls_rs1_data_31_m;
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wire muls_rs1_data_31_m;
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wire div_adder_out_31_w;
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wire div_adder_out_31_w;
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wire rs2_data_31_w;
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wire rs2_data_31_w;
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wire muls_rs1_data_31_w;
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wire muls_rs1_data_31_w;
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wire ovfl_32;
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wire ovfl_32;
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wire div_v;
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wire div_v;
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wire [5:0] div_state;
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wire [5:0] div_state;
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wire [5:0] next_state;
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wire [5:0] next_state;
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wire go_idle,
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wire go_idle,
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stay_idle,
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stay_idle,
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go_run,
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go_run,
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stay_run,
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stay_run,
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go_last_calc,
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go_last_calc,
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go_chk_ovfl,
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go_chk_ovfl,
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go_fix_ovfl,
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go_fix_ovfl,
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go_done,
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go_done,
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stay_done;
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stay_done;
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wire reset_cnt;
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wire reset_cnt;
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wire [5:0] cntr;
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wire [5:0] cntr;
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wire cntris63;
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wire cntris63;
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/////////////////////////////////
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/////////////////////////////////
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// G arbitration between MUL/DIV
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// G arbitration between MUL/DIV
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/////////////////////////////////
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/////////////////////////////////
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assign divcntl_wb_req_g = div_state[5] |
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assign divcntl_wb_req_g = div_state[`DONE] |
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(~(div_state[5] | div_state[3] | div_state[4]) &mdqctl_divcntl_muldone);
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(~(div_state[`DONE] | div_state[`CHK_OVFL] | div_state[`FIX_OVFL]) &mdqctl_divcntl_muldone);
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assign ecl_div_sel_div = ~(~(div_state[5] | div_state[3] | div_state[4]) &
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assign ecl_div_sel_div = ~(~(div_state[`DONE] | div_state[`CHK_OVFL] | div_state[`FIX_OVFL]) &
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mdqctl_divcntl_muldone);
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mdqctl_divcntl_muldone);
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// state flop
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// state flop
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dff #(6) divstate_dff(.din(next_state[5:0]), .clk(clk), .q(div_state[5:0]), .se(se), .si(),
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dff_s #(6) divstate_dff(.din(next_state[5:0]), .clk(clk), .q(div_state[5:0]), .se(se), `SIMPLY_RISC_SCANIN,
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.so());
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.so());
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// output logic and state decode
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// output logic and state decode
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assign ecl_div_almostlast_cycle = go_last_calc & ~ecl_div_ld_inputs;
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assign ecl_div_almostlast_cycle = go_last_calc & ~ecl_div_ld_inputs;
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assign ecl_div_sel_adder = (div_state[1] | div_state[2]) & ~ecl_div_ld_inputs;
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assign ecl_div_sel_adder = (div_state[`RUN] | div_state[`LAST_CALC]) & ~ecl_div_ld_inputs;
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assign ecl_div_last_cycle = div_state[2];
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assign ecl_div_last_cycle = div_state[`LAST_CALC];
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assign ecl_div_ld_inputs = mdqctl_divcntl_input_vld;
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assign ecl_div_ld_inputs = mdqctl_divcntl_input_vld;
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assign ecl_div_keep_d = ~(ecl_div_sel_adder | ecl_div_ld_inputs);
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assign ecl_div_keep_d = ~(ecl_div_sel_adder | ecl_div_ld_inputs);
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assign reset_cnt = ~div_state[1];
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assign reset_cnt = ~div_state[`RUN];
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// next state logic
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// next state logic
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assign stay_idle = div_state[0] & ~mdqctl_divcntl_input_vld;
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assign stay_idle = div_state[`IDLE] & ~mdqctl_divcntl_input_vld;
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assign go_idle = div_state[5] & wb_divcntl_ack_g;
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assign go_idle = div_state[`DONE] & wb_divcntl_ack_g;
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assign next_state[0] = go_idle | stay_idle | mdqctl_divcntl_reset_div | reset;
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assign next_state[`IDLE] = go_idle | stay_idle | mdqctl_divcntl_reset_div | reset;
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assign stay_run = div_state[1] & ~cntris63 & ~ecl_div_muls;
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assign stay_run = div_state[`RUN] & ~cntris63 & ~ecl_div_muls;
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assign go_run = (div_state[0] & mdqctl_divcntl_input_vld);
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assign go_run = (div_state[`IDLE] & mdqctl_divcntl_input_vld);
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assign next_state[1] = (go_run | stay_run) &
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assign next_state[`RUN] = (go_run | stay_run) &
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~mdqctl_divcntl_reset_div & ~reset;
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~mdqctl_divcntl_reset_div & ~reset;
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assign go_last_calc = div_state[1] & (cntris63);
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assign go_last_calc = div_state[`RUN] & (cntris63);
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assign next_state[2] = go_last_calc & ~mdqctl_divcntl_reset_div & ~reset;
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assign next_state[`LAST_CALC] = go_last_calc & ~mdqctl_divcntl_reset_div & ~reset;
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// chk_ovfl and fix_ovfl are place holders to guarantee that the overflow checking
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// chk_ovfl and fix_ovfl are place holders to guarantee that the overflow checking
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// takes place on the result. No special logic occurs in them compared to the done state.
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// takes place on the result. No special logic occurs in them compared to the done state.
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assign go_chk_ovfl = div_state[2];
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assign go_chk_ovfl = div_state[`LAST_CALC];
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assign next_state[3] = go_chk_ovfl & ~mdqctl_divcntl_reset_div & ~reset;
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assign next_state[`CHK_OVFL] = go_chk_ovfl & ~mdqctl_divcntl_reset_div & ~reset;
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assign go_fix_ovfl = div_state[3] | (div_state[1] & ecl_div_muls);
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assign go_fix_ovfl = div_state[`CHK_OVFL] | (div_state[`RUN] & ecl_div_muls);
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assign next_state[4] = go_fix_ovfl & ~mdqctl_divcntl_reset_div & ~reset;
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assign next_state[`FIX_OVFL] = go_fix_ovfl & ~mdqctl_divcntl_reset_div & ~reset;
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assign go_done = div_state[4];
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assign go_done = div_state[`FIX_OVFL];
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assign stay_done = div_state[5] & ~wb_divcntl_ack_g;
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assign stay_done = div_state[`DONE] & ~wb_divcntl_ack_g;
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assign next_state[5] = (go_done | stay_done) & ~mdqctl_divcntl_reset_div & ~reset;
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assign next_state[`DONE] = (go_done | stay_done) & ~mdqctl_divcntl_reset_div & ~reset;
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// counter
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// counter
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sparc_exu_ecl_cnt6 cnt6(.reset (reset_cnt),
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sparc_exu_ecl_cnt6 cnt6(.reset (reset_cnt),
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/*AUTOINST*/
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/*AUTOINST*/
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// Outputs
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// Outputs
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.cntr (cntr[5:0]),
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.cntr (cntr[5:0]),
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// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.se (se));
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.se (se));
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assign cntris63 = cntr[5] & cntr[4] & cntr[3] & cntr[2] & cntr[1] & cntr[0];
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assign cntris63 = cntr[5] & cntr[4] & cntr[3] & cntr[2] & cntr[1] & cntr[0];
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///////////////////////////////
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///////////////////////////////
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// Random logic for divider
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// Random logic for divider
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///////////////////////////////
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///////////////////////////////
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// Generation of sign extension of dividend and divisor
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// Generation of sign extension of dividend and divisor
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assign ecl_div_dividend_sign = ecl_div_signed_div & div_ecl_dividend_msb;
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assign ecl_div_dividend_sign = ecl_div_signed_div & div_ecl_dividend_msb;
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assign ecl_div_xinmask = div_ecl_divisorin_31 & ecl_div_signed_div;
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assign ecl_div_xinmask = div_ecl_divisorin_31 & ecl_div_signed_div;
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assign divisor_sign = div_ecl_x_msb & ecl_div_signed_div;
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assign divisor_sign = div_ecl_x_msb & ecl_div_signed_div;
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// Generation of next bit of quotient
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// Generation of next bit of quotient
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////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////
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// Calculate the next q. Requires calculating the result
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// Calculate the next q. Requires calculating the result
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// of the 65th bit of the adder and xoring it with the sign of
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// of the 65th bit of the adder and xoring it with the sign of
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// the divisor. The order of these xors is switched for critical
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// the divisor. The order of these xors is switched for critical
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// path considerations.
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// path considerations.
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////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////
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assign adderin1_64 = div_ecl_d_msb;
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assign adderin1_64 = div_ecl_d_msb;
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assign adderin2_64 = (ecl_div_signed_div & div_ecl_x_msb) ^ subtract;
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assign adderin2_64 = (ecl_div_signed_div & div_ecl_x_msb) ^ subtract;
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assign bit64_halfadd = adderin1_64 ^ adderin2_64;
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assign bit64_halfadd = adderin1_64 ^ adderin2_64;
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assign partial_qpredict = bit64_halfadd ^ ~(div_ecl_x_msb & ecl_div_signed_div);
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assign partial_qpredict = bit64_halfadd ^ ~(div_ecl_x_msb & ecl_div_signed_div);
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assign partial_qpredict_l = ~partial_qpredict;
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assign partial_qpredict_l = ~partial_qpredict;
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//assign qpredict = partial_qpredict ^ div_ecl_cout64;
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//assign qpredict = partial_qpredict ^ div_ecl_cout64;
|
//assign firstq = ~ecl_div_signed_div | div_ecl_xin_msb_l;
|
//assign firstq = ~ecl_div_signed_div | div_ecl_xin_msb_l;
|
assign firstq = ecl_div_dividend_sign;
|
assign firstq = ecl_div_dividend_sign;
|
|
|
mux2ds #(2) qnext_mux(.dout(q_next_nocout[1:0]),
|
mux2ds #(2) qnext_mux(.dout(q_next_nocout[1:0]),
|
.in0({partial_qpredict, partial_qpredict_l}),
|
.in0({partial_qpredict, partial_qpredict_l}),
|
.in1({2{firstq}}),
|
.in1({2{firstq}}),
|
.sel0(~ecl_div_ld_inputs),
|
.sel0(~ecl_div_ld_inputs),
|
.sel1(ecl_div_ld_inputs));
|
.sel1(ecl_div_ld_inputs));
|
dp_mux2es qnext_cout_mux(.dout(q_next),
|
dp_mux2es qnext_cout_mux(.dout(q_next),
|
.in0(q_next_nocout[1]),
|
.in0(q_next_nocout[1]),
|
.in1(q_next_nocout[0]),
|
.in1(q_next_nocout[0]),
|
.sel(div_ecl_cout64));
|
.sel(div_ecl_cout64));
|
|
|
dff q_dff(.din(q_next), .clk(clk), .q(ecl_div_newq), .se(se), .si(),
|
dff_s q_dff(.din(q_next), .clk(clk), .q(ecl_div_newq), .se(se), `SIMPLY_RISC_SCANIN,
|
.so());
|
.so());
|
|
|
|
|
////////////////////////////
|
////////////////////////////
|
// Subtraction logic and subtract flop
|
// Subtraction logic and subtract flop
|
//-------------------------------------
|
//-------------------------------------
|
// To take the subtraction calc out of the critical path,
|
// To take the subtraction calc out of the critical path,
|
// it is done in the previous cycle and part is done with a
|
// it is done in the previous cycle and part is done with a
|
// mux. The result is put into a flop.
|
// mux. The result is put into a flop.
|
////////////////////////////
|
////////////////////////////
|
assign firstlast_sub = ~ecl_div_almostlast_cycle & ~ecl_div_muls &
|
assign firstlast_sub = ~ecl_div_almostlast_cycle & ~ecl_div_muls &
|
(~ecl_div_signed_div | ~(div_ecl_dividend_msb ^ ~div_ecl_xin_msb_l));
|
(~ecl_div_signed_div | ~(div_ecl_dividend_msb ^ ~div_ecl_xin_msb_l));
|
|
|
assign ecl_div_keepx = ~(ecl_div_ld_inputs |
|
assign ecl_div_keepx = ~(ecl_div_ld_inputs |
|
ecl_div_almostlast_cycle);
|
ecl_div_almostlast_cycle);
|
|
|
mux2ds #(2) subnext_mux(.dout(sub_next_nocout[1:0]),
|
mux2ds #(2) subnext_mux(.dout(sub_next_nocout[1:0]),
|
.in0({2{firstlast_sub}}),
|
.in0({2{firstlast_sub}}),
|
.in1({partial_qpredict, partial_qpredict_l}),
|
.in1({partial_qpredict, partial_qpredict_l}),
|
.sel0(~ecl_div_keepx),
|
.sel0(~ecl_div_keepx),
|
.sel1(ecl_div_keepx));
|
.sel1(ecl_div_keepx));
|
dp_mux2es subtract_cout_mux(.dout(sub_next),
|
dp_mux2es subtract_cout_mux(.dout(sub_next),
|
.in0(sub_next_nocout[1]),
|
.in0(sub_next_nocout[1]),
|
.in1(sub_next_nocout[0]),
|
.in1(sub_next_nocout[0]),
|
.sel(div_ecl_cout64));
|
.sel(div_ecl_cout64));
|
|
|
dff sub_dff(.din(sub_next), .clk(clk), .q(subtract), .se(se), .si(),
|
dff_s sub_dff(.din(sub_next), .clk(clk), .q(subtract), .se(se), `SIMPLY_RISC_SCANIN,
|
.so());
|
.so());
|
|
|
assign ecl_div_subtract_l = ~subtract;
|
assign ecl_div_subtract_l = ~subtract;
|
|
|
|
|
/////////////////////////////////////////////
|
/////////////////////////////////////////////
|
// Carry in logic
|
// Carry in logic
|
//--------------------------------------------
|
//--------------------------------------------
|
// The carry is usually just subtract. The
|
// The carry is usually just subtract. The
|
// quotient correction for signed division
|
// quotient correction for signed division
|
// sometimes has to adjust it though.
|
// sometimes has to adjust it though.
|
/////////////////////////////////////////////
|
/////////////////////////////////////////////
|
assign detect_zero = div_ecl_detect_zero_low & div_ecl_detect_zero_high;
|
assign detect_zero = div_ecl_detect_zero_low & div_ecl_detect_zero_high;
|
|
|
assign ecl_div_cin = (ecl_div_last_cycle)? last_cin: subtract;
|
assign ecl_div_cin = (ecl_div_last_cycle)? last_cin: subtract;
|
// stores if the partial remainder was ever zero.
|
// stores if the partial remainder was ever zero.
|
/* -----\/----- EXCLUDED -----\/-----
|
/* -----\/----- EXCLUDED -----\/-----
|
// changed for timing
|
// changed for timing
|
assign zero_rem_d = ~ecl_div_ld_inputs & (div_ecl_detect_zero | zero_rem_q) &
|
assign zero_rem_d = ~ecl_div_ld_inputs & (div_ecl_detect_zero | zero_rem_q) &
|
(~div_ecl_d_62 | ecl_div_almostlast_cycle);
|
(~div_ecl_d_62 | ecl_div_almostlast_cycle);
|
-----/\----- EXCLUDED -----/\----- */
|
-----/\----- EXCLUDED -----/\----- */
|
assign new_zero_rem_with_zero = ~ecl_div_ld_inputs & (~div_ecl_d_62 | ecl_div_almostlast_cycle);
|
assign new_zero_rem_with_zero = ~ecl_div_ld_inputs & (~div_ecl_d_62 | ecl_div_almostlast_cycle);
|
assign new_zero_rem_no_zero = zero_rem_q & new_zero_rem_with_zero;
|
assign new_zero_rem_no_zero = zero_rem_q & new_zero_rem_with_zero;
|
assign zero_rem_d = (detect_zero)? new_zero_rem_with_zero: new_zero_rem_no_zero;
|
assign zero_rem_d = (detect_zero)? new_zero_rem_with_zero: new_zero_rem_no_zero;
|
dff zero_rem_dff(.din(zero_rem_d), .clk(clk), .q(zero_rem_q),
|
dff_s zero_rem_dff(.din(zero_rem_d), .clk(clk), .q(zero_rem_q),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
/* -----\/----- EXCLUDED -----\/-----
|
/* -----\/----- EXCLUDED -----\/-----
|
// changed for timing
|
// changed for timing
|
assign last_cin_next = ecl_div_signed_div & (divisor_sign & ~div_ecl_d_62 |
|
assign last_cin_next = ecl_div_signed_div & (divisor_sign & ~div_ecl_d_62 |
|
~divisor_sign &div_ecl_d_62&~zero_rem_d |
|
~divisor_sign &div_ecl_d_62&~zero_rem_d |
|
divisor_sign &div_ecl_d_62&zero_rem_d);
|
divisor_sign &div_ecl_d_62&zero_rem_d);
|
-----/\----- EXCLUDED -----/\----- */
|
-----/\----- EXCLUDED -----/\----- */
|
assign last_cin_with_zero = ecl_div_signed_div & (divisor_sign & ~div_ecl_d_62 |
|
assign last_cin_with_zero = ecl_div_signed_div & (divisor_sign & ~div_ecl_d_62 |
|
~divisor_sign &div_ecl_d_62&~new_zero_rem_with_zero |
|
~divisor_sign &div_ecl_d_62&~new_zero_rem_with_zero |
|
divisor_sign &div_ecl_d_62&new_zero_rem_with_zero);
|
divisor_sign &div_ecl_d_62&new_zero_rem_with_zero);
|
assign last_cin_no_zero = ecl_div_signed_div & (divisor_sign & ~div_ecl_d_62 |
|
assign last_cin_no_zero = ecl_div_signed_div & (divisor_sign & ~div_ecl_d_62 |
|
~divisor_sign &div_ecl_d_62&~new_zero_rem_no_zero |
|
~divisor_sign &div_ecl_d_62&~new_zero_rem_no_zero |
|
divisor_sign &div_ecl_d_62&new_zero_rem_no_zero);
|
divisor_sign &div_ecl_d_62&new_zero_rem_no_zero);
|
assign last_cin_next = (detect_zero)? last_cin_with_zero: last_cin_no_zero;
|
assign last_cin_next = (detect_zero)? last_cin_with_zero: last_cin_no_zero;
|
dff last_cin_dff(.din(last_cin_next), .clk(clk), .q(last_cin),
|
dff_s last_cin_dff(.din(last_cin_next), .clk(clk), .q(last_cin),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
///////////////////////////////
|
///////////////////////////////
|
// Condition code generation
|
// Condition code generation
|
///////////////////////////////
|
///////////////////////////////
|
// There is a special case:
|
// There is a special case:
|
// For 64 bit signed division largest neg/-1 = largest neg
|
// For 64 bit signed division largest neg/-1 = largest neg
|
// However for 32 bit division this will give us positive overflow.
|
// However for 32 bit division this will give us positive overflow.
|
// This is detected by a sign switch on this case.
|
// This is detected by a sign switch on this case.
|
wire inputs_neg_d;
|
wire inputs_neg_d;
|
wire inputs_neg_q;
|
wire inputs_neg_q;
|
wire large_neg_ovfl;
|
wire large_neg_ovfl;
|
assign inputs_neg_d = div_ecl_dividend_msb & div_ecl_divisorin_31;
|
assign inputs_neg_d = div_ecl_dividend_msb & div_ecl_divisorin_31;
|
assign large_neg_ovfl = inputs_neg_q & ~gencc_in_msb_l_d1;
|
assign large_neg_ovfl = inputs_neg_q & ~gencc_in_msb_l_d1;
|
dffe inputs_neg_dff(.din(inputs_neg_d), .clk(clk), .q(inputs_neg_q),
|
dffe_s inputs_neg_dff(.din(inputs_neg_d), .clk(clk), .q(inputs_neg_q),
|
.en(ecl_div_ld_inputs), .se(se), .si(), .so());
|
.en(ecl_div_ld_inputs), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(5) cc_sig_dff(.din({div_ecl_upper32_equal, div_ecl_gencc_in_msb_l,
|
dff_s #(5) cc_sig_dff(.din({div_ecl_upper32_equal, div_ecl_gencc_in_msb_l,
|
div_ecl_gencc_in_31, ecl_div_sel_div, div_ecl_low32_nonzero}),
|
div_ecl_gencc_in_31, ecl_div_sel_div, div_ecl_low32_nonzero}),
|
.q({upper32_equal_d1, gencc_in_msb_l_d1,
|
.q({upper32_equal_d1, gencc_in_msb_l_d1,
|
gencc_in_31_d1, sel_div_d1, low32_nonzero_d1}),
|
gencc_in_31_d1, sel_div_d1, low32_nonzero_d1}),
|
.clk(clk), .se(se), .si(), .so());
|
.clk(clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
// selects for correcting divide overflow
|
// selects for correcting divide overflow
|
assign ecl_div_sel_64b = ecl_div_div64 | ecl_div_muls;
|
assign ecl_div_sel_64b = ecl_div_div64 | ecl_div_muls;
|
assign ecl_div_sel_u32 = ~ecl_div_sel_64b & ~ecl_div_signed_div;
|
assign ecl_div_sel_u32 = ~ecl_div_sel_64b & ~ecl_div_signed_div;
|
assign ecl_div_sel_pos32 = (~ecl_div_sel_64b & ecl_div_signed_div &
|
assign ecl_div_sel_pos32 = (~ecl_div_sel_64b & ecl_div_signed_div &
|
(gencc_in_msb_l_d1 | large_neg_ovfl));
|
(gencc_in_msb_l_d1 | large_neg_ovfl));
|
assign ecl_div_sel_neg32 = (~ecl_div_sel_64b & ecl_div_signed_div &
|
assign ecl_div_sel_neg32 = (~ecl_div_sel_64b & ecl_div_signed_div &
|
~gencc_in_msb_l_d1 & ~large_neg_ovfl);
|
~gencc_in_msb_l_d1 & ~large_neg_ovfl);
|
|
|
// results of checking are staged one cycle for timing reasons
|
// results of checking are staged one cycle for timing reasons
|
// this is the reason for the chk and fix ovfl states
|
// this is the reason for the chk and fix ovfl states
|
assign ecl_div_upper32_zero = upper32_equal_d1 & gencc_in_msb_l_d1;
|
assign ecl_div_upper32_zero = upper32_equal_d1 & gencc_in_msb_l_d1;
|
assign ecl_div_upper33_zero = (upper32_equal_d1 & gencc_in_msb_l_d1 &
|
assign ecl_div_upper33_zero = (upper32_equal_d1 & gencc_in_msb_l_d1 &
|
~gencc_in_31_d1);
|
~gencc_in_31_d1);
|
assign ecl_div_upper33_one = (upper32_equal_d1 & ~gencc_in_msb_l_d1 &
|
assign ecl_div_upper33_one = (upper32_equal_d1 & ~gencc_in_msb_l_d1 &
|
gencc_in_31_d1);
|
gencc_in_31_d1);
|
|
|
// divide overflow
|
// divide overflow
|
assign unsign_ovfl = ecl_div_sel_u32 & ~ecl_div_upper32_zero & sel_div_d1;
|
assign unsign_ovfl = ecl_div_sel_u32 & ~ecl_div_upper32_zero & sel_div_d1;
|
assign pos_ovfl = ecl_div_sel_pos32 & ~ecl_div_upper33_zero & sel_div_d1;
|
assign pos_ovfl = ecl_div_sel_pos32 & ~ecl_div_upper33_zero & sel_div_d1;
|
assign neg_ovfl = ecl_div_sel_neg32 & ~ecl_div_upper33_one & sel_div_d1;
|
assign neg_ovfl = ecl_div_sel_neg32 & ~ecl_div_upper33_one & sel_div_d1;
|
assign div_v = pos_ovfl | unsign_ovfl | neg_ovfl;
|
assign div_v = pos_ovfl | unsign_ovfl | neg_ovfl;
|
|
|
// muls carry and overflow
|
// muls carry and overflow
|
assign next_muls_c = (div_state[1]) ? div_ecl_cout32: muls_c;
|
assign next_muls_c = (div_state[`RUN]) ? div_ecl_cout32: muls_c;
|
|
|
assign muls_rs1_data_31_m = ~muls_rs1_31_m_l;
|
assign muls_rs1_data_31_m = ~muls_rs1_31_m_l;
|
dff #(3) muls_overlow_dff(.din({muls_rs1_data_31_m, rs2_data_31_m, div_ecl_adder_out_31}),
|
dff_s #(3) muls_overlow_dff(.din({muls_rs1_data_31_m, rs2_data_31_m, div_ecl_adder_out_31}),
|
.q({muls_rs1_data_31_w, rs2_data_31_w, div_adder_out_31_w}),
|
.q({muls_rs1_data_31_w, rs2_data_31_w, div_adder_out_31_w}),
|
.clk(clk), .se(se), .si(), .so());
|
.clk(clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign ovfl_32 = ((muls_rs1_data_31_w & rs2_data_31_w & ~div_adder_out_31_w) |
|
assign ovfl_32 = ((muls_rs1_data_31_w & rs2_data_31_w & ~div_adder_out_31_w) |
|
(~muls_rs1_data_31_w & ~rs2_data_31_w & div_adder_out_31_w));
|
(~muls_rs1_data_31_w & ~rs2_data_31_w & div_adder_out_31_w));
|
assign next_muls_v = (div_state[4]) ? ovfl_32: muls_v;
|
assign next_muls_v = (div_state[`FIX_OVFL]) ? ovfl_32: muls_v;
|
dff muls_c_dff(.din(next_muls_c), .clk(clk), .q(muls_c),
|
dff_s muls_c_dff(.din(next_muls_c), .clk(clk), .q(muls_c),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff muls_v_dff(.din(next_muls_v), .clk(clk), .q(muls_v),
|
dff_s muls_v_dff(.din(next_muls_v), .clk(clk), .q(muls_v),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// negative
|
// negative
|
assign xcc[3] = ~gencc_in_msb_l_d1 & ~unsign_ovfl & ~pos_ovfl;
|
assign xcc[3] = ~gencc_in_msb_l_d1 & ~unsign_ovfl & ~pos_ovfl;
|
assign icc[3] = (gencc_in_31_d1 & ~pos_ovfl) | neg_ovfl | unsign_ovfl;
|
assign icc[3] = (gencc_in_31_d1 & ~pos_ovfl) | neg_ovfl | unsign_ovfl;
|
// zero
|
// zero
|
assign xcc[2] = upper32_equal_d1 & gencc_in_msb_l_d1 & ~low32_nonzero_d1;
|
assign xcc[2] = upper32_equal_d1 & gencc_in_msb_l_d1 & ~low32_nonzero_d1;
|
assign icc[2] = ~low32_nonzero_d1 & ~div_v; // nonzero checks before ovfl
|
assign icc[2] = ~low32_nonzero_d1 & ~div_v; // nonzero checks before ovfl
|
//overflow
|
//overflow
|
assign xcc[1] = 1'b0;
|
assign xcc[1] = 1'b0;
|
assign icc[1] = (ecl_div_muls & sel_div_d1) ? muls_v: div_v;
|
assign icc[1] = (ecl_div_muls & sel_div_d1) ? muls_v: div_v;
|
// carry
|
// carry
|
assign xcc[0] = 1'b0;
|
assign xcc[0] = 1'b0;
|
assign icc[0] = ecl_div_muls & sel_div_d1 & muls_c;
|
assign icc[0] = ecl_div_muls & sel_div_d1 & muls_c;
|
|
|
assign divcntl_ccr_cc_w2 = {xcc, icc};
|
assign divcntl_ccr_cc_w2 = {xcc, icc};
|
|
|
endmodule // sparc_exu_divcntl
|
endmodule // sparc_exu_divcntl
|
|
|