// ========== Copyright Header Begin ==========================================
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// ========== Copyright Header Begin ==========================================
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//
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//
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// OpenSPARC T1 Processor File: sparc_ifu_lru4.v
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// OpenSPARC T1 Processor File: sparc_ifu_lru4.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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//
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// The above named program is free software; you can redistribute it and/or
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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// License version 2 as published by the Free Software Foundation.
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//
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//
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// The above named program is distributed in the hope that it will be
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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// General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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`ifdef SIMPLY_RISC_TWEAKS
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`define SIMPLY_RISC_SCANIN .si(0)
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`else
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`define SIMPLY_RISC_SCANIN .si()
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`endif
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/*
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/*
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// Module Name: sparc_ifu_lru4
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// Module Name: sparc_ifu_lru4
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// Description:
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// Description:
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// LRU scheduler. Least priority to the last granted
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// LRU scheduler. Least priority to the last granted
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// customer. If no requests, the priority remains the same.
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// customer. If no requests, the priority remains the same.
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*/
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*/
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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module sparc_ifu_lru4(/*AUTOARG*/
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module sparc_ifu_lru4(/*AUTOARG*/
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// Outputs
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// Outputs
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grant_vec, so,
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grant_vec, so,
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// Inputs
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// Inputs
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clk, reset, se, si, recent_vec, load_recent, req_vec, spec_vec,
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clk, reset, se, si, recent_vec, load_recent, req_vec, spec_vec,
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use_spec
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use_spec
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);
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);
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input clk, reset, se, si;
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input clk, reset, se, si;
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input [3:0] recent_vec;
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input [3:0] recent_vec;
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input load_recent;
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input load_recent;
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input [3:0] req_vec,
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input [3:0] req_vec,
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spec_vec;
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spec_vec;
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input use_spec;
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input use_spec;
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output [3:0] grant_vec;
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output [3:0] grant_vec;
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output so;
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output so;
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wire [3:0] used0, // used0 is mru
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wire [3:0] used0, // used0 is mru
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used1,
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used1,
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used2,
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used2,
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used3; // used3 is lru
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used3; // used3 is lru
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wire [3:0] used23,
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wire [3:0] used23,
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used23_nxt;
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used23_nxt;
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wire [3:0] used0_buf,
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wire [3:0] used0_buf,
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used1_buf,
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used1_buf,
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used2_buf,
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used2_buf,
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used3_buf;
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used3_buf;
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wire [3:0] sp_used0,
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wire [3:0] sp_used0,
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sp_used1,
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sp_used1,
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sp_used2,
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sp_used2,
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sp_used3;
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sp_used3;
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wire [3:0] nosp_used0,
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wire [3:0] nosp_used0,
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nosp_used1,
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nosp_used1,
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nosp_used2,
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nosp_used2,
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nosp_used3;
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nosp_used3;
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wire [3:0] used0_calc,
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wire [3:0] used0_calc,
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used0_nxt,
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used0_nxt,
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used1_calc,
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used1_calc,
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used1_nxt,
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used1_nxt,
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used2_calc,
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used2_calc,
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used2_nxt,
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used2_nxt,
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used3_calc,
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used3_calc,
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used3_nxt;
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used3_nxt;
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wire hit1,
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wire hit1,
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hit2,
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hit2,
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hit3;
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hit3;
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wire [3:0] nospec_grant,
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wire [3:0] nospec_grant,
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spec_grant;
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spec_grant;
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wire reqhit1,
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wire reqhit1,
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reqhit2,
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reqhit2,
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reqhit3,
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reqhit3,
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reqhit23;
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reqhit23;
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wire spechit1,
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wire spechit1,
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spechit2,
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spechit2,
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spechit3,
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spechit3,
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spechit23;
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spechit23;
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wire sel_u0,
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wire sel_u0,
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sel_u1,
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sel_u1,
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sel_u2,
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sel_u2,
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sel_u3;
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sel_u3;
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wire sel_su0,
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wire sel_su0,
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sel_su1,
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sel_su1,
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sel_su2,
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sel_su2,
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sel_su3;
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sel_su3;
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dp_buffer #(4) use_buf0(.dout(used0_buf),
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dp_buffer #(4) use_buf0(.dout(used0_buf),
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.in (used0));
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.in (used0));
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dp_buffer #(4) use_buf1(.dout(used1_buf),
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dp_buffer #(4) use_buf1(.dout(used1_buf),
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.in (used1));
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.in (used1));
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dp_buffer #(4) use_buf2(.dout(used2_buf),
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dp_buffer #(4) use_buf2(.dout(used2_buf),
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.in (used2));
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.in (used2));
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dp_buffer #(4) use_buf3(.dout(used3_buf),
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dp_buffer #(4) use_buf3(.dout(used3_buf),
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.in (used3));
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.in (used3));
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// determine lru order for next cycle
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// determine lru order for next cycle
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// assign hit0 = (used0_buf[0] & recent_vec[0] |
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// assign hit0 = (used0_buf[0] & recent_vec[0] |
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// used0_buf[1] & recent_vec[1] |
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// used0_buf[1] & recent_vec[1] |
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// used0_buf[2] & recent_vec[2] |
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// used0_buf[2] & recent_vec[2] |
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// used0_buf[3] & recent_vec[3]) & load_recent;
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// used0_buf[3] & recent_vec[3]) & load_recent;
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assign hit1 = (used1_buf[0] & recent_vec[0] |
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assign hit1 = (used1_buf[0] & recent_vec[0] |
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used1_buf[1] & recent_vec[1] |
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used1_buf[1] & recent_vec[1] |
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used1_buf[2] & recent_vec[2] |
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used1_buf[2] & recent_vec[2] |
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used1_buf[3] & recent_vec[3]) & load_recent;
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used1_buf[3] & recent_vec[3]) & load_recent;
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assign hit2 = (used2_buf[0] & recent_vec[0] |
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assign hit2 = (used2_buf[0] & recent_vec[0] |
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used2_buf[1] & recent_vec[1] |
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used2_buf[1] & recent_vec[1] |
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used2_buf[2] & recent_vec[2] |
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used2_buf[2] & recent_vec[2] |
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used2_buf[3] & recent_vec[3]) & load_recent;
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used2_buf[3] & recent_vec[3]) & load_recent;
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assign hit3 = (used3_buf[0] & recent_vec[0] |
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assign hit3 = (used3_buf[0] & recent_vec[0] |
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used3_buf[1] & recent_vec[1] |
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used3_buf[1] & recent_vec[1] |
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used3_buf[2] & recent_vec[2] |
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used3_buf[2] & recent_vec[2] |
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used3_buf[3] & recent_vec[3]) & load_recent;
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used3_buf[3] & recent_vec[3]) & load_recent;
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assign used0_calc = load_recent ? recent_vec : used0_buf;
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assign used0_calc = load_recent ? recent_vec : used0_buf;
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assign used1_calc = (hit3 | hit2 | hit1) ? used0_buf : used1_buf;
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assign used1_calc = (hit3 | hit2 | hit1) ? used0_buf : used1_buf;
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assign used2_calc = (hit3 | hit2) ? used1_buf : used2_buf;
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assign used2_calc = (hit3 | hit2) ? used1_buf : used2_buf;
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assign used3_calc = (hit3) ? used2_buf : used3_buf;
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assign used3_calc = (hit3) ? used2_buf : used3_buf;
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assign used0_nxt = reset ? 4'b0001 : used0_calc;
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assign used0_nxt = reset ? 4'b0001 : used0_calc;
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assign used1_nxt = reset ? 4'b0010 : used1_calc;
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assign used1_nxt = reset ? 4'b0010 : used1_calc;
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assign used2_nxt = reset ? 4'b0100 : used2_calc;
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assign used2_nxt = reset ? 4'b0100 : used2_calc;
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assign used3_nxt = reset ? 4'b1000 : used3_calc;
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assign used3_nxt = reset ? 4'b1000 : used3_calc;
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// use 4X4 matrix to hold lru info
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// use 4X4 matrix to hold lru info
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dff #(4) use0_reg(.din (used0_nxt),
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dff_s #(4) use0_reg(.din (used0_nxt),
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.q (used0),
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.q (used0),
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.clk (clk), .se(se), .si(), .so());
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.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
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dff #(4) use1_reg(.din (used1_nxt),
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dff_s #(4) use1_reg(.din (used1_nxt),
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.q (used1),
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.q (used1),
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.clk (clk), .se(se), .si(), .so());
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.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
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dff #(4) use2_reg(.din (used2_nxt),
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dff_s #(4) use2_reg(.din (used2_nxt),
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.q (used2),
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.q (used2),
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.clk (clk), .se(se), .si(), .so());
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.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
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// used3 is lru
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// used3 is lru
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dff #(4) use3_reg(.din (used3_nxt),
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dff_s #(4) use3_reg(.din (used3_nxt),
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.q (used3),
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.q (used3),
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.clk (clk), .se(se), .si(), .so());
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.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
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assign used23_nxt = used2_nxt | used3_nxt;
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assign used23_nxt = used2_nxt | used3_nxt;
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dff #(4) use23_reg(.din (used23_nxt),
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dff_s #(4) use23_reg(.din (used23_nxt),
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.q (used23),
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.q (used23),
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.clk (clk), .se(se), .si(), .so());
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.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
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// grant request based on lru
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// grant request based on lru
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// save some loading on req_vec by not doing this
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// save some loading on req_vec by not doing this
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// assign reqhit0 = (used0[0] & req_vec[0] |
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// assign reqhit0 = (used0[0] & req_vec[0] |
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// used0[1] & req_vec[1] |
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// used0[1] & req_vec[1] |
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// used0[2] & req_vec[2] |
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// used0[2] & req_vec[2] |
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// used0[3] & req_vec[3]);
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// used0[3] & req_vec[3]);
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assign reqhit1 = (used1[0] & req_vec[0] |
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assign reqhit1 = (used1[0] & req_vec[0] |
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used1[1] & req_vec[1] |
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used1[1] & req_vec[1] |
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used1[2] & req_vec[2] |
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used1[2] & req_vec[2] |
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used1[3] & req_vec[3]);
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used1[3] & req_vec[3]);
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assign reqhit2 = (used2[0] & req_vec[0] |
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assign reqhit2 = (used2[0] & req_vec[0] |
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used2[1] & req_vec[1] |
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used2[1] & req_vec[1] |
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used2[2] & req_vec[2] |
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used2[2] & req_vec[2] |
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used2[3] & req_vec[3]);
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used2[3] & req_vec[3]);
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assign reqhit3 = (used3[0] & req_vec[0] |
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assign reqhit3 = (used3[0] & req_vec[0] |
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used3[1] & req_vec[1] |
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used3[1] & req_vec[1] |
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used3[2] & req_vec[2] |
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used3[2] & req_vec[2] |
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used3[3] & req_vec[3]);
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used3[3] & req_vec[3]);
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assign reqhit23 = (used23[0] & req_vec[0] |
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assign reqhit23 = (used23[0] & req_vec[0] |
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used23[1] & req_vec[1] |
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used23[1] & req_vec[1] |
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used23[2] & req_vec[2] |
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used23[2] & req_vec[2] |
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used23[3] & req_vec[3]);
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used23[3] & req_vec[3]);
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assign sel_u3 = reqhit3;
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assign sel_u3 = reqhit3;
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assign sel_u2 = ~reqhit3 & reqhit2;
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assign sel_u2 = ~reqhit3 & reqhit2;
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assign sel_u1 = ~reqhit23 & reqhit1;
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assign sel_u1 = ~reqhit23 & reqhit1;
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assign sel_u0 = ~reqhit23 & ~reqhit1;
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assign sel_u0 = ~reqhit23 & ~reqhit1;
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assign nosp_used0 = used0 & {4{~use_spec}};
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assign nosp_used0 = used0 & {4{~use_spec}};
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assign nosp_used1 = used1 & {4{~use_spec}};
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assign nosp_used1 = used1 & {4{~use_spec}};
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assign nosp_used2 = used2 & {4{~use_spec}};
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assign nosp_used2 = used2 & {4{~use_spec}};
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assign nosp_used3 = used3 & {4{~use_spec}};
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assign nosp_used3 = used3 & {4{~use_spec}};
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mux4ds #(4) nsgnt_mux(.dout (nospec_grant),
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mux4ds #(4) nsgnt_mux(.dout (nospec_grant),
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.in0 (nosp_used0),
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.in0 (nosp_used0),
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.in1 (nosp_used1),
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.in1 (nosp_used1),
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.in2 (nosp_used2),
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.in2 (nosp_used2),
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.in3 (nosp_used3),
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.in3 (nosp_used3),
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.sel0 (sel_u0),
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.sel0 (sel_u0),
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.sel1 (sel_u1),
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.sel1 (sel_u1),
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.sel2 (sel_u2),
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.sel2 (sel_u2),
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.sel3 (sel_u3));
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.sel3 (sel_u3));
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assign spechit1 = (used1[0] & spec_vec[0] |
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assign spechit1 = (used1[0] & spec_vec[0] |
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used1[1] & spec_vec[1] |
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used1[1] & spec_vec[1] |
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used1[2] & spec_vec[2] |
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used1[2] & spec_vec[2] |
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used1[3] & spec_vec[3]);
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used1[3] & spec_vec[3]);
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assign spechit2 = (used2[0] & spec_vec[0] |
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assign spechit2 = (used2[0] & spec_vec[0] |
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used2[1] & spec_vec[1] |
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used2[1] & spec_vec[1] |
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used2[2] & spec_vec[2] |
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used2[2] & spec_vec[2] |
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used2[3] & spec_vec[3]);
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used2[3] & spec_vec[3]);
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assign spechit3 = (used3[0] & spec_vec[0] |
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assign spechit3 = (used3[0] & spec_vec[0] |
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used3[1] & spec_vec[1] |
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used3[1] & spec_vec[1] |
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used3[2] & spec_vec[2] |
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used3[2] & spec_vec[2] |
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used3[3] & spec_vec[3]);
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used3[3] & spec_vec[3]);
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assign spechit23 = (used23[0] & spec_vec[0] |
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assign spechit23 = (used23[0] & spec_vec[0] |
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used23[1] & spec_vec[1] |
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used23[1] & spec_vec[1] |
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used23[2] & spec_vec[2] |
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used23[2] & spec_vec[2] |
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used23[3] & spec_vec[3]);
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used23[3] & spec_vec[3]);
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assign sel_su3 = spechit3;
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assign sel_su3 = spechit3;
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assign sel_su2 = ~spechit3 & spechit2;
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assign sel_su2 = ~spechit3 & spechit2;
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assign sel_su1 = ~spechit23 & spechit1;
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assign sel_su1 = ~spechit23 & spechit1;
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assign sel_su0 = ~spechit23 & ~spechit1;
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assign sel_su0 = ~spechit23 & ~spechit1;
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assign sp_used0 = used0 & {4{use_spec}};
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assign sp_used0 = used0 & {4{use_spec}};
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assign sp_used1 = used1 & {4{use_spec}};
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assign sp_used1 = used1 & {4{use_spec}};
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assign sp_used2 = used2 & {4{use_spec}};
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assign sp_used2 = used2 & {4{use_spec}};
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assign sp_used3 = used3 & {4{use_spec}};
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assign sp_used3 = used3 & {4{use_spec}};
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mux4ds #(4) sgnt_mux(.dout (spec_grant),
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mux4ds #(4) sgnt_mux(.dout (spec_grant),
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.in0 (sp_used0),
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.in0 (sp_used0),
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.in1 (sp_used1),
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.in1 (sp_used1),
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.in2 (sp_used2),
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.in2 (sp_used2),
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.in3 (sp_used3),
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.in3 (sp_used3),
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.sel0 (sel_su0),
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.sel0 (sel_su0),
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.sel1 (sel_su1),
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.sel1 (sel_su1),
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.sel2 (sel_su2),
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.sel2 (sel_su2),
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.sel3 (sel_su3));
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.sel3 (sel_su3));
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assign grant_vec = spec_grant | nospec_grant;
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assign grant_vec = spec_grant | nospec_grant;
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endmodule // sparc_ifu_lru4
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endmodule // sparc_ifu_lru4
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