// ========== Copyright Header Begin ==========================================
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// ========== Copyright Header Begin ==========================================
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//
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//
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// OpenSPARC T1 Processor File: sparc_ifu_thrcmpl.v
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// OpenSPARC T1 Processor File: sparc_ifu_thrcmpl.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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//
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// The above named program is free software; you can redistribute it and/or
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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// License version 2 as published by the Free Software Foundation.
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//
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//
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// The above named program is distributed in the hope that it will be
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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// General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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`ifdef SIMPLY_RISC_TWEAKS
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`define SIMPLY_RISC_SCANIN .si(0)
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`else
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`define SIMPLY_RISC_SCANIN .si()
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`endif
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/*
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/*
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// Module Name: sparc_ifu_thrcmpl
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// Module Name: sparc_ifu_thrcmpl
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// Description:
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// Description:
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// The thread completion block processes the completion signals fomr
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// The thread completion block processes the completion signals fomr
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// the different cpu blocks and generates a unified completion
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// the different cpu blocks and generates a unified completion
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// signal.
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// signal.
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*/
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*/
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module sparc_ifu_thrcmpl(/*AUTOARG*/
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module sparc_ifu_thrcmpl(/*AUTOARG*/
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// Outputs
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// Outputs
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completion, wm_imiss, wm_other,
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completion, wm_imiss, wm_other,
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// Inputs
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// Inputs
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clk, se, si, reset, fcl_ifq_icmiss_s1, erb_dtu_ifeterr_d1,
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clk, se, si, reset, fcl_ifq_icmiss_s1, erb_dtu_ifeterr_d1,
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sw_cond_s, en_spec_g, atr_s, dtu_fcl_thr_active, ifq_dtu_thrrdy,
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sw_cond_s, en_spec_g, atr_s, dtu_fcl_thr_active, ifq_dtu_thrrdy,
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ifq_dtu_pred_rdy, exu_lop_done, branch_done_d, fixedop_done,
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ifq_dtu_pred_rdy, exu_lop_done, branch_done_d, fixedop_done,
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ldmiss, spec_ld_d, trap, retr_thr_wakeup, flush_wake_w2,
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ldmiss, spec_ld_d, trap, retr_thr_wakeup, flush_wake_w2,
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ldhit_thr, spec_ld_g, clear_wmo_e,wbm_spc_stall,wbm_spc_resume,wait_state, wm_stbwait, stb_retry,
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ldhit_thr, spec_ld_g, clear_wmo_e, wm_stbwait, stb_retry,
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rst_thread, trap_thrrdy, thr_s2, thr_e, thr_s1, fp_thrrdy,
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rst_thread, trap_thrrdy, thr_s2, thr_e, thr_s1, fp_thrrdy,
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lsu_ifu_ldst_cmplt, sta_done_e, killed_inst_done_e
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lsu_ifu_ldst_cmplt, sta_done_e, killed_inst_done_e
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);
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);
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input clk, se, si, reset;
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input clk, se, si, reset;
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input fcl_ifq_icmiss_s1;
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input fcl_ifq_icmiss_s1;
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input erb_dtu_ifeterr_d1;
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input erb_dtu_ifeterr_d1;
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input sw_cond_s;
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input sw_cond_s;
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input en_spec_g;
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input en_spec_g;
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input atr_s;
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input atr_s;
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input [3:0] dtu_fcl_thr_active;
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input [3:0] dtu_fcl_thr_active;
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input [3:0] ifq_dtu_thrrdy, // I$ miss completion
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input [3:0] ifq_dtu_thrrdy, // I$ miss completion
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ifq_dtu_pred_rdy,
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ifq_dtu_pred_rdy,
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exu_lop_done, // mul, div, wrpr, sav, rest
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exu_lop_done, // mul, div, wrpr, sav, rest
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branch_done_d,
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branch_done_d,
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fixedop_done; // br, rdsr, wrs/pr,
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fixedop_done; // br, rdsr, wrs/pr,
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input [3:0] ldmiss,
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input [3:0] ldmiss,
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spec_ld_d,
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spec_ld_d,
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trap,
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trap,
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retr_thr_wakeup,
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retr_thr_wakeup,
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flush_wake_w2,
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flush_wake_w2,
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ldhit_thr,
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ldhit_thr,
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spec_ld_g;
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spec_ld_g;
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input clear_wmo_e;input wbm_spc_stall;input wbm_spc_resume;output wait_state;wire wait_next;
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input clear_wmo_e;
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input [3:0] wm_stbwait,
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input [3:0] wm_stbwait,
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stb_retry;
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stb_retry;
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input [3:0] rst_thread,
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input [3:0] rst_thread,
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trap_thrrdy;
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trap_thrrdy;
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input [3:0] thr_s2,
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input [3:0] thr_s2,
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thr_e,
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thr_e,
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thr_s1;
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thr_s1;
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input [3:0] fp_thrrdy;
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input [3:0] fp_thrrdy;
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input [3:0] lsu_ifu_ldst_cmplt; // sta local, ld and atomic done
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input [3:0] lsu_ifu_ldst_cmplt; // sta local, ld and atomic done
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input sta_done_e,
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input sta_done_e,
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killed_inst_done_e; // long lat op was killed
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killed_inst_done_e; // long lat op was killed
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// .. Other completion signals needed
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// .. Other completion signals needed
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// 1. STA completion from LSU -- real mem done 10/03, local TBD
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// 1. STA completion from LSU -- real mem done 10/03, local TBD
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// 2. Atomic completion -- done
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// 2. Atomic completion -- done
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// 3. membar completion (lsu) -- done
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// 3. membar completion (lsu) -- done
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// 4. flush completion (lsu)
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// 4. flush completion (lsu)
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// 5. FP op completion (ffu)
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// 5. FP op completion (ffu)
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//
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//
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output [3:0] completion;
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output [3:0] completion;
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output [3:0] wm_imiss;
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output [3:0] wm_imiss;
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output [3:0] wm_other;
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output [3:0] wm_other;
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// local signals
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// local signals
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wire [3:0] wm_imiss,
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wire [3:0] wm_imiss,
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wm_other,
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wm_other,
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wmi_nxt,
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wmi_nxt,
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wmo_nxt;
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wmo_nxt;
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wire [3:0] clr_wmo_thr_e;
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wire [3:0] clr_wmo_thr_e;
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wire [3:0] ldst_thrrdy,
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wire [3:0] ldst_thrrdy,
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ld_thrrdy,
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ld_thrrdy,
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sta_thrrdy,
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sta_thrrdy,
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killed_thrrdy,
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killed_thrrdy,
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fp_thrrdy,
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fp_thrrdy,
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pred_ifq_rdy,
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pred_ifq_rdy,
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imiss_thrrdy,
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imiss_thrrdy,
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other_thrrdy;
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other_thrrdy;
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// wire [3:0] can_imiss;
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// wire [3:0] can_imiss;
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Code begins here
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// Code begins here
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Thread completion
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// Thread completion
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// Since an imiss can overlap with anything else, have to make sure
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// Since an imiss can overlap with anything else, have to make sure
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// the imiss condition has been cleared.
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// the imiss condition has been cleared.
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// Imiss itself has to make sure ALL OTHER conditions have been
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// Imiss itself has to make sure ALL OTHER conditions have been
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// cleared. In this code, I am not checking for branches being
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// cleared. In this code, I am not checking for branches being
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// cleared, since Imiss is assumed to take much longer than a branch.
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// cleared, since Imiss is assumed to take much longer than a branch.
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// -- may not be a valid assumption, since milhits could be faster
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// -- may not be a valid assumption, since milhits could be faster
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// assign can_imiss = fcl_ifq_canthr;
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// assign can_imiss = fcl_ifq_canthr;
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// & (wm_imiss | ({4{fcl_ifq_icmiss_s1}} & thr_s1));
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// & (wm_imiss | ({4{fcl_ifq_icmiss_s1}} & thr_s1));
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dffr #(4) wmi_ff(.din (wmi_nxt),
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dffr_s #(4) wmi_ff(.din (wmi_nxt),
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.clk (clk),
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.clk (clk),
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.q (wm_imiss),
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.q (wm_imiss),
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.rst (reset),
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.rst (reset),
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.se (se), .si(), .so());
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.se (se), `SIMPLY_RISC_SCANIN, .so());
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dffr #(4) wmo_ff(.din (wmo_nxt),
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dffr_s #(4) wmo_ff(.din (wmo_nxt),
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.clk (clk),
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.clk (clk),
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.q (wm_other),
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.q (wm_other),
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.rst (reset),
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.rst (reset),
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.se (se), .si(), .so());
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.se (se), `SIMPLY_RISC_SCANIN, .so());
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assign wmi_nxt = ({4{fcl_ifq_icmiss_s1}} & thr_s1) | // set
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assign wmi_nxt = ({4{fcl_ifq_icmiss_s1}} & thr_s1) | // set
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({4{erb_dtu_ifeterr_d1}} & thr_e) |
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({4{erb_dtu_ifeterr_d1}} & thr_e) |
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(wm_imiss & ~imiss_thrrdy); // reset
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(wm_imiss & ~imiss_thrrdy); // reset
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// clear wm_other when we have a retracted store
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// clear wm_other when we have a retracted store
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assign clr_wmo_thr_e = {4{clear_wmo_e}} & thr_e;
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assign clr_wmo_thr_e = {4{clear_wmo_e}} & thr_e;
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assign wmo_nxt = (({4{sw_cond_s}} & thr_s2 & ~clr_wmo_thr_e) |
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assign wmo_nxt = (({4{sw_cond_s}} & thr_s2 & ~clr_wmo_thr_e) |
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trap | ldmiss) & dtu_fcl_thr_active |
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trap | ldmiss) & dtu_fcl_thr_active |
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rst_thread | // set
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rst_thread | // set
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wm_other & dtu_fcl_thr_active &
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wm_other & dtu_fcl_thr_active &
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~(other_thrrdy | spec_ld_d | clr_wmo_thr_e); // reset
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~(other_thrrdy | spec_ld_d | clr_wmo_thr_e); // reset
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// A load hit signal is always for the load which is being filled
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// A load hit signal is always for the load which is being filled
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// to the RF. If speculation is enabled, the load would have
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// to the RF. If speculation is enabled, the load would have
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// completed even before the hit signal. So need to suppress the
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// completed even before the hit signal. So need to suppress the
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// completions signal.
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// completions signal.
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// load miss, st buf hit, ld/st alternate completion
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// load miss, st buf hit, ld/st alternate completion
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assign ldst_thrrdy = lsu_ifu_ldst_cmplt & ~spec_ld_g;
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assign ldst_thrrdy = lsu_ifu_ldst_cmplt & ~spec_ld_g;
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assign ld_thrrdy = ldhit_thr & {4{~en_spec_g}};
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assign ld_thrrdy = ldhit_thr & {4{~en_spec_g}};
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assign sta_thrrdy = thr_e & {4{sta_done_e}};
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assign sta_thrrdy = thr_e & {4{sta_done_e}};
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assign killed_thrrdy = thr_e & {4{killed_inst_done_e}};
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assign killed_thrrdy = thr_e & {4{killed_inst_done_e}};
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// everthing else
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// everthing else
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assign other_thrrdy = (ldst_thrrdy | // ld, sta local, atomic
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assign other_thrrdy = (ldst_thrrdy | // ld, sta local, atomic
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branch_done_d | // br
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branch_done_d | // br
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ld_thrrdy | // load hit without spec
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ld_thrrdy | // load hit without spec
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exu_lop_done | // mul, div, win mgmt
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exu_lop_done | // mul, div, win mgmt
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fixedop_done | // rdsr, wrspr
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fixedop_done | // rdsr, wrspr
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killed_thrrdy | // ll op was anulled
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killed_thrrdy | // ll op was anulled
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retr_thr_wakeup | // retract cond compl
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retr_thr_wakeup | // retract cond compl
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flush_wake_w2 | // wake up after ecc
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flush_wake_w2 | // wake up after ecc
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fp_thrrdy | // fp completion
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fp_thrrdy | // fp completion
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sta_thrrdy | // sta to real memory
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sta_thrrdy | // sta to real memory
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trap_thrrdy); // trap
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trap_thrrdy); // trap
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// Imiss predicted ready
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// Imiss predicted ready
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assign pred_ifq_rdy = ifq_dtu_pred_rdy & {4{~atr_s}} & dtu_fcl_thr_active;
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assign pred_ifq_rdy = ifq_dtu_pred_rdy & {4{~atr_s}} & dtu_fcl_thr_active;
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assign imiss_thrrdy = pred_ifq_rdy | ifq_dtu_thrrdy;
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assign imiss_thrrdy = pred_ifq_rdy | ifq_dtu_thrrdy;
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// assign completion[0] = imiss_thrrdy & (~(wm_other | wm_stbwait) |
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// assign completion = imiss_thrrdy & (~(wm_other | wm_stbwait) |
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// other_thrrdy) | //see C1
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// other_thrrdy) | //see C1
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// other_thrrdy & (~(wm_imiss | wmi_nxt));
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// other_thrrdy & (~(wm_imiss | wmi_nxt));
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// assign completion[0] = (imiss_thrrdy & ~(wm_other | wm_stbwait) |
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// assign completion = (imiss_thrrdy & ~(wm_other | wm_stbwait) |
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// other_thrrdy & ~(wm_stbwait | wm_imiss) |
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// other_thrrdy & ~(wm_stbwait | wm_imiss) |
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// stb_retry & ~(wm_other | wm_imiss) |
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// stb_retry & ~(wm_other | wm_imiss) |
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// imiss_thrrdy & other_thrrdy & ~wm_stbwait |
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// imiss_thrrdy & other_thrrdy & ~wm_stbwait |
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// imiss_thrrdy & stb_retry & ~wm_other |
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// imiss_thrrdy & stb_retry & ~wm_other |
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// stb_retry & other_thrrdy & ~wm_imiss);
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// stb_retry & other_thrrdy & ~wm_imiss);
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assign completion[0] = ((imiss_thrrdy | ~wm_imiss) &
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assign completion = ((imiss_thrrdy | ~wm_imiss) &
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(other_thrrdy | ~wm_other) &
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(other_thrrdy | ~wm_other) &
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(stb_retry | ~wm_stbwait) &
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(stb_retry | ~wm_stbwait) &
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(wm_imiss | wm_other | wm_stbwait|wait_state));
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(wm_imiss | wm_other | wm_stbwait));
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// C1: should we do ~(wm_other | wmo_nxt)??
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// C1: should we do ~(wm_other | wmo_nxt)??
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// When an imiss is pending, we cannot be doing another fetch, so I
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// When an imiss is pending, we cannot be doing another fetch, so I
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// don't think so. It seems nice and symmetric to put it in
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// don't think so. It seems nice and symmetric to put it in
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// though, unfortunately this results in a timing problem on swc_s
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// though, unfortunately this results in a timing problem on swc_s
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// and trap
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// and trap
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assign wait_next=wbm_spc_stall|(wait_state & ~wbm_spc_resume);
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dffr wait_ff(.din(wait_next),.q(wait_state),.clk(clk),.rst(reset),.se(se),.si(),.so());
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assign completion[1]=completion[0];
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assign completion[2]=completion[0];
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assign completion[3]=completion[0];
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endmodule // sparc_ifu_thrcmpl
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endmodule // sparc_ifu_thrcmpl
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