// ========== Copyright Header Begin ==========================================
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// ========== Copyright Header Begin ==========================================
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//
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//
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// OpenSPARC T1 Processor File: sparc_mul_dp.v
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// OpenSPARC T1 Processor File: sparc_mul_dp.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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//
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// The above named program is free software; you can redistribute it and/or
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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// License version 2 as published by the Free Software Foundation.
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//
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//
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// The above named program is distributed in the hope that it will be
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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// General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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`ifdef SIMPLY_RISC_TWEAKS
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`define SIMPLY_RISC_SCANIN .si(0)
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`else
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`define SIMPLY_RISC_SCANIN .si()
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`endif
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//FPGA_SYN enables all FPGA related modifications
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//FPGA_SYN enables all FPGA related modifications
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`ifdef FPGA_SYN
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`define FPGA_SYN_CLK_EN
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`define FPGA_SYN_CLK_DFF
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`endif
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module sparc_mul_dp(
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module sparc_mul_dp(
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ecl_mul_rs1_data,
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ecl_mul_rs1_data,
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ecl_mul_rs2_data,
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ecl_mul_rs2_data,
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spu_mul_op1_data,
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spu_mul_op1_data,
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spu_mul_op2_data,
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spu_mul_op2_data,
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valid,
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valid,
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spick,
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spick,
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byp_sel,
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byp_sel,
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byp_imm,
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byp_imm,
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acc_imm,
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acc_imm,
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acc_actc2,
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acc_actc2,
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acc_actc3,
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acc_actc3,
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acc_actc5,
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acc_actc5,
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acc_reg_enb,
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acc_reg_enb,
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acc_reg_rst,
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acc_reg_rst,
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acc_reg_shf,
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acc_reg_shf,
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x2,
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x2,
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mul_data_out,
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mul_data_out,
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rst_l,
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rst_l,
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si,
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si,
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so,
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so,
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se,
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se,
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rclk
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rclk
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);
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);
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input [63:0] ecl_mul_rs1_data; // EXU mul operand 1
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input [63:0] ecl_mul_rs1_data; // EXU mul operand 1
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input [63:0] ecl_mul_rs2_data; // EXU mul operand 2
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input [63:0] ecl_mul_rs2_data; // EXU mul operand 2
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input [63:0] spu_mul_op1_data; // SPU mul operand 1
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input [63:0] spu_mul_op1_data; // SPU mul operand 1
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input [63:0] spu_mul_op2_data; // SPU mul operand 2
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input [63:0] spu_mul_op2_data; // SPU mul operand 2
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input valid; // begin cyc0 of MUL operation
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input valid; // begin cyc0 of MUL operation
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input spick; // Internal pick signals of exu, spu multiplier
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input spick; // Internal pick signals of exu, spu multiplier
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input byp_sel; // SPU bypass ACCUM[63:0] as operand
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input byp_sel; // SPU bypass ACCUM[63:0] as operand
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input byp_imm; // SPU bypss action from mout immediately
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input byp_imm; // SPU bypss action from mout immediately
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input acc_imm; // SPU accumlate from mout immediately
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input acc_imm; // SPU accumlate from mout immediately
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input acc_actc2, acc_actc3; // accumulate enable for LSB-32 and All-96
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input acc_actc2, acc_actc3; // accumulate enable for LSB-32 and All-96
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input acc_actc5; // accumulate enable for LSB-32 and All-96
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input acc_actc5; // accumulate enable for LSB-32 and All-96
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input acc_reg_enb; // ACCUM register enable
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input acc_reg_enb; // ACCUM register enable
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input acc_reg_rst; // ACCUM register reset
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input acc_reg_rst; // ACCUM register reset
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input acc_reg_shf; // ACCUM shift right 64-bit
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input acc_reg_shf; // ACCUM shift right 64-bit
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input x2; // for op1*op2*2
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input x2; // for op1*op2*2
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input rst_l; // system reset
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input rst_l; // system reset
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input si; // si
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input si; // si
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input se; // scan_enable
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input se; // scan_enable
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input rclk;
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input rclk;
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output so; // so
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output so; // so
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output [63:0] mul_data_out; // Multiplier outputs
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output [63:0] mul_data_out; // Multiplier outputs
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wire [63:0] mul_op1_d, mul_op2_d, bypreg;
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wire [63:0] mul_op1_d, mul_op2_d, bypreg;
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wire [63:32] mux1_reg, mux1_mou;
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wire [63:32] mux1_reg, mux1_mou;
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wire [96:0] mux2_reg, areg;
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wire [96:0] mux2_reg, areg;
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wire [135:0] mout, acc_reg_in, acc_reg;
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wire [135:0] mout, acc_reg_in, acc_reg;
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wire op2_s0, op2_s1, op2_s2;
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wire op2_s0, op2_s1, op2_s2;
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wire acc_reg_shf2, clk_enb1;
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wire acc_reg_shf2, clk_enb1;
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wire clk;
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wire clk;
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assign clk = rclk ;
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assign clk = rclk ;
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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////// op1 inputs mux between EXU and SPU
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////// op1 inputs mux between EXU and SPU
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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assign mul_op1_d = ({64{spick}} & spu_mul_op1_data) |
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assign mul_op1_d = ({64{spick}} & spu_mul_op1_data) |
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({64{~spick}} & ecl_mul_rs1_data );
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({64{~spick}} & ecl_mul_rs1_data );
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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////// op2 inputs mux between EXU, SPU and bypass from ACCUM register
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////// op2 inputs mux between EXU, SPU and bypass from ACCUM register
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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assign op2_s0 = ~spick;
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assign op2_s0 = ~spick;
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assign op2_s1 = spick & byp_sel ;
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assign op2_s1 = spick & byp_sel ;
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assign op2_s2 = spick & ~byp_sel ;
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assign op2_s2 = spick & ~byp_sel ;
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assign mul_op2_d = (op2_s0 & op2_s1)|(op2_s0 & op2_s2)|(op2_s1 & op2_s2) ? 64'hxx :
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assign mul_op2_d = (op2_s0 & op2_s1)|(op2_s0 & op2_s2)|(op2_s1 & op2_s2) ? 64'hxx :
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(op2_s0 ? ecl_mul_rs2_data :
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(op2_s0 ? ecl_mul_rs2_data :
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(op2_s1 ? bypreg :
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(op2_s1 ? bypreg :
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(op2_s2 ? spu_mul_op2_data : 64'hxx)
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(op2_s2 ? spu_mul_op2_data : 64'hxx)
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));
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));
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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////// Accumulate input muxes
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////// Accumulate input muxes
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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// MUX1: Pass acc_reg[31:0] at cyc2 of SPU accumulate, otherwise acc_reg[63:32]
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// MUX1: Pass acc_reg[31:0] at cyc2 of SPU accumulate, otherwise acc_reg[63:32]
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assign mux1_reg[63:32] = acc_actc2 ? acc_reg[31:0]
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assign mux1_reg[63:32] = acc_actc2 ? acc_reg[31:0]
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: acc_reg[63:32] ;
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: acc_reg[63:32] ;
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// Bypass mout[31:0] (mul core output) of MAC1 at cyc5 when the lower 32-bit
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// Bypass mout[31:0] (mul core output) of MAC1 at cyc5 when the lower 32-bit
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// are ready but not lateched into acc_reg yet.
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// are ready but not lateched into acc_reg yet.
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//
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//
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// MAC1: cyc1 |cyc2 |cyc3 | cyc4 | cyc5 | cyc6
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// MAC1: cyc1 |cyc2 |cyc3 | cyc4 | cyc5 | cyc6
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// | | | | mout[31:0] | acc_reg[128:0]
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// | | | | mout[31:0] | acc_reg[128:0]
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// | | | | bypass | latched out
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// | | | | bypass | latched out
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//
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//
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// MAC2: | cyc1 | cyc2 |
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// MAC2: | cyc1 | cyc2 |
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// | | ACCUM from |
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// | | ACCUM from |
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// | | mout[31:0] |
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// | | mout[31:0] |
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//
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//
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assign mux1_mou[63:32] = (acc_actc2 & acc_actc5) ? mout[31:0]
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assign mux1_mou[63:32] = (acc_actc2 & acc_actc5) ? mout[31:0]
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: mout[63:32] ;
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: mout[63:32] ;
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// MUX2: Immediate bypass from mout (output of mul core)
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// MUX2: Immediate bypass from mout (output of mul core)
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assign mux2_reg[96:0] = acc_imm ? {mout[128:64],mux1_mou[63:32]}
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assign mux2_reg[96:0] = acc_imm ? {mout[128:64],mux1_mou[63:32]}
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: {acc_reg[128:64],mux1_reg[63:32]};
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: {acc_reg[128:64],mux1_reg[63:32]};
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// Enable of accumulate reg input to multipler core
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// Enable of accumulate reg input to multipler core
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assign areg[96:32] = mux2_reg[96:32] & {65{acc_actc3}} ;
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assign areg[96:32] = mux2_reg[96:32] & {65{acc_actc3}} ;
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assign areg[31:0] = mux2_reg[31:0] & {32{(acc_actc3 | acc_actc2)}};
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assign areg[31:0] = mux2_reg[31:0] & {32{(acc_actc3 | acc_actc2)}};
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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////// Multiplier core connection
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////// Multiplier core connection
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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mul64 mulcore(.rs1_l (~mul_op1_d),
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mul64 mulcore(.rs1_l (~mul_op1_d),
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.rs2 (mul_op2_d),
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.rs2 (mul_op2_d),
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.valid (valid),
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.valid (valid),
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.areg (areg),
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.areg (areg),
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.accreg (acc_reg[135:129]),
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.accreg (acc_reg[135:129]),
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.x2 (x2),
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.x2 (x2),
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.out (mout),
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.out (mout),
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.rclk (clk),
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.rclk (clk),
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.si (),
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`SIMPLY_RISC_SCANIN,
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.so (),
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.so (),
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.se (se),
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.se (se),
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.mul_rst_l (rst_l),
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.mul_rst_l (rst_l),
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.mul_step (1'b1)
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.mul_step (1'b1)
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);
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);
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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///// ACCUM register and right shift muxes
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///// ACCUM register and right shift muxes
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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dff dffshf (.din (acc_reg_shf),
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dff_s dffshf (.din (acc_reg_shf),
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.clk (clk),
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.clk (clk),
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.q (acc_reg_shf2),
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.q (acc_reg_shf2),
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.se (se),
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.se (se),
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.si (),
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`SIMPLY_RISC_SCANIN,
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.so ()
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.so ()
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);
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);
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assign acc_reg_in = acc_reg_shf ? {64'b0,acc_reg[135:64]}
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assign acc_reg_in = acc_reg_shf ? {64'b0,acc_reg[135:64]}
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: mout ;
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: mout ;
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assign mul_data_out = acc_reg_shf2 ? acc_reg[63:0]
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assign mul_data_out = acc_reg_shf2 ? acc_reg[63:0]
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: mout[63:0] ;
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: mout[63:0] ;
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`ifdef FPGA_SYN_CLK_DFF
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dffre #(136) accum (.din (acc_reg_in),
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dffre_s #(136) accum (.din (acc_reg_in),
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.rst (acc_reg_rst),
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.rst (acc_reg_rst),
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.en (acc_reg_enb | acc_reg_rst), .clk(clk), //manually fixed
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.en (acc_reg_enb | acc_reg_rst), .clk(clk), //manually fixed
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.q (acc_reg),
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.q (acc_reg),
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.se (se),
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.se (se),
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.si (),
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`SIMPLY_RISC_SCANIN,
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.so ()
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.so ()
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);
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);
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`else
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dffr_s #(136) accum (.din (acc_reg_in),
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.rst (acc_reg_rst),
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.clk (clk_enb1),
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.q (acc_reg),
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.se (se),
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`SIMPLY_RISC_SCANIN,
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.so ()
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);
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`endif
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`ifdef FPGA_SYN_CLK_EN
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`else
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clken_buf ckbuf_1(.clk(clk_enb1), .rclk(clk), .enb_l(~(acc_reg_enb | acc_reg_rst)), .tmb_l(~se));
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`endif
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assign bypreg = byp_imm ? mout[63:0]
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assign bypreg = byp_imm ? mout[63:0]
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: acc_reg[63:0] ;
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: acc_reg[63:0] ;
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endmodule
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endmodule
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