#!/bin/bash
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#!/bin/bash
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set -e
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if ( (test $# != 1) || ((test $1 != "xst") && (test $1 != "fpga") && (test $1 != "dc")) ) then
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if ( (test $# != 1) || ((test $1 != "xst") && (test $1 != "fpga") && (test $1 != "dc")) ) then
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echo "Usage: $0 {xst|fpga|dc}"
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echo "Usage: $0 {xst|fpga|dc}"
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exit 1;
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exit 1
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fi
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fi
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test_var S1_ROOT
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test_var S1_ROOT
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echo -e "Synthesizing the design using $1"
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echo -e "Synthesizing the design using $1"
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mkdir -p $S1_ROOT/run/synth/$1
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mkdir -p $S1_ROOT/run/synth/$1
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cd $S1_ROOT/run/synth/$1
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cd $S1_ROOT/run/synth/$1
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rm -rf * .syn*
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rm -rf * .syn*
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if(test $1 == "xst") then
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if(test $1 == "xst") then
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xst -ifn $S1_ROOT/tools/src/build_xst.cmd -ofn synth.log
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xst -ifn $S1_ROOT/tools/src/build_xst.cmd -ofn synth.log
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#export TOP_LEVEL="s1_top"
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#export TOP_LEVEL="s1_top"
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#ngdbuild ${TOP_LEVEL}
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#ngdbuild ${TOP_LEVEL}
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#map -o ${TOP_LEVEL}_map.ncd ${TOP_LEVEL}
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#map -o ${TOP_LEVEL}_map.ncd ${TOP_LEVEL}
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#par -w -ol high ${TOP_LEVEL}_map.ncd ${TOP_LEVEL}.ncd
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#par -w -ol high ${TOP_LEVEL}_map.ncd ${TOP_LEVEL}.ncd
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#bitgen -g startupclk:Cclk -w ${TOP_LEVEL} ${TOP_LEVEL}.bit
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#bitgen -g startupclk:Cclk -w ${TOP_LEVEL} ${TOP_LEVEL}.bit
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#trce ${TOP_LEVEL} ${TOP_LEVEL}_map
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#trce ${TOP_LEVEL} ${TOP_LEVEL}_map
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fi
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fi
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if(test $1 == "fpga") then
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if(test $1 == "fpga") then
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iverilog -g1 -t xnf -o fpga.edif -c$FILELIST_FPGA 2>&1 | tee synth.log
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iverilog -g1 -t xnf -o fpga.edif -c$FILELIST_FPGA 2>&1 | tee synth.log
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fi
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fi
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if(test $1 == "dc") then
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if(test $1 == "dc") then
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mkdir work
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mkdir work
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ln -s -f ../../../tools/src/synopsys_dc.setup .synopsys_dc.setup
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ln -s -f ../../../tools/src/synopsys_dc.setup .synopsys_dc.setup
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dc_shell -tcl_mode -f $FILELIST_DC 2>&1 | tee synth.log
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dc_shell -tcl_mode -f $FILELIST_DC 2>&1 | tee synth.log
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fi
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fi
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echo -e "Synthesis with $1 done!"
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echo -e "Synthesis with $1 done!"
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