\documentclass{gqtekspec}
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\documentclass{gqtekspec}
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\usepackage{import}
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\usepackage{import}
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\usepackage{bytefield}
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\usepackage{bytefield}
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\project{CMod S6 SoC}
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\project{CMod S6 SoC}
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\title{Specification}
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\title{Specification}
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\author{Dan Gisselquist, Ph.D.}
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\author{Dan Gisselquist, Ph.D.}
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\email{dgisselq (at) opencores.org}
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\email{dgisselq (at) opencores.org}
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\revision{Rev.~0.2}
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\revision{Rev.~0.2}
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\begin{document}
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\begin{document}
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\pagestyle{gqtekspecplain}
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\pagestyle{gqtekspecplain}
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\titlepage
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\titlepage
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\begin{license}
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\begin{license}
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Copyright (C) \theyear\today, Gisselquist Technology, LLC
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Copyright (C) \theyear\today, Gisselquist Technology, LLC
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This project is free software (firmware): you can redistribute it and/or
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This project is free software (firmware): you can redistribute it and/or
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modify it under the terms of the GNU General Public License as published
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modify it under the terms of the GNU General Public License as published
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by the Free Software Foundation, either version 3 of the License, or (at
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by the Free Software Foundation, either version 3 of the License, or (at
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your option) any later version.
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your option) any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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for more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see \texttt{http://www.gnu.org/licenses/} for a copy.
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with this program. If not, see \texttt{http://www.gnu.org/licenses/} for a copy.
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\end{license}
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\end{license}
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\begin{revisionhistory}
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\begin{revisionhistory}
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0.1 & 4/22/2016 & Gisselquist & First Draft \\\hline
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0.1 & 4/22/2016 & Gisselquist & First Draft \\\hline
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\end{revisionhistory}
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\end{revisionhistory}
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% Revision History
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% Revision History
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% Table of Contents, named Contents
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% Table of Contents, named Contents
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\tableofcontents
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\tableofcontents
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\listoffigures
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\listoffigures
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\listoftables
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\listoftables
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\begin{preface}
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\begin{preface}
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The Zip CPU was built with the express purpose of being an area optimized,
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The Zip CPU was built with the express purpose of being an area optimized,
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32--bit FPGA soft processor.
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32--bit FPGA soft processor.
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The S6~SoC is designed to prove that the ZipCPU has met this goal.
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The S6~SoC is designed to prove that the ZipCPU has met this goal.
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\end{preface}
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\end{preface}
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\chapter{Introduction}
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\chapter{Introduction}
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\pagenumbering{arabic}
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\pagenumbering{arabic}
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\setcounter{page}{1}
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\setcounter{page}{1}
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This project is ongoing. Any and all files, to include this one, are subject
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This project is ongoing. Any and all files, to include this one, are subject
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to change without notice.
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to change without notice.
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This project comes from my desire to demonstrate the Zip CPU's utility in a
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This project comes from my desire to demonstrate the Zip CPU's utility in a
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challenging environment. The CMod~S6 board fits this role nicely.
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challenging environment. The CMod~S6 board fits this role nicely.
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\begin{enumerate}
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\begin{enumerate}
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\item The Spartan--6 LX4 FPGA is very limited in it's resources:
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\item The Spartan--6 LX4 FPGA is very limited in it's resources:
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It only has 2,400 look--up tables (LUTs), and can only support
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It only has 2,400 look--up tables (LUTs), and can only support
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a 4,096~Word RAM memory (16 kB).
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a 4,096~Word RAM memory (16 kB).
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\item With only 4kW RAM, the majority of any program will need to be placed into
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\item With only 4kW RAM, the majority of any program will need to be placed into
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and run from flash. (The chip will actually support more, just not
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and run from flash. (The chip will actually support more, just not
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8k RAM.)
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8k RAM.)
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\item While the chip has enough area for the CPU, it doesn't have enough area
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\item While the chip has enough area for the CPU, it doesn't have enough area
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to include the CPU and \ldots write access to the flash, debug access,
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to include the CPU and \ldots write access to the flash, debug access,
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wishbone command access from the UART, pipelined CPU operations, and
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wishbone command access from the UART, pipelined CPU operations, and
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more. Other solutions will need to be found.
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more. Other solutions will need to be found.
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\end{enumerate}
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\end{enumerate}
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Of course, if someone just wants the functionality of a small, cheap, CPU,
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Of course, if someone just wants the functionality of a small, cheap, CPU,
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this project does not fit that role very well. While the S6 is not very
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this project does not fit that role very well. While the S6 is not very
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expensive, it is still an order of magnitude greater than it's CPU competitors
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expensive, it is still an order of magnitude greater than it's CPU competitors
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in price. This includes such CPU's as the Raspberry Pi Zero, or even the
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in price. This includes such CPU's as the Raspberry Pi Zero, or even the
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TeensyLC.
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TeensyLC.
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If, on the other hand, what you want is a small, cheap, CPU that can be embedded
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If, on the other hand, what you want is a small, cheap, CPU that can be embedded
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within an FPGA without using too much of the FPGA's resources, this project
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within an FPGA without using too much of the FPGA's resources, this project
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will demonstrate that utility and possibility. Alternatively, if you wish to
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will demonstrate that utility and possibility. Alternatively, if you wish to
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study how to get a CPU to work in a small, constrained environment, this project
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study how to get a CPU to work in a small, constrained environment, this project
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may be what you are looking for.
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may be what you are looking for.
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\chapter{Architecture}
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\chapter{Architecture}
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Fig.~\ref{fig:architecture}
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Fig.~\ref{fig:architecture}
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\begin{figure}\begin{center}
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\begin{figure}\begin{center}
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\includegraphics[width=5in]{../gfx/s6bones.eps}
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\includegraphics[width=5in]{../gfx/s6bones.eps}
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\caption{CMod S6 SoC Architecture: ZipCPU and
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\caption{CMod S6 SoC Architecture: ZipCPU and
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Peripherals}\label{fig:architecture}
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Peripherals}\label{fig:architecture}
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\end{center}\end{figure}
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\end{center}\end{figure}
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shows the basic internal architecture of the S6~SoC. In summary, it consists of a CPU
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shows the basic internal architecture of the S6~SoC. In summary, it consists of a CPU
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coupled with a variety of peripherals for the purpose of controlling the
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coupled with a variety of peripherals for the purpose of controlling the
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external peripherals of the S6: flash, LEDs, buttons, and GPIO. External
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external peripherals of the S6: flash, LEDs, buttons, and GPIO. External
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devices may also be added on, such as an audio device, an external serial
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devices may also be added on, such as an audio device, an external serial
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port, an external keypad, and an external display. All of these devices
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port, an external keypad, and an external display. All of these devices
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are then available for the CPU to interact with.
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are then available for the CPU to interact with.
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If you are familiar with the Zip CPU, you'll notice this architecture provides
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If you are familiar with the Zip CPU, you'll notice this architecture provides
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no access to the Zip CPU debug port. There simply wasn't enough room on the
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no access to the Zip CPU debug port. There simply wasn't enough room on the
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device. Debugging the ZipCPU will instead need to take place via other means,
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device. Debugging the ZipCPU will instead need to take place via other means,
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such as dumping all registers and/or memory to the serial port on any reboot.
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such as dumping all registers and/or memory to the serial port on any reboot.
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Further, the ZipCPU has no ability to write to flash memory. For this reason,
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Further, the ZipCPU has no ability to write to flash memory. For this reason,
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there exists an alternate CMod S6~SoC architecture, as shown in
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there exists an alternate CMod S6~SoC architecture, as shown in
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Fig.~\ref{fig:altarchitecture}.
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Fig.~\ref{fig:altarchitecture}.
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\begin{figure}\begin{center}
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\begin{figure}\begin{center}
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\includegraphics[width=5in]{../gfx/altbones.eps}
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\includegraphics[width=5in]{../gfx/altbones.eps}
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\caption{Alternate CMod S6 SoC Architecture: Peripherals, with no
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\caption{Alternate CMod S6 SoC Architecture: Peripherals, with no
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CPU}\label{fig:altarchitecture}
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CPU}\label{fig:altarchitecture}
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\end{center}\end{figure}
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\end{center}\end{figure}
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Using this alternate architecture, it should be possible to test the peripherals
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Using this alternate architecture, it should be possible to test the peripherals
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and program the flash memory. Both architectures may be loaded into the flash,
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and program the flash memory. Both architectures may be loaded into the flash,
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together with the programming code for the Zip CPU.
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together with the programming code for the Zip CPU.
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The basic approach is simple: up and until the software works, the S6 will
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The basic approach is simple: up and until the software works, the S6 will
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power up into the alternate architecture of Fig.~\ref{fig:altarchitecture}.
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power up into the alternate architecture of Fig.~\ref{fig:altarchitecture}.
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While in this state, the flash may be examined and programmed. Once complete,
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While in this state, the flash may be examined and programmed. Once complete,
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a UART command to the ICAPE port will tell the S6 to load the (primary)
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a UART command to the ICAPE port will tell the S6 to load the (primary)
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FPGA configuration from an alternate flash location. This alternate location
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FPGA configuration from an alternate flash location. This alternate location
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will contain a configuration image containing the CPU. The CPU will then begin
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will contain a configuration image containing the CPU. The CPU will then begin
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following the instructions given to it from the flash.
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following the instructions given to it from the flash.
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\chapter{Operation}
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\chapter{Operation}
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\chapter{Registers}
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\chapter{Registers}
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There are several address regions on the S6~SoC, as shown in
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There are several address regions on the S6~SoC, as shown in
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Tbl.~\ref{tbl:memregions}.
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Tbl.~\ref{tbl:memregions}.
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\begin{table}[htbp]
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\begin{table}[htbp]
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\begin{center}\begin{tabular}{|p{0.75in}|p{0.75in}|p{0.5in}|p{3.0in}|}\hline
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\begin{center}\begin{tabular}{|p{0.75in}|p{0.75in}|p{0.5in}|p{3.0in}|}\hline
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\rowcolor[gray]{0.85} Start & End & & Purpose \\\hline\hline
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\rowcolor[gray]{0.85} Start & End & & Purpose \\\hline\hline
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\scalebox{0.9}{\tt 0x000100} & \scalebox{0.9}{\tt 0x000107} & R/W & Peripheral I/O Control \\\hline
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\scalebox{0.9}{\tt 0x000100} & \scalebox{0.9}{\tt 0x000107} & R/W & Peripheral I/O Control \\\hline
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\scalebox{0.9}{\tt 0x000200} & \scalebox{0.9}{\tt 0x000201} & R/(W) & Debugging scope\\\hline
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\scalebox{0.9}{\tt 0x000200} & \scalebox{0.9}{\tt 0x000201} & R/(W) & Debugging scope\\\hline
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\scalebox{0.9}{\tt 0x000400} & \scalebox{0.9}{\tt 0x00043f} & R/W & Internal Configuration Access Port\\\hline
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\scalebox{0.9}{\tt 0x000400} & \scalebox{0.9}{\tt 0x00043f} & R/W & Internal Configuration Access Port\\\hline
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\scalebox{0.9}{\tt 0x000800} & \scalebox{0.9}{\tt 0x000803} & R/W & RTC Clock (if present)\\\hline
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\scalebox{0.9}{\tt 0x000800} & \scalebox{0.9}{\tt 0x000803} & R/W & RTC Clock (if present)\\\hline
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\scalebox{0.9}{\tt 0x002000} & \scalebox{0.9}{\tt 0x002fff} & R/W & 16kB On-Chip Block RAM \\\hline
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\scalebox{0.9}{\tt 0x002000} & \scalebox{0.9}{\tt 0x002fff} & R/W & 16kB On-Chip Block RAM \\\hline
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\scalebox{0.9}{\tt 0x400000} & \scalebox{0.9}{\tt 0x7fffff} & R & 16~MB SPI Flash memory\\\hline
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\scalebox{0.9}{\tt 0x400000} & \scalebox{0.9}{\tt 0x7fffff} & R & 16~MB SPI Flash memory\\\hline
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\end{tabular}
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\end{tabular}
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\caption{Address Regions}\label{tbl:memregions}
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\caption{Address Regions}\label{tbl:memregions}
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\end{center}\end{table}
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\end{center}\end{table}
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In general, the address regions that are made up of RAM or flash act like
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In general, the address regions that are made up of RAM or flash act like
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memory. The RAM can be read and written, and the flash acts like read only
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memory. The RAM can be read and written, and the flash acts like read only
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memory.
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memory.
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This isn't quite so true with the other address regions. Accessing the I/O
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This isn't quite so true with the other address regions. Accessing the I/O
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region, while it may be read/write, may have side-effects. For example, reading
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region, while it may be read/write, may have side-effects. For example, reading
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from the debugging scope device's data port will read a word from the scope's
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from the debugging scope device's data port will read a word from the scope's
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buffer and advance the buffer pointer.
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buffer and advance the buffer pointer.
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\section{Debugging Scope}
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\section{Debugging Scope}
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The debugging scope consists of two registers, a control register and a data
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The debugging scope consists of two registers, a control register and a data
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register. It needs to be internally wired to 32--wires, internal to the S6
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register. It needs to be internally wired to 32--wires, internal to the S6
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SoC, that will be of interest later. For further details on how to configure
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SoC, that will be of interest later. For further details on how to configure
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and use this scope, please see the {\tt WBSCOPE} project on OpenCores.
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and use this scope, please see the {\tt WBSCOPE} project on OpenCores.
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\section{Internal Configuration Access Port}
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\section{Internal Configuration Access Port}
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The Internal Configuration Access Port (ICAP) provides access to the internal
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The Internal Configuration Access Port (ICAP) provides access to the internal
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configuration details of the FPGA. This access was designed so as to provide
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configuration details of the FPGA. This access was designed so as to provide
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the CPU with the capability to command a different FPGA load. In particular,
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the CPU with the capability to command a different FPGA load. In particular,
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the code in Fig.~\ref{fig:reload} should reconfigure the FPGA from any given
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the code in Fig.~\ref{fig:reload} should reconfigure the FPGA from any given
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Quad SPI {\tt address}.\footnote{According to Xilinx's technical support, this
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Quad SPI {\tt address}.\footnote{According to Xilinx's technical support, this
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will only work if the JTAG port is not busy.}
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will only work if the JTAG port is not busy.}
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\begin{figure}\begin{center}\begin{tabbing}
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\begin{figure}\begin{center}\begin{tabbing}
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{\tt warmboot(uint32 address) \{} \\
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{\tt warmboot(uint32 address) \{} \\
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\hbox to 0.25in{}\={\tt uint32\_t *icape6 = (volatile uint32\_t *)0x{\em <ICAPE port address>};}\\
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\hbox to 0.25in{}\={\tt uint32\_t *icape6 = (volatile uint32\_t *)0x{\em <ICAPE port address>};}\\
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\>{\tt icape6[13] = (address<<2)\&0x0ffff;}\\
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\>{\tt icape6[13] = (address<<2)\&0x0ffff;}\\
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\>{\tt icape6[14] = ((address>>14)\&0x0ff)|((0x03)<<8);}\\
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\>{\tt icape6[14] = ((address>>14)\&0x0ff)|((0x03)<<8);}\\
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\>{\tt icape6[4] = 14;}\\
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\>{\tt icape6[4] = 14;}\\
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\>{\em // The CMod~S6 is now reconfiguring itself from the new address.}\\
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\>{\em // The CMod~S6 is now reconfiguring itself from the new address.}\\
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\>{\em // If all goes well, this routine will never return.}\\
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\>{\em // If all goes well, this routine will never return.}\\
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{\tt \}}
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{\tt \}}
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\end{tabbing}
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\end{tabbing}
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\caption{Spartan--6 ICAPE Usage}\label{fig:reload}
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\caption{Spartan--6 ICAPE Usage}\label{fig:reload}
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\end{center}\end{figure}
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\end{center}\end{figure}
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For further details, please see either the {\tt WBICAPETWO} project on OpenCores
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For further details, please see either the {\tt WBICAPETWO} project on OpenCores
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as well as Xilinx's ``Spartan-6 FPGA Configuration User Guide''.
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as well as Xilinx's ``Spartan-6 FPGA Configuration User Guide''.
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\section{Real--Time Clock}
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\section{Real--Time Clock}
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The Real Time Clock will be included if there is enough area to support it.
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The Real Time Clock will be included if there is enough area to support it.
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The four registers correspond to a clock, a timer, a stopwatch, and an alarm.
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The four registers correspond to a clock, a timer, a stopwatch, and an alarm.
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If space is tight, the timer and stopwatch, or indeed the entire clock, may be
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If space is tight, the timer and stopwatch, or indeed the entire clock, may be
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removed from the design. For further details regarding how to set and use this
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removed from the design. For further details regarding how to set and use this
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clock, please see the {\tt RTCCLOCK} project on OpenCores.
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clock, please see the {\tt RTCCLOCK} project on OpenCores.
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\section{I/O Peripherals}
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\section{I/O Peripherals}
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Tbl.~\ref{tbl:ioregs}
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Tbl.~\ref{tbl:ioregs}
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\begin{table}[htbp]
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\begin{table}[htbp]
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\begin{center}\begin{reglist}
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\begin{center}\begin{reglist}
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PIC &\scalebox{0.8}{\tt 0x0100} & 32 & R/W & Interrupt Controller \\\hline
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PIC &\scalebox{0.8}{\tt 0x0100} & 32 & R/W & Interrupt Controller \\\hline
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BUSERR &\scalebox{0.8}{\tt 0x0101} & 32 & R & Last Bus Error Address\\\hline
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BUSERR &\scalebox{0.8}{\tt 0x0101} & 32 & R & Last Bus Error Address\\\hline
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TIMA &\scalebox{0.8}{\tt 0x0102} & 32 & R/W & ZipTimer A\\\hline
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TIMA &\scalebox{0.8}{\tt 0x0102} & 32 & R/W & ZipTimer A\\\hline
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TIMB &\scalebox{0.8}{\tt 0x0103} & 32 & R/W & ZipTimer B\\\hline
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TIMB &\scalebox{0.8}{\tt 0x0103} & 32 & R/W & ZipTimer B\\\hline
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PWM &\scalebox{0.8}{\tt 0x0104} & 32 & R/W & PWM Audio Controller\\\hline
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PWM &\scalebox{0.8}{\tt 0x0104} & 32 & R/W & PWM Audio Controller\\\hline
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KYPAD &\scalebox{0.8}{\tt 0x0105} & 32 & R/W & Special Purpose I/O, Keypad, LED Controller \\\hline
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KYPAD &\scalebox{0.8}{\tt 0x0105} & 32 & R/W & Special Purpose I/O, Keypad, LED Controller \\\hline
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GPIO &\scalebox{0.8}{\tt 0x0106} & 32 & R/W & GPIO Controller \\\hline
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GPIO &\scalebox{0.8}{\tt 0x0106} & 32 & R/W & GPIO Controller \\\hline
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UART &\scalebox{0.8}{\tt 0x0107} & 32 & R/W & UART data\\\hline
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UART &\scalebox{0.8}{\tt 0x0107} & 32 & R/W & UART data\\\hline
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\end{reglist}
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\end{reglist}
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\caption{I/O Peripheral Registers}\label{tbl:ioregs}
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\caption{I/O Peripheral Registers}\label{tbl:ioregs}
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\end{center}\end{table}
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\end{center}\end{table}
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shows the addresses of various I/O peripherals included as part of the SoC.
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shows the addresses of various I/O peripherals included as part of the SoC.
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|
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The interrupt controller is identical to the one found with the ZipSystem.
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The interrupt controller is identical to the one found with the ZipSystem.
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Please read the ZipSystem documentation for how to control this.
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Please read the ZipSystem documentation for how to control this.
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The Bus Error peripheral simply records the address of the last bus error.
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The Bus Error peripheral simply records the address of the last bus error.
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This can be useful when debugging. While the peripheral may only be read,
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This can be useful when debugging. While the peripheral may only be read,
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setting it is really as easy as creating a bus error and trapping the result.
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setting it is really as easy as creating a bus error and trapping the result.
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The two ZipTimer's are ZipSystem timer's, placed onto this peripheral bus.
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The two ZipTimer's are ZipSystem timer's, placed onto this peripheral bus.
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They are available for the CPU to use. Common uses might include I2C or SPI
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They are available for the CPU to use. Common uses might include I2C or SPI
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speed control, or multi--tasking task-swap control. For further details, please
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speed control, or multi--tasking task-swap control. For further details, please
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see the ZipSystem documentation.
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see the ZipSystem documentation.
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Audio Controller
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Audio Controller
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Register {\tt KYPAD}, as shown in Fig.~\ref{fig:spioreg},
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Register {\tt KYPAD}, as shown in Fig.~\ref{fig:spioreg},
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\begin{figure}\begin{center}
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\begin{figure}\begin{center}
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\begin{bytefield}[endianness=big]{32}
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\begin{bytefield}[endianness=big]{32}
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\bitheader{0-31} \\
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\bitheader{0-31} \\
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\begin{leftwordgroup}{Read}\bitbox[lrt]{16}{Zeros}
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\begin{leftwordgroup}{Read}\bitbox[lrt]{16}{Zeros}
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\bitbox[lrt]{4}{Kpad}
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\bitbox[lrt]{4}{Kpad}
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\bitbox[lrt]{4}{Kpad}
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\bitbox[lrt]{4}{Kpad}
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\bitbox[lrt]{2}{00}
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\bitbox[lrt]{2}{00}
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\bitbox[lrt]{2}{Btn}
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\bitbox[lrt]{2}{Btn}
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\bitbox[lrt]{4}{LED} \\
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\bitbox[lrt]{4}{LED} \\
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\bitbox[lrb]{16}{}
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\bitbox[lrb]{16}{}
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\bitbox[lrb]{4}{Col Out}
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\bitbox[lrb]{4}{Col Out}
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\bitbox[lrb]{4}{Row In}
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\bitbox[lrb]{4}{Row In}
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\bitbox[lrb]{2}{}
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\bitbox[lrb]{2}{}
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\bitbox[lrb]{2}{}
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\bitbox[lrb]{2}{}
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\bitbox[lrb]{4}{}\end{leftwordgroup} \\
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\bitbox[lrb]{4}{}\end{leftwordgroup} \\
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\begin{leftwordgroup}{Write}\bitbox[lrt]{16}{Ignored}
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\begin{leftwordgroup}{Write}\bitbox[lrt]{16}{Ignored}
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\bitbox[lrt]{4}{Col}
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\bitbox[lrt]{4}{Col}
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\bitbox[lrt]{4}{Col}
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\bitbox[lrt]{4}{Col}
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\bitbox[lrt]{4}{LED}
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\bitbox[lrt]{4}{LED}
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\bitbox[lrt]{4}{LED} \\
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\bitbox[lrt]{4}{LED} \\
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\bitbox[lrb]{16}{}
|
\bitbox[lrb]{16}{}
|
\bitbox[lrb]{4}{Out}
|
\bitbox[lrb]{4}{Out}
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\bitbox[lrb]{4}{Enable}
|
\bitbox[lrb]{4}{Enable}
|
\bitbox[lrb]{4}{Enable}
|
\bitbox[lrb]{4}{Enable}
|
\bitbox[lrb]{4}{}\end{leftwordgroup} \\
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\bitbox[lrb]{4}{}\end{leftwordgroup} \\
|
\end{bytefield}
|
\end{bytefield}
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\caption{SPIO Control Register}\label{fig:spioreg}
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\caption{SPIO Control Register}\label{fig:spioreg}
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\end{center}\end{figure}
|
\end{center}\end{figure}
|
is a Special Purpose Input/Output (SPIO) register. It is
|
is a Special Purpose Input/Output (SPIO) register. It is
|
designed to control the on-board LED's, buttons, and keypad. Upon any read,
|
designed to control the on-board LED's, buttons, and keypad. Upon any read,
|
the register reads the current state of the keypad column output, the keypad
|
the register reads the current state of the keypad column output, the keypad
|
row input, the buttons and the LED's. Writing is more difficult, in order to
|
row input, the buttons and the LED's. Writing is more difficult, in order to
|
make certain that parts of these registers can be modified atomically.
|
make certain that parts of these registers can be modified atomically.
|
Specifically, to change an LED, write the new value as well as a `1' to the
|
Specifically, to change an LED, write the new value as well as a `1' to the
|
corresponding LED change enable bit. The same goes for the keypad column
|
corresponding LED change enable bit. The same goes for the keypad column
|
output, a `1' needs to be written to the change enable bit in order for a
|
output, a `1' needs to be written to the change enable bit in order for a
|
new value to be accepted.
|
new value to be accepted.
|
|
|
The controller will generate a keypad interrupt whenever any row input is
|
The controller will generate a keypad interrupt whenever any row input is
|
zero, and a button interrupt whenever any button value is a one.
|
zero, and a button interrupt whenever any button value is a one.
|
|
|
The General Purpose Input and Output (GPIO) control register, shown in
|
The General Purpose Input and Output (GPIO) control register, shown in
|
Fig.~\ref{fig:gpioreg},
|
Fig.~\ref{fig:gpioreg},
|
\begin{figure}\begin{center}
|
\begin{figure}\begin{center}
|
\begin{bytefield}[endianness=big]{32}
|
\begin{bytefield}[endianness=big]{32}
|
\bitheader{0-31} \\
|
\bitheader{0-31} \\
|
\bitbox[lrtb]{16}{Current Input Vals (x16)}\bitbox[lrt]{16}{Current Output} \\
|
\bitbox[lrtb]{16}{Current Input Vals (x16)}\bitbox[lrt]{16}{Current Output} \\
|
\bitbox[lrtb]{16}{Output Change Enable}\bitbox[lrb]{16}{Values (16-outs)}
|
\bitbox[lrtb]{16}{Output Change Enable}\bitbox[lrb]{16}{Values (16-outs)}
|
\end{bytefield}
|
\end{bytefield}
|
\caption{GPIO Control Register}\label{fig:gpioreg}
|
\caption{GPIO Control Register}\label{fig:gpioreg}
|
\end{center}\end{figure}
|
\end{center}\end{figure}
|
is quite simple to use: when read, the top 16--bits indicate
|
is quite simple to use: when read, the top 16--bits indicate
|
the value of the 16--input GPIO pins, whereas the bottom 16--bits indicate
|
the value of the 16--input GPIO pins, whereas the bottom 16--bits indicate
|
the value being placed on the 16--output GPIO pins. To change a GPIO pin,
|
the value being placed on the 16--output GPIO pins. To change a GPIO pin,
|
write the new pins value to this register, together with setting the
|
write the new pins value to this register, together with setting the
|
corresponding pin in the upper 16--bits. For example, to set output pin 0,
|
corresponding pin in the upper 16--bits. For example, to set output pin 0,
|
write a {\tt 0x010001} to the GPIO device. To clear output pin 0, write a
|
write a {\tt 0x010001} to the GPIO device. To clear output pin 0, write a
|
{\tt 0x010000}. This makes it possible to adjust some output pins independent
|
{\tt 0x010000}. This makes it possible to adjust some output pins independent
|
of the others.
|
of the others.
|
|
|
The GPIO controller, like the keypad or SPIO controller, will also generate
|
The GPIO controller, like the keypad or SPIO controller, will also generate
|
an interrupt. The GPIO interrupt is generated whenever a GPIO input line
|
an interrupt. The GPIO interrupt is generated whenever a GPIO input line
|
changes.
|
changes.
|
|
|
Of the 16 GPIO inputs and the 16 GPIO outputs, two lines have been taken for
|
Of the 16 GPIO inputs and the 16 GPIO outputs, two lines have been taken for
|
I2C support. GPIO line zero, for both input and output, is an I2C data line,
|
I2C support. GPIO line zero, for both input and output, is an I2C data line,
|
and GPIO line one is an I2C clock line. If the output of either of these
|
and GPIO line one is an I2C clock line. If the output of either of these
|
lines is set to zero, the GPIO controller will drive the line. Otherwise,
|
lines is set to zero, the GPIO controller will drive the line. Otherwise,
|
the line is pulled up with a weak resistor so that other devices may
|
the line is pulled up with a weak resistor so that other devices may
|
pull it low. If either line is low, when the output control bit is high,
|
pull it low. If either line is low, when the output control bit is high,
|
it is an indicator that another device is sending data across these wires.
|
it is an indicator that another device is sending data across these wires.
|
|
|
Moving on to the UART \ldots
|
Moving on to the UART \ldots
|
although the UART module within the S6~SoC is highly configurable, as built
|
although the UART module within the S6~SoC is highly configurable, as built
|
the UART can only handle 9600~Baud, 8--data bits, no parity, and one stop bit.
|
the UART can only handle 9600~Baud, 8--data bits, no parity, and one stop bit.
|
There is a single byte data buffer, so reading from the port has a real--time
|
There is a single byte data buffer, so reading from the port has a real--time
|
requirement associated with it.
|
requirement associated with it.
|
Attempts to read from this port will either return an 8--bit data value from
|
Attempts to read from this port will either return an 8--bit data value from
|
the port, or if no values are available it will return an {\tt 0x0100}
|
the port, or if no values are available it will return an {\tt 0x0100}
|
indicating that fact. In a similar fashion, writes to this port will send
|
indicating that fact. In a similar fashion, writes to this port will send
|
the lower 8--bits of the write out the serial port. If the port is already
|
the lower 8--bits of the write out the serial port. If the port is already
|
busy, a single byte will be buffered.
|
busy, a single byte will be buffered.
|
|
|
\chapter{Clocks}
|
\chapter{Clocks}
|
|
|
The S6~SoC is designed to run off of one master clock. This clock is derived
|
The S6~SoC is designed to run off of one master clock. This clock is derived
|
from the 8~MHz input clock on the board, by multiplying it up to 80~MHz.
|
from the 8~MHz input clock on the board, by multiplying it up to 80~MHz.
|
|
|
\chapter{IO Ports}
|
\chapter{IO Ports}
|
|
|
See Table.~\ref{tbl:ioports}.
|
See Table.~\ref{tbl:ioports}.
|
\begin{table}[htbp]
|
\begin{table}[htbp]
|
\begin{center}
|
\begin{center}
|
\begin{portlist}
|
\begin{portlist}
|
i\_clk\_8mhz & 1 & Input & Clock\\\hline
|
i\_clk\_8mhz & 1 & Input & Clock\\\hline
|
o\_qspi\_cs\_n & 1 & Output & Quad SPI Flash chip select\\\hline
|
o\_qspi\_cs\_n & 1 & Output & Quad SPI Flash chip select\\\hline
|
o\_qspi\_sck & 1 & Output & Quad SPI Flash clock\\\hline
|
o\_qspi\_sck & 1 & Output & Quad SPI Flash clock\\\hline
|
io\_qspi\_dat & 4 & Input/Output & Four-wire SPI flash data bus\\\hline
|
io\_qspi\_dat & 4 & Input/Output & Four-wire SPI flash data bus\\\hline
|
i\_btn & 2 & Input & Inputs from the two on-board push-buttons\\\hline
|
i\_btn & 2 & Input & Inputs from the two on-board push-buttons\\\hline
|
o\_led & 4 & Output & Outputs controlling the four on-board LED's\\\hline
|
o\_led & 4 & Output & Outputs controlling the four on-board LED's\\\hline
|
o\_pwm & 1 & Output & Audio output, via pulse width modulator\\\hline
|
o\_pwm & 1 & Output & Audio output, via pulse width modulator\\\hline
|
\multicolumn{2}{|l|}{o\_pwm\_shutdown\_n, 1}& Output & Audio output shutdown control\\\hline
|
\multicolumn{2}{|l|}{o\_pwm\_shutdown\_n, 1}& Output & Audio output shutdown control\\\hline
|
o\_pwm\_gain & 1 & Output & Audio output 20~dB gain enable\\\hline
|
o\_pwm\_gain & 1 & Output & Audio output 20~dB gain enable\\\hline
|
i\_uart & 1 & Input & UART receive input\\\hline
|
i\_uart & 1 & Input & UART receive input\\\hline
|
o\_uart & 1 & Output & UART transmit output\\\hline
|
o\_uart & 1 & Output & UART transmit output\\\hline
|
i\_uart\_cts & 1 & Input & \\\hline
|
i\_uart\_cts & 1 & Input & \\\hline
|
o\_uart\_rts & 1 & Output & \\\hline
|
o\_uart\_rts & 1 & Output & \\\hline
|
i\_kp\_row & 4 & Output & Four wires to activate the four rows of the keypad\\\hline
|
i\_kp\_row & 4 & Output & Four wires to activate the four rows of the keypad\\\hline
|
o\_kp\_col & 4 & Output & Return four wires, from the keypads columns \\\hline
|
o\_kp\_col & 4 & Output & Return four wires, from the keypads columns \\\hline
|
i\_gpio & 14 & Output & General purpose logic input lines\\\hline
|
i\_gpio & 14 & Output & General purpose logic input lines\\\hline
|
o\_gpio & 14 & Output & General purpose logic output lines\\\hline
|
o\_gpio & 14 & Output & General purpose logic output lines\\\hline
|
io\_scl & 1 & Input/Output & I2C clock port\\\hline
|
io\_scl & 1 & Input/Output & I2C clock port\\\hline
|
io\_sda & 1 & Input/Output & I2C data port\\\hline
|
io\_sda & 1 & Input/Output & I2C data port\\\hline
|
\end{portlist}
|
\end{portlist}
|
\caption{List of IO ports}\label{tbl:ioports}
|
\caption{List of IO ports}\label{tbl:ioports}
|
\end{center}\end{table}
|
\end{center}\end{table}
|
|
|
|
\begin{table}
|
|
\begin{center}
|
|
\includegraphics[height=7in]{../gfx/pinout.eps}
|
|
\caption{Physical Locations of Device I/O Ports}\label{tbl:physicalio}
|
|
\end{center}\end{table}
|
% Appendices
|
% Appendices
|
% Index
|
% Index
|
\end{document}
|
\end{document}
|
|
|
|
|
|
|