/****************************************************************************
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/****************************************************************************
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sbd_shifter_left2
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sbd_shifter_left2
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- shift register - shifts left - towards MSB - 2 bits
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- shift register - shifts left - towards MSB - 2 bits
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Copyright (C) 2005 Samuel Brown
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Copyright (C) 2005 Samuel Brown
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sam.brown@sbdesign.org
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sam.brown@sbdesign.org
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This library is free software; you can redistribute it and/or
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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****************************************************************************/
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****************************************************************************/
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module sbd_shifter_left2 (SIN,PIN,LOAD,RST,SHIFT,CLK,SOUT,POUT);
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module sbd_shifter_left2 (SIN,PIN,LOAD,RST,SHIFT,CLK,SOUT,POUT);
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parameter bitlength = 24;
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parameter bitlength = 24;
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input [1:0] SIN;
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input [1:0] SIN;
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input [bitlength-1:0] PIN;
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input [bitlength-1:0] PIN;
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input LOAD;
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input LOAD;
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input RST;
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input RST;
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input SHIFT;
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input SHIFT;
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input CLK;
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input CLK;
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output wire [1:0] SOUT;
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output wire [1:0] SOUT;
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output wire [bitlength-1:0] POUT;
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output wire [bitlength-1:0] POUT;
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reg [bitlength-1:0] writeData, readData;
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reg [bitlength-1:0] writeData, readData;
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assign POUT = readData;
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assign POUT = readData;
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assign SOUT = readData[bitlength-1:bitlength-2];
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assign SOUT = readData[bitlength-1:bitlength-2];
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always @ (posedge CLK)
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always @ (posedge CLK)
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begin:shiftreg
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begin:shiftreg
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if(RST) readData <= 0;
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if(RST) readData <= 0;
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else if(SHIFT | LOAD) readData <= writeData;
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else if(SHIFT | LOAD) readData <= writeData;
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end
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end
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always @ (readData, SIN, PIN, LOAD)
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always @ (readData, SIN, PIN, LOAD)
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begin:shiftmux
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begin:shiftmux
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if(LOAD) writeData = PIN;
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if(LOAD) writeData = PIN;
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else writeData = { readData[bitlength-3:0], SIN };
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else writeData = { readData[bitlength-3:0], SIN };
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end
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end
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endmodule
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endmodule
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