/****************************************************************************
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/****************************************************************************
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sbd_sqrt_fp
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sbd_sqrt_fp
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|
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- square root function for single or double precisons ieee 754
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- square root function for single or double precisons ieee 754
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floating-point numbers
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floating-point numbers
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This core is capable of handling single or double precision floating-
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This core is capable of handling single or double precision floating-
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poing numbers. For single precision, set the bitlength parameter to 32;
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poing numbers. For single precision, set the bitlength parameter to 32;
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for double precision, set the bitlength parameter to 64. The algorithm
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for double precision, set the bitlength parameter to 64. The algorithm
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used is iterative and will take 52 clock cycles for single precision and
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used is iterative and will take 52 clock cycles for single precision and
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110 clock cycles for double precision. The sign bit is simply passed
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110 clock cycles for double precision. The sign bit is simply passed
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through from input to output, so if given negative input, this core
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through from input to output, so if given negative input, this core
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will produce a negative output corresponding to -1 * sqrt(|input|).
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will produce a negative output corresponding to -1 * sqrt(|input|).
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Ports: - all signals are active high
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Ports: - all signals are active high
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input [bitlength-1:0] D_IN; // single or double precison input
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input [bitlength-1:0] D_IN; // single or double precison input
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input VAL_IN; // Assert VAL_IN to signal a valid
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input VAL_IN; // Assert VAL_IN to signal a valid
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input value. The module will only
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input value. The module will only
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accept input when RDY_IN is asserted.
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accept input when RDY_IN is asserted.
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If RDY_IN is low, then VAL_IN should
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If RDY_IN is low, then VAL_IN should
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remain asserted until RDY_IN goes
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remain asserted until RDY_IN goes
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high. VAL_IN and RDY_IN must both be
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high. VAL_IN and RDY_IN must both be
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asserted for one clock cycle for
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asserted for one clock cycle for
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computation to begin.
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computation to begin.
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output wire RDY_IN; // module is ready to accept input
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output wire RDY_IN; // module is ready to accept input
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input CLK; // clock
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input CLK; // clock
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output reg [bitlength-1:0] D_OUT; // single or double precision output
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output reg [bitlength-1:0] D_OUT; // single or double precision output
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output reg VAL_OUT; // VAL_OUT is asserted when the output
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output reg VAL_OUT; // VAL_OUT is asserted when the output
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is valid. VAL_OUT will remain asserted
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is valid. VAL_OUT will remain asserted
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and D_OUT will persist until VAL_OUT and
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and D_OUT will persist until VAL_OUT and
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RDY_OUT have both been asserted for one
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RDY_OUT have both been asserted for one
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clock cycle.
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clock cycle.
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input RDY_OUT; // when asserted, downstream logic is
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input RDY_OUT; // when asserted, downstream logic is
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ready to accept output of module
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ready to accept output of module
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This core was designed using synchronous resets, for use in FPGAs. The
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This core was designed using synchronous resets, for use in FPGAs. The
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synchronous resets could easily be made asynchronous for use in ASICs by
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synchronous resets could easily be made asynchronous for use in ASICs by
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editing the always @ (posedge CLK) blocks in this and all dependant files.
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editing the always @ (posedge CLK) blocks in this and all dependant files.
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Resource Utilization:
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Resource Utilization:
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(synthesized with XST for Virtex4 - no architectural dependancies exist in this core
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(synthesized with XST for Virtex4 - no architectural dependancies exist in this core
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- this is merely an example)
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- this is merely an example)
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Single Precision:
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Single Precision:
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Slices: 155
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Slices: 155
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Flip Flops: 204
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Flip Flops: 204
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4-Input LUTs: 269
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4-Input LUTs: 269
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Double Precision:
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Double Precision:
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Slices: 324
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Slices: 324
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Flip Flops: 417
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Flip Flops: 417
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4-Input LUTs: 566
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4-Input LUTs: 566
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Both numerical accuracy and performance of the single and double precision versions of
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Both numerical accuracy and performance of the single and double precision versions of
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this core have been verified in a Xilinx XC4VLX25-10 at 100MHz. Without optimizations,
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this core have been verified in a Xilinx XC4VLX25-10 at 100MHz. Without optimizations,
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the single precision core should operate at up to at least 190MHz, and the double precision
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the single precision core should operate at up to at least 190MHz, and the double precision
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core should operate at up to at least 134MHz in this platform. Higher performance should
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core should operate at up to at least 134MHz in this platform. Higher performance should
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be possible with a little effort.
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be possible with a little effort.
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This module uses the following files:
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This module uses the following files:
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|
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sbd_sqrt_fp_calc_mant.v
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sbd_sqrt_fp_calc_mant.v
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sbd_sqrt_fp_state_mach.v
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sbd_sqrt_fp_state_mach.v
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sbd_shifter_left2.v
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sbd_shifter_left2.v
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sbd_shifter_left3_right2.v
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sbd_shifter_left3_right2.v
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sbd_adsu.v
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sbd_adsu.v
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Copyright (C) 2005 Samuel Brown
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Copyright (C) 2005 Samuel Brown
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sam.brown@sbdesign.org
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sam.brown@sbdesign.org
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This library is free software; you can redistribute it and/or
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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modify it under the terms of the GNU Lesser General Public
|
License as published by the Free Software Foundation; either
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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version 2.1 of the License, or (at your option) any later version.
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|
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This library is distributed in the hope that it will be useful,
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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Lesser General Public License for more details.
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|
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You should have received a copy of the GNU Lesser General Public
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You should have received a copy of the GNU Lesser General Public
|
License along with this library; if not, write to the Free Software
|
License along with this library; if not, write to the Free Software
|
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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|
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****************************************************************************/
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****************************************************************************/
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module sbd_sqrt_fp ( D_IN, VAL_IN, RDY_IN, CLK, D_OUT, VAL_OUT, RDY_OUT );
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module sbd_sqrt_fp ( D_IN, VAL_IN, RDY_IN, CLK, D_OUT, VAL_OUT, RDY_OUT );
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|
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parameter bitlength = 32;
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parameter bitlength = 32;
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input [bitlength-1:0] D_IN;
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input [bitlength-1:0] D_IN;
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input VAL_IN;
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input VAL_IN;
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output wire RDY_IN;
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output wire RDY_IN;
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input CLK;
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input CLK;
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output reg [bitlength-1:0] D_OUT;
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output reg [bitlength-1:0] D_OUT;
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output reg VAL_OUT;
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output reg VAL_OUT;
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input RDY_OUT;
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input RDY_OUT;
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|
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reg [bitlength-1:0] raw_data_reg;
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reg [bitlength-1:0] raw_data_reg;
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reg beg_in_reg;
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reg beg_in_reg;
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reg d_rdy_reg;
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reg d_rdy_reg;
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wire mant_out;
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wire mant_out;
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reg mant_out_reg;
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reg mant_out_reg;
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wire [bitlength-1:0] sqrt_final;
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wire [bitlength-1:0] sqrt_final;
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|
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generate
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generate
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if(bitlength == 32)
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if(bitlength == 32)
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begin:single
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begin:single
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//------------------ Single Precision --------------------------------------
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//------------------ Single Precision --------------------------------------
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wire [7:0] exp_off, exp_adj, exp_final;
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wire [7:0] exp_off, exp_adj, exp_final;
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wire non_zero_exp = ~(!raw_data_reg[30:23]);
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wire non_zero_exp = ~(!raw_data_reg[30:23]);
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wire [23:0] mant_final;
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wire [23:0] mant_final;
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wire [22:0] mant_final_imp = mant_final[22:0];
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wire [22:0] mant_final_imp = mant_final[22:0];
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reg [23:0] mant_adj; // mantissa with explicit leading bit - adjusted
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reg [23:0] mant_adj; // mantissa with explicit leading bit - adjusted
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// for even/odd exponent
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// for even/odd exponent
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//------------ Exponent Calculation & Mantissa Preparation --------------
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//------------ Exponent Calculation & Mantissa Preparation --------------
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sbd_adsu exp_offset_adsu (
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sbd_adsu exp_offset_adsu (
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.A(raw_data_reg[30:23]),
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.A(raw_data_reg[30:23]),
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.B(8'h7F),
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.B(8'h7F),
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.ADD(1'b0),
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.ADD(1'b0),
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.C_IN(1'b1),
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.C_IN(1'b1),
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.S(exp_off));
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.S(exp_off));
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defparam exp_offset_adsu.bitlength = 8;
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defparam exp_offset_adsu.bitlength = 8;
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|
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sbd_adsu exp_adjust_adsu (
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sbd_adsu exp_adjust_adsu (
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.A(8'h7F),
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.A(8'h7F),
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.B({ exp_off[7], exp_off[7:1] }),
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.B({ exp_off[7], exp_off[7:1] }),
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.ADD(1'b1),
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.ADD(1'b1),
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.C_IN(1'b0),
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.C_IN(1'b0),
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.S(exp_adj));
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.S(exp_adj));
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defparam exp_adjust_adsu.bitlength = 8;
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defparam exp_adjust_adsu.bitlength = 8;
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|
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assign exp_final = exp_adj & {8{non_zero_exp}};
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assign exp_final = exp_adj & {8{non_zero_exp}};
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always @ (raw_data_reg, non_zero_exp)
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always @ (raw_data_reg, non_zero_exp)
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begin:mant_adj_mux
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begin:mant_adj_mux
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if(raw_data_reg[23]) mant_adj = { 1'b0, non_zero_exp, raw_data_reg[22:1] };
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if(raw_data_reg[23]) mant_adj = { 1'b0, non_zero_exp, raw_data_reg[22:1] };
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else mant_adj = { non_zero_exp, raw_data_reg[22:0] };
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else mant_adj = { non_zero_exp, raw_data_reg[22:0] };
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end
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end
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|
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//------------- Mantissa Calculation --------------------------------------
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//------------- Mantissa Calculation --------------------------------------
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|
|
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sbd_sqrt_fp_calc_mant mant_iterations (
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sbd_sqrt_fp_calc_mant mant_iterations (
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.MANT_IN(mant_adj),
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.MANT_IN(mant_adj),
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.CLK(CLK),
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.CLK(CLK),
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.VAL_IN(beg_in_reg),
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.VAL_IN(beg_in_reg),
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.MANT_OUT(mant_final),
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.MANT_OUT(mant_final),
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.VAL_OUT(mant_out));
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.VAL_OUT(mant_out));
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defparam mant_iterations.mantlength = 24;
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defparam mant_iterations.mantlength = 24;
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|
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assign sqrt_final = { raw_data_reg[bitlength-1], exp_final, mant_final_imp };
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assign sqrt_final = { raw_data_reg[bitlength-1], exp_final, mant_final_imp };
|
|
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end
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end
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else if(bitlength == 64)
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else if(bitlength == 64)
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begin:double
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begin:double
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|
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//------------------ Doule Precision ---------------------------------------
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//------------------ Doule Precision ---------------------------------------
|
|
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wire [10:0] exp_off, exp_adj, exp_final;
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wire [10:0] exp_off, exp_adj, exp_final;
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wire non_zero_exp = ~(!raw_data_reg[62:52]);
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wire non_zero_exp = ~(!raw_data_reg[62:52]);
|
|
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wire [52:0] mant_final;
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wire [52:0] mant_final;
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wire [51:0] mant_final_imp = mant_final[51:0];
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wire [51:0] mant_final_imp = mant_final[51:0];
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reg [52:0] mant_adj; // mantissa with explicit leading bit - adjusted
|
reg [52:0] mant_adj; // mantissa with explicit leading bit - adjusted
|
// for even/odd exponent
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// for even/odd exponent
|
|
|
//------------ Exponent Calculation & Mantissa Preparation --------------
|
//------------ Exponent Calculation & Mantissa Preparation --------------
|
|
|
sbd_adsu exp_offset_adsu (
|
sbd_adsu exp_offset_adsu (
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.A(raw_data_reg[62:52]),
|
.A(raw_data_reg[62:52]),
|
.B(11'h3FF),
|
.B(11'h3FF),
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.ADD(1'b0),
|
.ADD(1'b0),
|
.C_IN(1'b1),
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.C_IN(1'b1),
|
.S(exp_off));
|
.S(exp_off));
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defparam exp_offset_adsu.bitlength = 11;
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defparam exp_offset_adsu.bitlength = 11;
|
|
|
sbd_adsu exp_adjust_adsu (
|
sbd_adsu exp_adjust_adsu (
|
.A(11'h3FF),
|
.A(11'h3FF),
|
.B({ exp_off[10], exp_off[10:1] }),
|
.B({ exp_off[10], exp_off[10:1] }),
|
.ADD(1'b1),
|
.ADD(1'b1),
|
.C_IN(1'b0),
|
.C_IN(1'b0),
|
.S(exp_adj));
|
.S(exp_adj));
|
defparam exp_adjust_adsu.bitlength = 11;
|
defparam exp_adjust_adsu.bitlength = 11;
|
|
|
assign exp_final = exp_adj & {11{non_zero_exp}};
|
assign exp_final = exp_adj & {11{non_zero_exp}};
|
|
|
always @ (raw_data_reg, non_zero_exp)
|
always @ (raw_data_reg, non_zero_exp)
|
begin:mant_adj_mux
|
begin:mant_adj_mux
|
if(raw_data_reg[52]) mant_adj = { 1'b0, non_zero_exp, raw_data_reg[51:1] };
|
if(raw_data_reg[52]) mant_adj = { 1'b0, non_zero_exp, raw_data_reg[51:1] };
|
else mant_adj = { non_zero_exp, raw_data_reg[51:0] };
|
else mant_adj = { non_zero_exp, raw_data_reg[51:0] };
|
end
|
end
|
|
|
//------------- Mantissa Calculation --------------------------------------
|
//------------- Mantissa Calculation --------------------------------------
|
|
|
|
|
sbd_sqrt_fp_calc_mant mant_iterations (
|
sbd_sqrt_fp_calc_mant mant_iterations (
|
.MANT_IN(mant_adj),
|
.MANT_IN(mant_adj),
|
.CLK(CLK),
|
.CLK(CLK),
|
.VAL_IN(beg_in_reg),
|
.VAL_IN(beg_in_reg),
|
.MANT_OUT(mant_final),
|
.MANT_OUT(mant_final),
|
.VAL_OUT(mant_out));
|
.VAL_OUT(mant_out));
|
defparam mant_iterations.mantlength = 53;
|
defparam mant_iterations.mantlength = 53;
|
|
|
assign sqrt_final = { raw_data_reg[bitlength-1], exp_final, mant_final_imp };
|
assign sqrt_final = { raw_data_reg[bitlength-1], exp_final, mant_final_imp };
|
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
assign RDY_IN = ~d_rdy_reg;
|
assign RDY_IN = ~d_rdy_reg;
|
wire beg_in = VAL_IN & RDY_IN;
|
wire beg_in = VAL_IN & RDY_IN;
|
|
|
initial
|
initial
|
begin:simzero
|
begin:simzero
|
|
|
D_OUT <= 0;
|
D_OUT <= 0;
|
VAL_OUT <= 0;
|
VAL_OUT <= 0;
|
raw_data_reg <= 0;
|
raw_data_reg <= 0;
|
beg_in_reg <= 0;
|
beg_in_reg <= 0;
|
d_rdy_reg <= 0;
|
d_rdy_reg <= 0;
|
mant_out_reg <= 0;
|
mant_out_reg <= 0;
|
|
|
end
|
end
|
|
|
always @ (posedge CLK)
|
always @ (posedge CLK)
|
begin:reg_input
|
begin:reg_input
|
// input buffer
|
// input buffer
|
if(beg_in) raw_data_reg <= D_IN;
|
if(beg_in) raw_data_reg <= D_IN;
|
|
|
// val delay
|
// val delay
|
beg_in_reg <= beg_in;
|
beg_in_reg <= beg_in;
|
|
|
// RDY state
|
// RDY state
|
if(mant_out) d_rdy_reg <= 0;
|
if(mant_out) d_rdy_reg <= 0;
|
else if(beg_in) d_rdy_reg <= 1;
|
else if(beg_in) d_rdy_reg <= 1;
|
|
|
// output registers
|
// output registers
|
if(mant_out_reg) D_OUT <= sqrt_final;
|
if(mant_out_reg) D_OUT <= sqrt_final;
|
if(VAL_OUT && RDY_OUT) VAL_OUT <= 0;
|
if(VAL_OUT && RDY_OUT) VAL_OUT <= 0;
|
else if(mant_out_reg) VAL_OUT <= 1;
|
else if(mant_out_reg) VAL_OUT <= 1;
|
|
|
//delay output latch
|
//delay output latch
|
mant_out_reg <= mant_out;
|
mant_out_reg <= mant_out;
|
|
|
end
|
end
|
|
|
|
|
endmodule
|
endmodule
|
|
|
